[llvm] [AMDGPU] Conditionally enable DAG combines for fminimum/fmaximum (PR #81584)

[Jay Foad via llvm-commits]

https://github.com/jayfoad created https://github.com/llvm/llvm-project/pull/81584

fminimum/fmaximum are only legal on some subtargets. This patch only
enables the DAG combines for fminimum3/fmaximum3 on those subtargets.

Without this, the combine can kick in before legalization, and then
nothing will legalize the target-specific fminimum3/fmaximum3 nodes.


>From 001b68b1a6e1f7c8cf3cb6d6388cd38dd63deeff Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Tue, 13 Feb 2024 08:56:22 +0000
Subject: [PATCH] [AMDGPU] Conditionally enable DAG combines for
 fminimum/fmaximum

fminimum/fmaximum are only legal on some subtargets. This patch only
enables the DAG combines for fminimum3/fmaximum3 on those subtargets.

Without this, the combine can kick in before legalization, and then
nothing will legalize the target-specific fminimum3/fmaximum3 nodes.
---
 llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 83221f7ead37e1..2dde4d711ec3f7 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -890,8 +890,6 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
                        ISD::FMAXNUM,
                        ISD::FMINNUM_IEEE,
                        ISD::FMAXNUM_IEEE,
-                       ISD::FMINIMUM,
-                       ISD::FMAXIMUM,
                        ISD::FMA,
                        ISD::SMIN,
                        ISD::SMAX,
@@ -911,6 +909,8 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
                        ISD::EXTRACT_VECTOR_ELT,
                        ISD::INSERT_VECTOR_ELT,
                        ISD::FCOPYSIGN});
+  if (Subtarget->hasIEEEMinMax())
+    setTargetDAGCombine({ISD::FMINIMUM, ISD::FMAXIMUM});
 
   if (Subtarget->has16BitInsts() && !Subtarget->hasMed3_16())
     setTargetDAGCombine(ISD::FP_ROUND);