[llvm] AMDGPU/NFC: Remove some bits from TSFlags (PR #81525)

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Mon Feb 12 12:30:32 PST 2024


github-actions[bot] wrote:

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git-clang-format --diff ab702513f1ee2268ce216d11c310a08cae24a0e7 1c06810b36335708360303029852801ee53fb599 -- llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp llvm/lib/Target/AMDGPU/SIDefines.h llvm/lib/Target/AMDGPU/SIInstrInfo.cpp llvm/lib/Target/AMDGPU/SIInstrInfo.h llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 51df7897f8..7a6c28421c 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -845,13 +845,10 @@ public:
   // Most sopk treat the immediate as a signed 16-bit, however some
   // use it as unsigned.
   static bool sopkIsZext(unsigned Opcode) {
-    return Opcode == AMDGPU::S_CMPK_EQ_U32 ||
-           Opcode == AMDGPU::S_CMPK_LG_U32 ||
-           Opcode == AMDGPU::S_CMPK_GT_U32 ||
-           Opcode == AMDGPU::S_CMPK_GE_U32 ||
-           Opcode == AMDGPU::S_CMPK_LT_U32 ||
-           Opcode == AMDGPU::S_CMPK_LE_U32 ||
-           Opcode == AMDGPU:: S_GETREG_B32;
+    return Opcode == AMDGPU::S_CMPK_EQ_U32 || Opcode == AMDGPU::S_CMPK_LG_U32 ||
+           Opcode == AMDGPU::S_CMPK_GT_U32 || Opcode == AMDGPU::S_CMPK_GE_U32 ||
+           Opcode == AMDGPU::S_CMPK_LT_U32 || Opcode == AMDGPU::S_CMPK_LE_U32 ||
+           Opcode == AMDGPU::S_GETREG_B32;
   }
 
   /// \returns true if this is an s_store_dword* instruction. This is more

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https://github.com/llvm/llvm-project/pull/81525


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