[llvm] 0b6e040 - [RISCV] Exclude X1 and X5 from register scavenging for long branch. (#80215)

[via llvm-commits]

Author: Craig Topper
Date: 2024-02-12T09:17:50-08:00
New Revision: 0b6e04005ca0eab7c5566950d8595379a9f72d41

URL: https://github.com/llvm/llvm-project/commit/0b6e04005ca0eab7c5566950d8595379a9f72d41
DIFF: https://github.com/llvm/llvm-project/commit/0b6e04005ca0eab7c5566950d8595379a9f72d41.diff

LOG: [RISCV] Exclude X1 and X5 from register scavenging for long branch. (#80215)

When a branch target is too far away we need to emit an indirect branch.
We scavenge a register for this since we don't know we need this until
after register allocation.

Jumps using X1 and X5 as the source are hints to the hardware to pop the
return-address stack. We should avoiding using them for jumps that
aren't a return or tail call.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 89eb71d917428e..225a9db8f3ee11 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1115,7 +1115,7 @@ void RISCVInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
   // FIXME: A virtual register must be used initially, as the register
   // scavenger won't work with empty blocks (SIInstrInfo::insertIndirectBranch
   // uses the same workaround).
-  Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
+  Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRJALRRegClass);
   auto II = MBB.end();
   // We may also update the jump target to RestoreBB later.
   MachineInstr &MI = *BuildMI(MBB, II, DL, get(RISCV::PseudoJump))