[llvm] [AArch64][GlobalISel] Legalize Insert vector element (PR #81453)

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git-clang-format --diff 1c48c9234b3e30e6ed5b9a0ce68320579bb6fec7 5fe4d0b7196ef89f8a528f6d51fdd302af2ce2bf -- llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index d6978bf90a..735a24c298 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -2137,7 +2137,8 @@ bool AArch64InstructionSelector::preISelLower(MachineInstr &I) {
       Register ExtDst = Ext.getReg(0);
       MRI.setRegBank(ExtDst, RBI.getRegBank(AArch64::GPRRegBankID));
       if (!select(*Ext)) {
-        LLVM_DEBUG(dbgs() << "Failed to select G_ANYEXT in G_INSERT_VECTOR_ELT");
+        LLVM_DEBUG(
+            dbgs() << "Failed to select G_ANYEXT in G_INSERT_VECTOR_ELT");
         return false;
       }
       I.getOperand(2).setReg(ExtDst);
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index b545c04e16..e57108b3a7 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -870,7 +870,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
       .clampMaxNumElements(1, p0, 2);
 
   getActionDefinitionsBuilder(G_INSERT_VECTOR_ELT)
-      .legalIf(typeInSet(0, {v16s8, v8s8, v8s16, v4s16, v4s32, v2s32, v2s64, v2p0}))
+      .legalIf(
+          typeInSet(0, {v16s8, v8s8, v8s16, v4s16, v4s32, v2s32, v2s64, v2p0}))
       .widenVectorEltsToVectorMinSize(0, 64)
       .moreElementsToNextPow2(0)
       .clampNumElements(0, v8s8, v16s8)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
index a12cac010f..34f3f222dc 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
@@ -36,8 +36,8 @@
 #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
 #include "llvm/CodeGen/GlobalISel/Utils.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/TargetOpcodes.h"

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https://github.com/llvm/llvm-project/pull/81453