[llvm] [AArch64][GlobalISel] Expand abs.v4i8 to v4i16 and abs.v2s16 to v2s32 (PR #81231)

[Dhruv Chawla via llvm-commits]

dc03-work wrote:

> I'm not sure we want to promote (elements) as opposed to widen (the vector). Promote is what SDAG does, and there are advantages in places (notably that is how args are passed but I've seen other cases where it does work quite well too, usually when the code is already extending the v4i8 to a larger type). But it is certainly not optimal in all cases: https://godbolt.org/z/5bnWxqc4x.
> 
> I think the reason the existing code is falling back is because there is an anyext between the arg and the abs. Which presumably we will need to fix in any case?

I did try using `moreElementsIf` to unconditionally widen a `<4 x i8>` vector to `<8 x i8>`, however that is also causing fallback to SDAG. I'm not sure what would need to be done for the trunc/anyext pair because those are caused by the ABI.

For now, I think it would be best to remain conservative and follow what SDAG already does. Maybe a smarter way to do this would be to make a decision based on detecting when values are coming through formal arguments vs. being declared locally in the function?

https://github.com/llvm/llvm-project/pull/81231