[llvm] [AMDGPU][MC] Support src modifiers for v_mov_b32 and v_movrel* instructions (PR #76498)
Joe Nash via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 9 11:35:52 PST 2024
================
@@ -2358,24 +2358,51 @@
# GFX12: v_movreld_b32_e64 v255, 0xaf123456 ; encoding: [0xff,0x00,0xc2,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf]
0xff,0x00,0xc2,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf
+# GFX12: v_movreld_b32_e64 v5, -v1 ; encoding: [0x05,0x00,0xc2,0xd5,0x01,0x01,0x00,0x20]
+0x05,0x00,0xc2,0xd5,0x01,0x01,0x00,0x20
+
+# GFX12: v_movreld_b32_e64 v5, |v2| ; encoding: [0x05,0x01,0xc2,0xd5,0x02,0x01,0x00,0x00]
+0x05,0x01,0xc2,0xd5,0x02,0x01,0x00,0x00
+
+# GFX12: v_movreld_b32_e64 v5, -s1 ; encoding: [0x05,0x00,0xc2,0xd5,0x01,0x00,0x00,0x20]
+0x05,0x00,0xc2,0xd5,0x01,0x00,0x00,0x20
+
# GFX12: v_movrels_b32_e64 v5, v1 ; encoding: [0x05,0x00,0xc3,0xd5,0x01,0x01,0x00,0x00]
0x05,0x00,0xc3,0xd5,0x01,0x01,0x00,0x00
# GFX12: v_movrels_b32_e64 v255, v255 ; encoding: [0xff,0x00,0xc3,0xd5,0xff,0x01,0x00,0x00]
0xff,0x00,0xc3,0xd5,0xff,0x01,0x00,0x00
+# GFX12: v_movrels_b32_e64 v5, -v1 ; encoding: [0x05,0x00,0xc3,0xd5,0x01,0x01,0x00,0x20]
+0x05,0x00,0xc3,0xd5,0x01,0x01,0x00,0x20
+
+# GFX12: v_movrels_b32_e64 v5, |v2| ; encoding: [0x05,0x01,0xc3,0xd5,0x02,0x01,0x00,0x00]
+0x05,0x01,0xc3,0xd5,0x02,0x01,0x00,0x00
+
# GFX12: v_movrelsd_2_b32_e64 v5, v1 ; encoding: [0x05,0x00,0xc8,0xd5,0x01,0x01,0x00,0x00]
0x05,0x00,0xc8,0xd5,0x01,0x01,0x00,0x00
# GFX12: v_movrelsd_2_b32_e64 v255, v255 ; encoding: [0xff,0x00,0xc8,0xd5,0xff,0x01,0x00,0x00]
0xff,0x00,0xc8,0xd5,0xff,0x01,0x00,0x00
+# GFX12: v_movrelsd_2_b32_e64_dpp v5, -v1 dpp8:[7,6,5,4,3,2,1,0]
+[0x05,0x00,0xc8,0xd5,0xe9,0x00,0x00,0x20,0x01,0x77,0x39,0x05]
+
+# GFX12: _movrelsd_2_b32_e64_dpp v5, |v1| dpp8:[7,6,5,4,3,2,1,0]
----------------
Sisyph wrote:
typo in the check line, 'v' is missing. And these dpp8 tests should go in the file llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp8.txt
https://github.com/llvm/llvm-project/pull/76498
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