[llvm] [SelectionDAG] Support integer promotion for VP_LOAD and VP_STORE (PR #81299)
Lei Huang via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 9 10:54:54 PST 2024
https://github.com/lei137 created https://github.com/llvm/llvm-project/pull/81299
Add integer promotion support for VP_LOAD and VP_STORE via legalization of extend and truncate of each form.
Patch commandeered from: https://reviews.llvm.org/D109377
>From be606c29c6d4586514aeb275735022522db62582 Mon Sep 17 00:00:00 2001
From: Lei Huang <lei at ca.ibm.com>
Date: Thu, 8 Feb 2024 09:39:51 -0500
Subject: [PATCH] [SelectionDAG] Support integer promotion for VP_LOAD and
VP_STORE
Add integer promotion support for VP_LOAD and VP_STORE via
legalization of extend and truncate of each form.
Patch commandeered from: https://reviews.llvm.org/D109377
---
.../SelectionDAG/LegalizeIntegerTypes.cpp | 70 +++++++++++++++++++
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h | 3 +
.../CodeGen/RISCV/rvv/fixed-vectors-vpload.ll | 28 +++++---
.../RISCV/rvv/fixed-vectors-vpstore.ll | 16 ++++-
llvm/test/CodeGen/RISCV/rvv/vpload.ll | 28 +++++---
llvm/test/CodeGen/RISCV/rvv/vpstore.ll | 28 +++++---
6 files changed, 147 insertions(+), 26 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 39b7e061554141..041f14144d10ef 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -79,6 +79,9 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
case ISD::EXTRACT_VECTOR_ELT:
Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N)); break;
+ case ISD::VP_LOAD:
+ Res = PromoteIntRes_VP_LOAD(cast<VPLoadSDNode>(N));
+ break;
case ISD::MLOAD: Res = PromoteIntRes_MLOAD(cast<MaskedLoadSDNode>(N));
break;
case ISD::MGATHER: Res = PromoteIntRes_MGATHER(cast<MaskedGatherSDNode>(N));
@@ -866,6 +869,23 @@ SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
return Res;
}
+SDValue DAGTypeLegalizer::PromoteIntRes_VP_LOAD(VPLoadSDNode *N) {
+ assert(!N->isIndexed() && "Indexed vp_load during type legalization!");
+ EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
+ ISD::LoadExtType ExtType = (N->getExtensionType() == ISD::NON_EXTLOAD)
+ ? ISD::EXTLOAD
+ : N->getExtensionType();
+ SDLoc dl(N);
+ SDValue Res =
+ DAG.getLoadVP(N->getAddressingMode(), ExtType, NVT, dl, N->getChain(),
+ N->getBasePtr(), N->getOffset(), N->getMask(),
+ N->getVectorLength(), N->getMemoryVT(), N->getMemOperand());
+ // Legalize the chain result - switch anything that used the old chain to
+ // use the new one.
+ ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
+ return Res;
+}
+
SDValue DAGTypeLegalizer::PromoteIntRes_MLOAD(MaskedLoadSDNode *N) {
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
SDValue ExtPassThru = GetPromotedInteger(N->getPassThru());
@@ -1802,8 +1822,14 @@ bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
case ISD::STRICT_SINT_TO_FP: Res = PromoteIntOp_STRICT_SINT_TO_FP(N); break;
case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
OpNo); break;
+ case ISD::VP_STORE:
+ Res = PromoteIntOp_VP_STORE(cast<VPStoreSDNode>(N), OpNo);
+ break;
case ISD::MSTORE: Res = PromoteIntOp_MSTORE(cast<MaskedStoreSDNode>(N),
OpNo); break;
+ case ISD::VP_LOAD:
+ Res = PromoteIntOp_VP_LOAD(cast<VPLoadSDNode>(N), OpNo);
+ break;
case ISD::MLOAD: Res = PromoteIntOp_MLOAD(cast<MaskedLoadSDNode>(N),
OpNo); break;
case ISD::MGATHER: Res = PromoteIntOp_MGATHER(cast<MaskedGatherSDNode>(N),
@@ -2194,6 +2220,50 @@ SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
N->getMemoryVT(), N->getMemOperand());
}
+SDValue DAGTypeLegalizer::PromoteIntOp_VP_STORE(VPStoreSDNode *N,
+ unsigned OpNo) {
+ SDValue DataOp = N->getValue();
+ SDValue Operand = N->getOperand(OpNo);
+
+ if (OpNo >= 4) {
+ // The Mask or EVL. Update in place.
+ EVT DataVT = DataOp.getValueType();
+ SDValue PromotedOperand = OpNo == 4 ? PromoteTargetBoolean(Operand, DataVT)
+ : ZExtPromotedInteger(Operand);
+ SmallVector<SDValue, 6> NewOps(N->op_begin(), N->op_end());
+ NewOps[OpNo] = PromotedOperand;
+ return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
+ }
+
+ assert(OpNo == 1 && "Unexpected operand for promotion");
+ DataOp = GetPromotedInteger(DataOp);
+
+ assert(!N->isIndexed() && "expecting unindexed vp_store!");
+
+ return DAG.getTruncStoreVP(N->getChain(), SDLoc(N), DataOp, N->getBasePtr(),
+ N->getMask(), N->getVectorLength(),
+ N->getMemoryVT(), N->getMemOperand(),
+ N->isCompressingStore());
+}
+
+SDValue DAGTypeLegalizer::PromoteIntOp_VP_LOAD(VPLoadSDNode *N, unsigned OpNo) {
+ assert(OpNo >= 3 && "Only know how to promote the mask or length!");
+ EVT DataVT = N->getValueType(0);
+ SDValue Operand = N->getOperand(OpNo);
+ SDValue PromotedOperand = OpNo == 3 ? PromoteTargetBoolean(Operand, DataVT)
+ : ZExtPromotedInteger(Operand);
+ SmallVector<SDValue, 5> NewOps(N->op_begin(), N->op_end());
+ NewOps[OpNo] = PromotedOperand;
+ SDNode *Res = DAG.UpdateNodeOperands(N, NewOps);
+ if (Res == N)
+ return SDValue(Res, 0);
+
+ // Update triggered CSE, do our own replacement since caller can't.
+ ReplaceValueWith(SDValue(N, 0), SDValue(Res, 0));
+ ReplaceValueWith(SDValue(N, 1), SDValue(Res, 1));
+ return SDValue();
+}
+
SDValue DAGTypeLegalizer::PromoteIntOp_MSTORE(MaskedStoreSDNode *N,
unsigned OpNo) {
SDValue DataOp = N->getValue();
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index 09f0bca8b8611e..c4f64096b01cc5 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -331,6 +331,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue PromoteIntRes_FREEZE(SDNode *N);
SDValue PromoteIntRes_INT_EXTEND(SDNode *N);
SDValue PromoteIntRes_LOAD(LoadSDNode *N);
+ SDValue PromoteIntRes_VP_LOAD(VPLoadSDNode *N);
SDValue PromoteIntRes_MLOAD(MaskedLoadSDNode *N);
SDValue PromoteIntRes_MGATHER(MaskedGatherSDNode *N);
SDValue PromoteIntRes_Overflow(SDNode *N);
@@ -407,6 +408,8 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue PromoteIntOp_ExpOp(SDNode *N);
SDValue PromoteIntOp_VECREDUCE(SDNode *N);
SDValue PromoteIntOp_VP_REDUCE(SDNode *N, unsigned OpNo);
+ SDValue PromoteIntOp_VP_STORE(VPStoreSDNode *N, unsigned OpNo);
+ SDValue PromoteIntOp_VP_LOAD(VPLoadSDNode *N, unsigned OpNo);
SDValue PromoteIntOp_SET_ROUNDING(SDNode *N);
SDValue PromoteIntOp_STACKMAP(SDNode *N, unsigned OpNo);
SDValue PromoteIntOp_PATCHPOINT(SDNode *N, unsigned OpNo);
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
index bb213c9276a3a9..806be381e4731d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll
@@ -52,6 +52,18 @@ define <4 x i8> @vpload_v4i8_allones_mask(ptr %ptr, i32 zeroext %evl) {
ret <4 x i8> %load
}
+declare <8 x i7> @llvm.vp.load.v8i7.p0v8i7(<8 x i7>*, <8 x i1>, i32)
+
+define <8 x i7> @vpload_v8i7(<8 x i7>* %ptr, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpload_v8i7:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
+; CHECK-NEXT: vle8.v v8, (a0), v0.t
+; CHECK-NEXT: ret
+ %load = call <8 x i7> @llvm.vp.load.v8i7.p0v8i7(<8 x i7>* %ptr, <8 x i1> %m, i32 %evl)
+ ret <8 x i7> %load
+}
+
declare <8 x i8> @llvm.vp.load.v8i8.p0(ptr, <8 x i1>, i32)
define <8 x i8> @vpload_v8i8(ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {
@@ -383,10 +395,10 @@ define <32 x double> @vpload_v32f64(ptr %ptr, <32 x i1> %m, i32 zeroext %evl) {
; CHECK: # %bb.0:
; CHECK-NEXT: li a3, 16
; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: bltu a1, a3, .LBB31_2
+; CHECK-NEXT: bltu a1, a3, .LBB32_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: .LBB31_2:
+; CHECK-NEXT: .LBB32_2:
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v8, (a0), v0.t
; CHECK-NEXT: addi a2, a1, -16
@@ -413,10 +425,10 @@ define <33 x double> @vpload_v33f64(ptr %ptr, <33 x i1> %m, i32 zeroext %evl) {
; CHECK-NEXT: li a4, 32
; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: mv a3, a2
-; CHECK-NEXT: bltu a2, a4, .LBB32_2
+; CHECK-NEXT: bltu a2, a4, .LBB33_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a3, 32
-; CHECK-NEXT: .LBB32_2:
+; CHECK-NEXT: .LBB33_2:
; CHECK-NEXT: addi a4, a3, -16
; CHECK-NEXT: sltu a5, a3, a4
; CHECK-NEXT: addi a5, a5, -1
@@ -431,19 +443,19 @@ define <33 x double> @vpload_v33f64(ptr %ptr, <33 x i1> %m, i32 zeroext %evl) {
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a4, a2, a4
; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: bltu a4, a2, .LBB32_4
+; CHECK-NEXT: bltu a4, a2, .LBB33_4
; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: li a4, 16
-; CHECK-NEXT: .LBB32_4:
+; CHECK-NEXT: .LBB33_4:
; CHECK-NEXT: addi a5, a1, 256
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v8, 4
; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v24, (a5), v0.t
-; CHECK-NEXT: bltu a3, a2, .LBB32_6
+; CHECK-NEXT: bltu a3, a2, .LBB33_6
; CHECK-NEXT: # %bb.5:
; CHECK-NEXT: li a3, 16
-; CHECK-NEXT: .LBB32_6:
+; CHECK-NEXT: .LBB33_6:
; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vle64.v v8, (a1), v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll
index d7643bc3041832..3e0d4e00873103 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll
@@ -28,6 +28,18 @@ define void @vpstore_v4i8(<4 x i8> %val, ptr %ptr, <4 x i1> %m, i32 zeroext %evl
ret void
}
+declare void @llvm.vp.store.v8i7.v8i7.p0(<8 x i7>, <8 x i7>*, <8 x i1>, i32)
+
+define void @vpstore_v8i7(<8 x i7> %val, <8 x i7>* %ptr, <8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpstore_v8i7:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
+; CHECK-NEXT: vse8.v v8, (a0), v0.t
+; CHECK-NEXT: ret
+ call void @llvm.vp.store.v8i7.v8i7.p0(<8 x i7> %val, <8 x i7>* %ptr, <8 x i1> %m, i32 %evl)
+ ret void
+}
+
declare void @llvm.vp.store.v8i8.p0(<8 x i8>, ptr, <8 x i1>, i32)
define void @vpstore_v8i8(<8 x i8> %val, ptr %ptr, <8 x i1> %m, i32 zeroext %evl) {
@@ -287,10 +299,10 @@ define void @vpstore_v32f64(<32 x double> %val, ptr %ptr, <32 x i1> %m, i32 zero
; CHECK: # %bb.0:
; CHECK-NEXT: li a3, 16
; CHECK-NEXT: mv a2, a1
-; CHECK-NEXT: bltu a1, a3, .LBB23_2
+; CHECK-NEXT: bltu a1, a3, .LBB24_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 16
-; CHECK-NEXT: .LBB23_2:
+; CHECK-NEXT: .LBB24_2:
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vse64.v v8, (a0), v0.t
; CHECK-NEXT: addi a2, a1, -16
diff --git a/llvm/test/CodeGen/RISCV/rvv/vpload.ll b/llvm/test/CodeGen/RISCV/rvv/vpload.ll
index c203fcb903e56c..8e3795b71803de 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vpload.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vpload.ll
@@ -52,6 +52,18 @@ define <vscale x 3 x i8> @vpload_nxv3i8(ptr %ptr, <vscale x 3 x i1> %m, i32 zero
ret <vscale x 3 x i8> %load
}
+declare <vscale x 4 x i6> @llvm.vp.load.nxv4i6.nxv4i6.p0(<vscale x 4 x i6>*, <vscale x 4 x i1>, i32)
+
+define <vscale x 4 x i6> @vpload_nxv4i6(<vscale x 4 x i6>* %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpload_nxv4i6:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
+; CHECK-NEXT: vle8.v v8, (a0), v0.t
+; CHECK-NEXT: ret
+ %load = call <vscale x 4 x i6> @llvm.vp.load.nxv4i6.nxv4i6.p0(<vscale x 4 x i6>* %ptr, <vscale x 4 x i1> %m, i32 %evl)
+ ret <vscale x 4 x i6> %load
+}
+
declare <vscale x 4 x i8> @llvm.vp.load.nxv4i8.p0(ptr, <vscale x 4 x i1>, i32)
define <vscale x 4 x i8> @vpload_nxv4i8(ptr %ptr, <vscale x 4 x i1> %m, i32 zeroext %evl) {
@@ -466,10 +478,10 @@ define <vscale x 16 x double> @vpload_nxv16f64(ptr %ptr, <vscale x 16 x i1> %m,
; CHECK-NEXT: vslidedown.vx v0, v0, a5
; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v16, (a4), v0.t
-; CHECK-NEXT: bltu a1, a2, .LBB37_2
+; CHECK-NEXT: bltu a1, a2, .LBB38_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a1, a2
-; CHECK-NEXT: .LBB37_2:
+; CHECK-NEXT: .LBB38_2:
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vle64.v v8, (a0), v0.t
@@ -496,10 +508,10 @@ define <vscale x 16 x double> @vpload_nxv17f64(ptr %ptr, ptr %out, <vscale x 17
; CHECK-NEXT: slli a5, a3, 1
; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: mv a4, a2
-; CHECK-NEXT: bltu a2, a5, .LBB38_2
+; CHECK-NEXT: bltu a2, a5, .LBB39_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a4, a5
-; CHECK-NEXT: .LBB38_2:
+; CHECK-NEXT: .LBB39_2:
; CHECK-NEXT: sub a6, a4, a3
; CHECK-NEXT: sltu a7, a4, a6
; CHECK-NEXT: addi a7, a7, -1
@@ -515,10 +527,10 @@ define <vscale x 16 x double> @vpload_nxv17f64(ptr %ptr, ptr %out, <vscale x 17
; CHECK-NEXT: sltu a2, a2, a5
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a5
-; CHECK-NEXT: bltu a2, a3, .LBB38_4
+; CHECK-NEXT: bltu a2, a3, .LBB39_4
; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: mv a2, a3
-; CHECK-NEXT: .LBB38_4:
+; CHECK-NEXT: .LBB39_4:
; CHECK-NEXT: slli a5, a3, 4
; CHECK-NEXT: add a5, a0, a5
; CHECK-NEXT: srli a6, a3, 2
@@ -526,10 +538,10 @@ define <vscale x 16 x double> @vpload_nxv17f64(ptr %ptr, ptr %out, <vscale x 17
; CHECK-NEXT: vslidedown.vx v0, v8, a6
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v24, (a5), v0.t
-; CHECK-NEXT: bltu a4, a3, .LBB38_6
+; CHECK-NEXT: bltu a4, a3, .LBB39_6
; CHECK-NEXT: # %bb.5:
; CHECK-NEXT: mv a4, a3
-; CHECK-NEXT: .LBB38_6:
+; CHECK-NEXT: .LBB39_6:
; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vle64.v v8, (a0), v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/vpstore.ll b/llvm/test/CodeGen/RISCV/rvv/vpstore.ll
index 8b27a61e243db1..10a9ea1c6413c3 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vpstore.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vpstore.ll
@@ -100,6 +100,18 @@ define void @vpstore_nxv4i16(<vscale x 4 x i16> %val, ptr %ptr, <vscale x 4 x i1
ret void
}
+declare void @llvm.vp.store.nxv8i12.nxv8i12.p0(<vscale x 8 x i12>, <vscale x 8 x i12>*, <vscale x 8 x i1>, i32)
+
+define void @vpstore_nxv8i12(<vscale x 8 x i12> %val, <vscale x 8 x i12>* %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {
+; CHECK-LABEL: vpstore_nxv8i12:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
+; CHECK-NEXT: vse16.v v8, (a0), v0.t
+; CHECK-NEXT: ret
+ call void @llvm.vp.store.nxv8i12.nxv8i12.p0(<vscale x 8 x i12> %val, <vscale x 8 x i12>* %ptr, <vscale x 8 x i1> %m, i32 %evl)
+ ret void
+}
+
declare void @llvm.vp.store.nxv8i16.p0(<vscale x 8 x i16>, ptr, <vscale x 8 x i1>, i32)
define void @vpstore_nxv8i16(<vscale x 8 x i16> %val, ptr %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) {
@@ -371,10 +383,10 @@ define void @vpstore_nxv16f64(<vscale x 16 x double> %val, ptr %ptr, <vscale x 1
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: mv a3, a1
-; CHECK-NEXT: bltu a1, a2, .LBB30_2
+; CHECK-NEXT: bltu a1, a2, .LBB31_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a3, a2
-; CHECK-NEXT: .LBB30_2:
+; CHECK-NEXT: .LBB31_2:
; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; CHECK-NEXT: vse64.v v8, (a0), v0.t
; CHECK-NEXT: sub a3, a1, a2
@@ -404,15 +416,15 @@ define void @vpstore_nxv17f64(<vscale x 17 x double> %val, ptr %ptr, <vscale x 1
; CHECK-NEXT: slli a4, a3, 1
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: mv a5, a2
-; CHECK-NEXT: bltu a2, a4, .LBB31_2
+; CHECK-NEXT: bltu a2, a4, .LBB32_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a5, a4
-; CHECK-NEXT: .LBB31_2:
+; CHECK-NEXT: .LBB32_2:
; CHECK-NEXT: mv a6, a5
-; CHECK-NEXT: bltu a5, a3, .LBB31_4
+; CHECK-NEXT: bltu a5, a3, .LBB32_4
; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: mv a6, a3
-; CHECK-NEXT: .LBB31_4:
+; CHECK-NEXT: .LBB32_4:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a7, vlenb
@@ -440,10 +452,10 @@ define void @vpstore_nxv17f64(<vscale x 17 x double> %val, ptr %ptr, <vscale x 1
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a0, a2, a0
; CHECK-NEXT: vse64.v v16, (a5), v0.t
-; CHECK-NEXT: bltu a0, a3, .LBB31_6
+; CHECK-NEXT: bltu a0, a3, .LBB32_6
; CHECK-NEXT: # %bb.5:
; CHECK-NEXT: mv a0, a3
-; CHECK-NEXT: .LBB31_6:
+; CHECK-NEXT: .LBB32_6:
; CHECK-NEXT: slli a2, a3, 4
; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: srli a3, a3, 2
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