[llvm] [AMDGPU][DOC] Add MI200 Names to AMDGPUUsage Doc (PR #81252)
Corbin Robeck via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 9 06:36:42 PST 2024
https://github.com/CRobeck created https://github.com/llvm/llvm-project/pull/81252
None
>From b45292ac765a04a62e28e46226605f38200c2130 Mon Sep 17 00:00:00 2001
From: Corbin Robeck <13821049+CRobeck at users.noreply.github.com>
Date: Fri, 9 Feb 2024 09:35:43 -0500
Subject: [PATCH] [AMDGPU][DOC] Add MI200 Names to AMDGPUUsage
---
llvm/docs/AMDGPUUsage.rst | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index 6b2417143ca06c..f463e83929eb80 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -357,12 +357,12 @@ Every processor supports every OS ABI (see :ref:`amdgpu-os`) with the following
Add product
names.
- ``gfx90a`` ``amdgcn`` dGPU - sramecc - Absolute - *rocm-amdhsa* *TBA*
- - tgsplit flat
- - xnack scratch .. TODO::
+ ``gfx90a`` ``amdgcn`` dGPU - sramecc - Absolute - *rocm-amdhsa* - AMD Instinct MI210 Accelerator
+ - tgsplit flat - *rocm-amdhsa* - AMD Instinct MI250 Accelerator
+ - xnack scratch - *rocm-amdhsa* - AMD Instinct MI250X Accelerator
- kernarg preload - Packed
- work-item Add product
- IDs names.
+ work-item
+ IDs
``gfx90c`` ``amdgcn`` APU - xnack - Absolute - *pal-amdpal* - Ryzen 7 4700G
flat - Ryzen 7 4700GE
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