[llvm] f78c9b8 - [RISCV] Use MCPhysReg for AllPopRegs. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-02-08T13:50:44-08:00
New Revision: f78c9b88b7a1a54cf67037f9088a3e48779b1e44

URL: https://github.com/llvm/llvm-project/commit/f78c9b88b7a1a54cf67037f9088a3e48779b1e44
DIFF: https://github.com/llvm/llvm-project/commit/f78c9b88b7a1a54cf67037f9088a3e48779b1e44.diff

LOG: [RISCV] Use MCPhysReg for AllPopRegs. NFC

MCPhysReg is 2 bytes, while Register is 4 bytes.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index e5b510349e3dd0..b12b49797b0e09 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -42,7 +42,7 @@ RISCVFrameLowering::RISCVFrameLowering(const RISCVSubtarget &STI)
                           /*TransientStackAlignment=*/Align(16)),
       STI(STI) {}
 
-static const Register AllPopRegs[] = {
+static const MCPhysReg AllPopRegs[] = {
     RISCV::X1,  RISCV::X8,  RISCV::X9,  RISCV::X18, RISCV::X19,
     RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24,
     RISCV::X25, RISCV::X26, RISCV::X27};