[llvm] [AMDGPU][MC][True16] Support V_RCP/SQRT/RSQ/LOG/EXP_F16. (PR #81131)

[Joe Nash via llvm-commits]

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@@ -45,49 +46,64 @@
 # GFX11: v_bfrev_b32_e64 v255, 0xaf123456        ; encoding: [0xff,0x00,0xb8,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf]
 0xff,0x00,0xb8,0xd5,0xff,0x00,0x00,0x00,0x56,0x34,0x12,0xaf
 
-# GFX11: v_ceil_f16_e64 v5, v1                   ; encoding: [0x05,0x00,0xdc,0xd5,0x01,0x01,0x00,0x00]
+# GFX11-REAL16: v_ceil_f16_e64 v5.l, v1.l        ; encoding: [0x05,0x00,0xdc,0xd5,0x01,0x01,0x00,0x00]
+# GFX11-FAKE16: v_ceil_f16_e64 v5, v1            ; encoding: [0x05,0x00,0xdc,0xd5,0x01,0x01,0x00,0x00]
 0x05,0x00,0xdc,0xd5,0x01,0x01,0x00,0x00
 
-# GFX11: v_ceil_f16_e64 v5, v255                 ; encoding: [0x05,0x00,0xdc,0xd5,0xff,0x01,0x00,0x00]
+# GFX11-REAL16: v_ceil_f16_e64 v5.l, v255.l      ; encoding: [0x05,0x00,0xdc,0xd5,0xff,0x01,0x00,0x00]
+# GFX11-FAKE16: v_ceil_f16_e64 v5, v255          ; encoding: [0x05,0x00,0xdc,0xd5,0xff,0x01,0x00,0x00]
 0x05,0x00,0xdc,0xd5,0xff,0x01,0x00,0x00
 
-# GFX11: v_ceil_f16_e64 v5, s1                   ; encoding: [0x05,0x00,0xdc,0xd5,0x01,0x00,0x00,0x00]
+# GFX11-REAL16: v_ceil_f16_e64 v5.l, s1          ; encoding: [0x05,0x00,0xdc,0xd5,0x01,0x00,0x00,0x00]
+# GFX11-FAKE16: v_ceil_f16_e64 v5, s1            ; encoding: [0x05,0x00,0xdc,0xd5,0x01,0x00,0x00,0x00]
----------------
Sisyph wrote:

> > SGPRs use the opsel:[] syntax.
> 
> That's an odd choice, s0.l/s0.h would be much more readable and I don't see any downside to displaying sgprs and vgprs the same way.

Yep, I agree the .l/.h syntax would be better. It has not been a priority since it would only affect asm. We do not have codegen support for 16 bit sgprs coming any time soon. If you want to do any patches toward .l/.h syntax it would be welcome.

https://github.com/llvm/llvm-project/pull/81131