[llvm] [RISCV] Handle ADD in RISCVInstrInfo::isCopyInstrImpl (PR #81123)

[Craig Topper via llvm-commits]

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@@ -1579,6 +1579,12 @@ RISCVInstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
   switch (MI.getOpcode()) {
   default:
     break;
+  case RISCV::ADD:
+    if (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0)
+      return DestSourcePair{MI.getOperand(0), MI.getOperand(2)};
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topperc wrote:

Do we need to check that Operand 2 is a register?

https://github.com/llvm/llvm-project/pull/81123