[llvm] [RISCV][NFCI] Use isADDLike helper for or_is_add PatFrag (PR #81137)

[Alex Bradbury via llvm-commits]

https://github.com/asb created https://github.com/llvm/llvm-project/pull/81137

This should be equivalent.

>From 824e25f38905f81848d2b6d0aea0aa5fd0beb0e2 Mon Sep 17 00:00:00 2001
From: Alex Bradbury <asb at igalia.com>
Date: Thu, 8 Feb 2024 13:50:21 +0000
Subject: [PATCH] [RISCV][NFCI] Use isADDLike helper for or_is_add PatFrag

This should be equivalent.
---
 llvm/lib/Target/RISCV/RISCVInstrInfo.td | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 518982441e7c0..aa84a4553ec1f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1249,11 +1249,7 @@ def : PatGprUimmLog2XLen<sra, SRAI>;
 // Select 'or' as ADDI if the immediate bits are known to be 0 in $rs1. This
 // can improve compressibility.
 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
-  if (N->getFlags().hasDisjoint())
-    return true;
-  KnownBits Known0 = CurDAG->computeKnownBits(N->getOperand(0), 0);
-  KnownBits Known1 = CurDAG->computeKnownBits(N->getOperand(1), 0);
-  return KnownBits::haveNoCommonBitsSet(Known0, Known1);
+  return CurDAG->isADDLike(SDValue(N, 0));
 }]>;
 def : PatGprSimm12<or_is_add, ADDI>;