[llvm] [Xtensa] Initial codegen support from IR (PR #78548)
Andrei Safronov via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 7 15:21:16 PST 2024
https://github.com/andreisfr updated https://github.com/llvm/llvm-project/pull/78548
>From 22a85f7900b035b56da02b476b99dd865f007a09 Mon Sep 17 00:00:00 2001
From: Andrei Safronov <safronov at espressif.com>
Date: Sat, 27 Jan 2024 01:37:03 +0300
Subject: [PATCH 1/2] [Xtensa] Initial codegen support from IR.
Initial codegen support for IR tests. Added basic
implementation of the TargetFrameLowering, MCInstLower,
AsmPrinter, RegisterInfo, InstructionInfo,
TargetLowering, SelectionDAGISel.
---
llvm/lib/Target/Xtensa/CMakeLists.txt | 10 +++
llvm/lib/Target/Xtensa/Xtensa.h | 30 +++++++
llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp | 41 ++++++++++
llvm/lib/Target/Xtensa/XtensaAsmPrinter.h | 42 ++++++++++
.../lib/Target/Xtensa/XtensaFrameLowering.cpp | 44 ++++++++++
llvm/lib/Target/Xtensa/XtensaFrameLowering.h | 34 ++++++++
llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp | 81 +++++++++++++++++++
llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 60 ++++++++++++++
llvm/lib/Target/Xtensa/XtensaISelLowering.h | 40 +++++++++
llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp | 27 +++++++
llvm/lib/Target/Xtensa/XtensaInstrInfo.h | 43 ++++++++++
llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp | 62 ++++++++++++++
llvm/lib/Target/Xtensa/XtensaMCInstLower.h | 43 ++++++++++
llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp | 72 +++++++++++++++++
llvm/lib/Target/Xtensa/XtensaRegisterInfo.h | 56 +++++++++++++
llvm/lib/Target/Xtensa/XtensaSubtarget.cpp | 46 +++++++++++
llvm/lib/Target/Xtensa/XtensaSubtarget.h | 72 +++++++++++++++++
.../lib/Target/Xtensa/XtensaTargetMachine.cpp | 30 ++++++-
llvm/lib/Target/Xtensa/XtensaTargetMachine.h | 6 ++
llvm/test/CodeGen/Xtensa/lit.local.cfg | 2 +
llvm/test/CodeGen/Xtensa/simple.ll | 5 ++
21 files changed, 844 insertions(+), 2 deletions(-)
create mode 100644 llvm/lib/Target/Xtensa/Xtensa.h
create mode 100644 llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
create mode 100644 llvm/lib/Target/Xtensa/XtensaAsmPrinter.h
create mode 100644 llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp
create mode 100644 llvm/lib/Target/Xtensa/XtensaFrameLowering.h
create mode 100644 llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
create mode 100644 llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
create mode 100644 llvm/lib/Target/Xtensa/XtensaISelLowering.h
create mode 100644 llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
create mode 100644 llvm/lib/Target/Xtensa/XtensaInstrInfo.h
create mode 100644 llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp
create mode 100644 llvm/lib/Target/Xtensa/XtensaMCInstLower.h
create mode 100644 llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp
create mode 100644 llvm/lib/Target/Xtensa/XtensaRegisterInfo.h
create mode 100644 llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
create mode 100644 llvm/lib/Target/Xtensa/XtensaSubtarget.h
create mode 100644 llvm/test/CodeGen/Xtensa/lit.local.cfg
create mode 100644 llvm/test/CodeGen/Xtensa/simple.ll
diff --git a/llvm/lib/Target/Xtensa/CMakeLists.txt b/llvm/lib/Target/Xtensa/CMakeLists.txt
index 7192f7392072b3..5a4d0a5af8bd00 100644
--- a/llvm/lib/Target/Xtensa/CMakeLists.txt
+++ b/llvm/lib/Target/Xtensa/CMakeLists.txt
@@ -4,6 +4,7 @@ set(LLVM_TARGET_DEFINITIONS Xtensa.td)
tablegen(LLVM XtensaGenAsmMatcher.inc -gen-asm-matcher)
tablegen(LLVM XtensaGenAsmWriter.inc -gen-asm-writer)
+tablegen(LLVM XtensaGenDAGISel.inc -gen-dag-isel)
tablegen(LLVM XtensaGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM XtensaGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM XtensaGenMCCodeEmitter.inc -gen-emitter)
@@ -13,6 +14,14 @@ tablegen(LLVM XtensaGenSubtargetInfo.inc -gen-subtarget)
add_public_tablegen_target(XtensaCommonTableGen)
add_llvm_target(XtensaCodeGen
+ XtensaAsmPrinter.cpp
+ XtensaFrameLowering.cpp
+ XtensaInstrInfo.cpp
+ XtensaISelDAGToDAG.cpp
+ XtensaISelLowering.cpp
+ XtensaMCInstLower.cpp
+ XtensaRegisterInfo.cpp
+ XtensaSubtarget.cpp
XtensaTargetMachine.cpp
LINK_COMPONENTS
@@ -20,6 +29,7 @@ add_llvm_target(XtensaCodeGen
CodeGen
Core
MC
+ SelectionDAG
Support
Target
XtensaDesc
diff --git a/llvm/lib/Target/Xtensa/Xtensa.h b/llvm/lib/Target/Xtensa/Xtensa.h
new file mode 100644
index 00000000000000..1d6e2a2b32f152
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/Xtensa.h
@@ -0,0 +1,30 @@
+//===- Xtensa.h - Top-level interface for Xtensa representation -*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the entry points for global functions defined in
+// the LLVM Xtensa back-end.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_XTENSA_XTENSA_H
+#define LLVM_LIB_TARGET_XTENSA_XTENSA_H
+
+#include "MCTargetDesc/XtensaMCTargetDesc.h"
+#include "llvm/PassRegistry.h"
+#include "llvm/Support/CodeGen.h"
+
+namespace llvm {
+class XtensaTargetMachine;
+class FunctionPass;
+
+FunctionPass *createXtensaISelDag(XtensaTargetMachine &TM,
+ CodeGenOptLevel OptLevel);
+} // namespace llvm
+#endif // LLVM_LIB_TARGET_XTENSA_XTENSA_H
diff --git a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
new file mode 100644
index 00000000000000..fc681b1cbe8bd6
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
@@ -0,0 +1,41 @@
+//===- XtensaAsmPrinter.cpp Xtensa LLVM Assembly Printer ------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains a printer that converts from our internal representation
+// of machine-dependent LLVM code to GAS-format Xtensa assembly language.
+//
+//===----------------------------------------------------------------------===//
+
+#include "XtensaAsmPrinter.h"
+#include "TargetInfo/XtensaTargetInfo.h"
+#include "XtensaMCInstLower.h"
+#include "llvm/BinaryFormat/ELF.h"
+#include "llvm/CodeGen/MachineModuleInfoImpls.h"
+#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
+#include "llvm/MC/MCExpr.h"
+#include "llvm/MC/MCSectionELF.h"
+#include "llvm/MC/MCStreamer.h"
+#include "llvm/MC/MCSymbol.h"
+#include "llvm/MC/MCSymbolELF.h"
+#include "llvm/MC/TargetRegistry.h"
+
+using namespace llvm;
+
+void XtensaAsmPrinter::emitInstruction(const MachineInstr *MI) {
+ XtensaMCInstLower Lower(MF->getContext(), *this);
+ MCInst LoweredMI;
+ Lower.lower(MI, LoweredMI);
+ EmitToStreamer(*OutStreamer, LoweredMI);
+}
+
+// Force static initialization.
+extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXtensaAsmPrinter() {
+ RegisterAsmPrinter<XtensaAsmPrinter> A(getTheXtensaTarget());
+}
diff --git a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h
new file mode 100644
index 00000000000000..37ead2ddb37f11
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h
@@ -0,0 +1,42 @@
+//===- XtensaAsmPrinter.h - Xtensa LLVM Assembly Printer --------*- C++-*--===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// Xtensa Assembly printer class.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_XTENSA_XTENSAASMPRINTER_H
+#define LLVM_LIB_TARGET_XTENSA_XTENSAASMPRINTER_H
+
+#include "XtensaTargetMachine.h"
+#include "llvm/CodeGen/AsmPrinter.h"
+#include "llvm/Support/Compiler.h"
+
+namespace llvm {
+class MCStreamer;
+class MachineBasicBlock;
+class MachineInstr;
+class Module;
+class raw_ostream;
+
+class LLVM_LIBRARY_VISIBILITY XtensaAsmPrinter : public AsmPrinter {
+ const MCSubtargetInfo *STI;
+
+public:
+ explicit XtensaAsmPrinter(TargetMachine &TM,
+ std::unique_ptr<MCStreamer> Streamer)
+ : AsmPrinter(TM, std::move(Streamer)), STI(TM.getMCSubtargetInfo()) {}
+
+ StringRef getPassName() const override { return "Xtensa Assembly Printer"; }
+ void emitInstruction(const MachineInstr *MI) override;
+};
+} // end namespace llvm
+
+#endif /* LLVM_LIB_TARGET_XTENSA_XTENSAASMPRINTER_H */
diff --git a/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp
new file mode 100644
index 00000000000000..b201b99813ced1
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp
@@ -0,0 +1,44 @@
+//===- XtensaFrameLowering.cpp - Xtensa Frame Information -----------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the Xtensa implementation of TargetFrameLowering class.
+//
+//===----------------------------------------------------------------------===//
+
+#include "XtensaFrameLowering.h"
+#include "XtensaInstrInfo.h"
+#include "XtensaSubtarget.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/IR/Function.h"
+
+using namespace llvm;
+
+XtensaFrameLowering::XtensaFrameLowering()
+ : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, Align(4), 0,
+ Align(4)) {}
+
+// hasFP - Return true if the specified function should have a dedicated frame
+// pointer register. This is true if the function has variable sized allocas or
+// if frame pointer elimination is disabled.
+bool XtensaFrameLowering::hasFP(const MachineFunction &MF) const {
+ const MachineFrameInfo &MFI = MF.getFrameInfo();
+ return MF.getTarget().Options.DisableFramePointerElim(MF) ||
+ MFI.hasVarSizedObjects();
+}
+
+void XtensaFrameLowering::emitPrologue(MachineFunction &MF,
+ MachineBasicBlock &MBB) const {}
+
+void XtensaFrameLowering::emitEpilogue(MachineFunction &MF,
+ MachineBasicBlock &MBB) const {}
diff --git a/llvm/lib/Target/Xtensa/XtensaFrameLowering.h b/llvm/lib/Target/Xtensa/XtensaFrameLowering.h
new file mode 100644
index 00000000000000..a5dfc83b940597
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaFrameLowering.h
@@ -0,0 +1,34 @@
+//===- XtensaFrameLowering.h - Define frame lowering for Xtensa --*- C++ -*-==//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===-----------------------------------------------------------------------==//
+
+#ifndef LLVM_LIB_TARGET_XTENSA_XTENSAFRAMELOWERING_H
+#define LLVM_LIB_TARGET_XTENSA_XTENSAFRAMELOWERING_H
+
+#include "llvm/CodeGen/TargetFrameLowering.h"
+
+namespace llvm {
+class XtensaTargetMachine;
+class XtensaSubtarget;
+
+class XtensaFrameLowering : public TargetFrameLowering {
+public:
+ XtensaFrameLowering();
+
+ bool hasFP(const MachineFunction &MF) const override;
+
+ /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
+ /// the function.
+ void emitPrologue(MachineFunction &, MachineBasicBlock &) const override;
+ void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
+};
+
+} // namespace llvm
+
+#endif /* LLVM_LIB_TARGET_XTENSA_XTENSAFRAMELOWERING_H */
diff --git a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
new file mode 100644
index 00000000000000..1c2263109bd850
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
@@ -0,0 +1,81 @@
+//===- XtensaISelDAGToDAG.cpp - A dag to dag inst selector for Xtensa -----===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines an instruction selector for the Xtensa target.
+//
+//===----------------------------------------------------------------------===//
+
+#include "Xtensa.h"
+#include "XtensaTargetMachine.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/SelectionDAGISel.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "xtensa-isel"
+
+namespace {
+
+class XtensaDAGToDAGISel : public SelectionDAGISel {
+public:
+ static char ID;
+
+ XtensaDAGToDAGISel(XtensaTargetMachine &TM, CodeGenOptLevel OptLevel)
+ : SelectionDAGISel(ID, TM, OptLevel) {}
+
+ StringRef getPassName() const override {
+ return "Xtensa DAG->DAG Pattern Instruction Selection";
+ }
+
+ void Select(SDNode *Node) override;
+
+ bool selectMemRegAddr(SDValue Addr, SDValue &Base, SDValue &Offset,
+ int Scale) {
+ report_fatal_error("MemReg address is not implemented yet");
+ }
+
+ bool selectMemRegAddrISH1(SDValue Addr, SDValue &Base, SDValue &Offset) {
+ return selectMemRegAddr(Addr, Base, Offset, 1);
+ }
+
+ bool selectMemRegAddrISH2(SDValue Addr, SDValue &Base, SDValue &Offset) {
+ return selectMemRegAddr(Addr, Base, Offset, 2);
+ }
+
+ bool selectMemRegAddrISH4(SDValue Addr, SDValue &Base, SDValue &Offset) {
+ return selectMemRegAddr(Addr, Base, Offset, 4);
+ }
+
+// Include the pieces autogenerated from the target description.
+#include "XtensaGenDAGISel.inc"
+}; // namespace
+} // end anonymous namespace
+
+char XtensaDAGToDAGISel::ID = 0;
+
+FunctionPass *llvm::createXtensaISelDag(XtensaTargetMachine &TM,
+ CodeGenOptLevel OptLevel) {
+ return new XtensaDAGToDAGISel(TM, OptLevel);
+}
+
+void XtensaDAGToDAGISel::Select(SDNode *Node) {
+ SDLoc DL(Node);
+
+ // If we have a custom node, we already have selected!
+ if (Node->isMachineOpcode()) {
+ Node->setNodeId(-1);
+ return;
+ }
+
+ SelectCode(Node);
+}
diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
new file mode 100644
index 00000000000000..0b8d908de04764
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
@@ -0,0 +1,60 @@
+//===- XtensaISelLowering.cpp - Xtensa DAG Lowering Implementation --------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the interfaces that Xtensa uses to lower LLVM code into a
+// selection DAG.
+//
+//===----------------------------------------------------------------------===//
+
+#include "XtensaISelLowering.h"
+#include "XtensaSubtarget.h"
+#include "XtensaTargetMachine.h"
+#include "llvm/CodeGen/CallingConvLower.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineJumpTableInfo.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "xtensa-lower"
+
+XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &tm,
+ const XtensaSubtarget &STI)
+ : TargetLowering(tm), Subtarget(STI) {
+ // Set up the register classes.
+ addRegisterClass(MVT::i32, &Xtensa::ARRegClass);
+
+ // Set up special registers.
+ setStackPointerRegisterToSaveRestore(Xtensa::SP);
+
+ setSchedulingPreference(Sched::RegPressure);
+
+ setMinFunctionAlignment(Align(4));
+
+ // Compute derived properties from the register classes
+ computeRegisterProperties(STI.getRegisterInfo());
+}
+
+SDValue XtensaTargetLowering::LowerOperation(SDValue Op,
+ SelectionDAG &DAG) const {
+ switch (Op.getOpcode()) {
+ default:
+ report_fatal_error("Unexpected node to lower");
+ }
+}
+
+const char *XtensaTargetLowering::getTargetNodeName(unsigned Opcode) const {
+ return NULL;
+}
diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h
new file mode 100644
index 00000000000000..d61e9db621ba21
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h
@@ -0,0 +1,40 @@
+//===- XtensaISelLowering.h - Xtensa DAG Lowering Interface -----*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the interfaces that Xtensa uses to lower LLVM code into a
+// selection DAG.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_XTENSA_XTENSAISELLOWERING_H
+#define LLVM_LIB_TARGET_XTENSA_XTENSAISELLOWERING_H
+
+#include "llvm/CodeGen/CallingConvLower.h"
+#include "llvm/CodeGen/SelectionDAG.h"
+#include "llvm/CodeGen/TargetLowering.h"
+
+namespace llvm {
+class XtensaSubtarget;
+
+class XtensaTargetLowering : public TargetLowering {
+public:
+ explicit XtensaTargetLowering(const TargetMachine &TM,
+ const XtensaSubtarget &STI);
+
+ const char *getTargetNodeName(unsigned Opcode) const override;
+ SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
+
+private:
+ const XtensaSubtarget &Subtarget;
+};
+
+} // end namespace llvm
+
+#endif /* LLVM_LIB_TARGET_XTENSA_XTENSAISELLOWERING_H */
diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
new file mode 100644
index 00000000000000..52a87fe4b93438
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp
@@ -0,0 +1,27 @@
+//===- XtensaInstrInfo.cpp - Xtensa Instruction Information ---------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the Xtensa implementation of the TargetInstrInfo class.
+//
+//===----------------------------------------------------------------------===//
+
+#include "XtensaInstrInfo.h"
+#include "XtensaTargetMachine.h"
+#include "llvm/CodeGen/MachineConstantPool.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+
+#define GET_INSTRINFO_CTOR_DTOR
+#include "XtensaGenInstrInfo.inc"
+
+using namespace llvm;
+
+XtensaInstrInfo::XtensaInstrInfo(XtensaSubtarget &sti)
+ : XtensaGenInstrInfo(), RI(sti), STI(sti) {}
diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.h b/llvm/lib/Target/Xtensa/XtensaInstrInfo.h
new file mode 100644
index 00000000000000..7225886b2ce119
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.h
@@ -0,0 +1,43 @@
+//===-- XtensaInstrInfo.h - Xtensa Instruction Information ------*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the Xtensa implementation of the TargetInstrInfo class.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_XTENSA_XTENSAINSTRINFO_H
+#define LLVM_LIB_TARGET_XTENSA_XTENSAINSTRINFO_H
+
+#include "Xtensa.h"
+#include "XtensaRegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+
+#define GET_INSTRINFO_HEADER
+
+#include "XtensaGenInstrInfo.inc"
+
+namespace llvm {
+
+class XtensaTargetMachine;
+class XtensaSubtarget;
+class XtensaInstrInfo : public XtensaGenInstrInfo {
+ const XtensaRegisterInfo RI;
+ XtensaSubtarget &STI;
+
+public:
+ XtensaInstrInfo(XtensaSubtarget &STI);
+
+ // Return the XtensaRegisterInfo, which this class owns.
+ const XtensaRegisterInfo &getRegisterInfo() const { return RI; }
+};
+} // end namespace llvm
+
+#endif /* LLVM_LIB_TARGET_XTENSA_XTENSAINSTRINFO_H */
diff --git a/llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp b/llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp
new file mode 100644
index 00000000000000..5be72f92870e87
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp
@@ -0,0 +1,62 @@
+//===- XtensaMCInstLower.cpp - Convert Xtensa MachineInstr to MCInst ------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains code to lower Xtensa MachineInstrs to their corresponding
+// MCInst records.
+//
+//===----------------------------------------------------------------------===//
+
+#include "XtensaMCInstLower.h"
+#include "MCTargetDesc/XtensaMCExpr.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/IR/Mangler.h"
+#include "llvm/MC/MCExpr.h"
+#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCStreamer.h"
+
+using namespace llvm;
+
+XtensaMCInstLower::XtensaMCInstLower(MCContext &ctx,
+ XtensaAsmPrinter &asmPrinter)
+ : Ctx(ctx), Printer(asmPrinter) {}
+
+MCOperand XtensaMCInstLower::lowerOperand(const MachineOperand &MO,
+ unsigned Offset) const {
+ MachineOperand::MachineOperandType MOTy = MO.getType();
+
+ switch (MOTy) {
+ case MachineOperand::MO_Register:
+ // Ignore all implicit register operands.
+ if (MO.isImplicit())
+ break;
+ return MCOperand::createReg(MO.getReg());
+ case MachineOperand::MO_Immediate:
+ return MCOperand::createImm(MO.getImm() + Offset);
+ case MachineOperand::MO_RegisterMask:
+ break;
+ default:
+ report_fatal_error("unknown operand type");
+ }
+
+ return MCOperand();
+}
+
+void XtensaMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
+ OutMI.setOpcode(MI->getOpcode());
+
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ const MachineOperand &MO = MI->getOperand(i);
+ MCOperand MCOp = lowerOperand(MO);
+
+ if (MCOp.isValid())
+ OutMI.addOperand(MCOp);
+ }
+}
diff --git a/llvm/lib/Target/Xtensa/XtensaMCInstLower.h b/llvm/lib/Target/Xtensa/XtensaMCInstLower.h
new file mode 100644
index 00000000000000..2b238417ae3eba
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaMCInstLower.h
@@ -0,0 +1,43 @@
+//===- XtensaMCInstLower.h - Lower MachineInstr to MCInst ------*- C++ -*--===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_XTENSA_XTENSAMCINSTLOWER_H
+#define LLVM_LIB_TARGET_XTENSA_XTENSAMCINSTLOWER_H
+
+#include "XtensaAsmPrinter.h"
+#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/Support/Compiler.h"
+#include "llvm/Support/DataTypes.h"
+
+namespace llvm {
+class MCContext;
+class MCInst;
+class MCOperand;
+class MCSymbol;
+class MachineInstr;
+class MachineOperand;
+class XtensaAsmPrinter;
+
+class LLVM_LIBRARY_VISIBILITY XtensaMCInstLower {
+ MCContext &Ctx;
+ XtensaAsmPrinter &Printer;
+
+public:
+ XtensaMCInstLower(MCContext &ctx, XtensaAsmPrinter &asmPrinter);
+
+ // Lower MachineInstr MI to MCInst OutMI.
+ void lower(const MachineInstr *MI, MCInst &OutMI) const;
+
+ // Return an MCOperand for MO. Return an empty operand if MO is implicit.
+ MCOperand lowerOperand(const MachineOperand &MO, unsigned Offset = 0) const;
+};
+} // end namespace llvm
+
+#endif /* LLVM_LIB_TARGET_XTENSA_XTENSAMCINSTLOWER_H */
diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp
new file mode 100644
index 00000000000000..4ac99776d3c9eb
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp
@@ -0,0 +1,72 @@
+//===- XtensaRegisterInfo.cpp - Xtensa Register Information ---------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the Xtensa implementation of the TargetRegisterInfo class.
+//
+//===----------------------------------------------------------------------===//
+
+#include "XtensaRegisterInfo.h"
+#include "XtensaInstrInfo.h"
+#include "XtensaSubtarget.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/raw_ostream.h"
+
+#define DEBUG_TYPE "xtensa-reg-info"
+
+#define GET_REGINFO_TARGET_DESC
+#include "XtensaGenRegisterInfo.inc"
+
+using namespace llvm;
+
+XtensaRegisterInfo::XtensaRegisterInfo(const XtensaSubtarget &STI)
+ : XtensaGenRegisterInfo(Xtensa::A0), Subtarget(STI) {}
+
+const uint16_t *
+XtensaRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
+ // Calling convention is not implemented yet
+ return nullptr;
+}
+
+const uint32_t *
+XtensaRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
+ CallingConv::ID) const {
+ // Calling convention is not implemented yet
+ return nullptr;
+}
+
+BitVector XtensaRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
+ BitVector Reserved(getNumRegs());
+ const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
+
+ Reserved.set(Xtensa::A0);
+ if (TFI->hasFP(MF)) {
+ // Reserve frame pointer.
+ Reserved.set(getFrameRegister(MF));
+ }
+
+ // Reserve stack pointer.
+ Reserved.set(Xtensa::SP);
+ return Reserved;
+}
+
+bool XtensaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
+ int SPAdj, unsigned FIOperandNum,
+ RegScavenger *RS) const {
+ report_fatal_error("Eliminate frame index not supported yet");
+ return false;
+}
+
+Register XtensaRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
+ const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
+ return TFI->hasFP(MF) ? (Xtensa::A15) : Xtensa::SP;
+}
diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.h b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.h
new file mode 100644
index 00000000000000..4f5426acf7a559
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.h
@@ -0,0 +1,56 @@
+//===-- XtensaRegisterInfo.h - Xtensa Register Information Impl -*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains the Xtensa implementation of the TargetRegisterInfo class.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_XTENSA_XTENSAREGISTERINFO_H
+#define LLVM_LIB_TARGET_XTENSA_XTENSAREGISTERINFO_H
+
+#include "Xtensa.h"
+#include "llvm/CodeGen/TargetRegisterInfo.h"
+
+#define GET_REGINFO_HEADER
+#include "XtensaGenRegisterInfo.inc"
+
+namespace llvm {
+class TargetRegisterClass;
+class XtensaInstrInfo;
+class XtensaSubtarget;
+
+struct XtensaRegisterInfo : public XtensaGenRegisterInfo {
+public:
+ const XtensaSubtarget &Subtarget;
+
+ XtensaRegisterInfo(const XtensaSubtarget &STI);
+
+ bool requiresRegisterScavenging(const MachineFunction &MF) const override {
+ return true;
+ }
+
+ bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
+ return true;
+ }
+
+ const uint16_t *
+ getCalleeSavedRegs(const MachineFunction *MF = 0) const override;
+ const uint32_t *getCallPreservedMask(const MachineFunction &MF,
+ CallingConv::ID) const override;
+ BitVector getReservedRegs(const MachineFunction &MF) const override;
+ bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
+ unsigned FIOperandNum,
+ RegScavenger *RS = nullptr) const override;
+ Register getFrameRegister(const MachineFunction &MF) const override;
+};
+
+} // end namespace llvm
+
+#endif /* LLVM_LIB_TARGET_XTENSA_REGISTERINFO_H */
diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
new file mode 100644
index 00000000000000..f76af66cac1efd
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
@@ -0,0 +1,46 @@
+//===- XtensaSubtarget.cpp - Xtensa Subtarget Information -----------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the Xtensa specific subclass of TargetSubtargetInfo.
+//
+//===----------------------------------------------------------------------===//
+
+#include "XtensaSubtarget.h"
+#include "llvm/IR/GlobalValue.h"
+#include "llvm/Support/Debug.h"
+
+#define DEBUG_TYPE "xtensa-subtarget"
+
+#define GET_SUBTARGETINFO_TARGET_DESC
+#define GET_SUBTARGETINFO_CTOR
+#include "XtensaGenSubtargetInfo.inc"
+
+using namespace llvm;
+
+XtensaSubtarget &
+XtensaSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
+ StringRef CPUName = CPU;
+ if (CPUName.empty()) {
+ // set default cpu name
+ CPUName = "generic";
+ }
+
+ HasDensity = false;
+
+ // Parse features string.
+ ParseSubtargetFeatures(CPUName, CPUName, FS);
+ return *this;
+}
+
+XtensaSubtarget::XtensaSubtarget(const Triple &TT, const std::string &CPU,
+ const std::string &FS, const TargetMachine &TM)
+ : XtensaGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), TargetTriple(TT),
+ InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
+ TSInfo(), FrameLowering() {}
diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.h b/llvm/lib/Target/Xtensa/XtensaSubtarget.h
new file mode 100644
index 00000000000000..0fca21957adeb6
--- /dev/null
+++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.h
@@ -0,0 +1,72 @@
+//===-- XtensaSubtarget.h - Define Subtarget for the Xtensa ----*- C++ -*--===//
+//
+// The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the Xtensa specific subclass of TargetSubtargetInfo.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_XTENSA_XTENSASUBTARGET_H
+#define LLVM_LIB_TARGET_XTENSA_XTENSASUBTARGET_H
+
+#include "XtensaFrameLowering.h"
+#include "XtensaISelLowering.h"
+#include "XtensaInstrInfo.h"
+#include "XtensaRegisterInfo.h"
+#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
+#include "llvm/IR/DataLayout.h"
+#include "llvm/Target/TargetMachine.h"
+
+#define GET_SUBTARGETINFO_HEADER
+#include "XtensaGenSubtargetInfo.inc"
+
+namespace llvm {
+class StringRef;
+
+class XtensaSubtarget : public XtensaGenSubtargetInfo {
+private:
+ Triple TargetTriple;
+ XtensaInstrInfo InstrInfo;
+ XtensaTargetLowering TLInfo;
+ SelectionDAGTargetInfo TSInfo;
+ XtensaFrameLowering FrameLowering;
+
+ // Enabled Xtensa Density extension
+ bool HasDensity;
+
+ XtensaSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
+
+public:
+ XtensaSubtarget(const Triple &TT, const std::string &CPU,
+ const std::string &FS, const TargetMachine &TM);
+
+ const TargetFrameLowering *getFrameLowering() const override {
+ return &FrameLowering;
+ }
+ const XtensaInstrInfo *getInstrInfo() const override { return &InstrInfo; }
+ const XtensaRegisterInfo *getRegisterInfo() const override {
+ return &InstrInfo.getRegisterInfo();
+ }
+
+ const XtensaTargetLowering *getTargetLowering() const override {
+ return &TLInfo;
+ }
+ const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
+ return &TSInfo;
+ }
+
+ bool hasDensity() const { return HasDensity; }
+
+ // Automatically generated by tblgen.
+ void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
+};
+} // end namespace llvm
+
+#endif /* LLVM_LIB_TARGET_XTENSA_XTENSASUBTARGET_H */
diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
index c891ecd9c0c3fc..5ee24c701f074e 100644
--- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
@@ -52,7 +52,8 @@ XtensaTargetMachine::XtensaTargetMachine(const Target &T, const Triple &TT,
: LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, IsLittle), TT,
CPU, FS, Options, getEffectiveRelocModel(JIT, RM),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
- TLOF(std::make_unique<TargetLoweringObjectFileELF>()) {
+ TLOF(std::make_unique<TargetLoweringObjectFileELF>()),
+ Subtarget(TT, std::string(CPU), std::string(FS), *this) {
initAsmInfo();
}
@@ -64,6 +65,31 @@ XtensaTargetMachine::XtensaTargetMachine(const Target &T, const Triple &TT,
CodeGenOptLevel OL, bool JIT)
: XtensaTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
+const XtensaSubtarget *
+XtensaTargetMachine::getSubtargetImpl(const Function &F) const {
+ return &Subtarget;
+}
+
+namespace {
+/// Xtensa Code Generator Pass Configuration Options.
+class XtensaPassConfig : public TargetPassConfig {
+public:
+ XtensaPassConfig(XtensaTargetMachine &TM, PassManagerBase &PM)
+ : TargetPassConfig(TM, PM) {}
+
+ XtensaTargetMachine &getXtensaTargetMachine() const {
+ return getTM<XtensaTargetMachine>();
+ }
+
+ bool addInstSelector() override;
+};
+} // end anonymous namespace
+
+bool XtensaPassConfig::addInstSelector() {
+ addPass(createXtensaISelDag(getXtensaTargetMachine(), getOptLevel()));
+ return false;
+}
+
TargetPassConfig *XtensaTargetMachine::createPassConfig(PassManagerBase &PM) {
- return new TargetPassConfig(*this, PM);
+ return new XtensaPassConfig(*this, PM);
}
diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.h b/llvm/lib/Target/Xtensa/XtensaTargetMachine.h
index dd76f45b3bb717..be0886f2a9b0fe 100644
--- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.h
+++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.h
@@ -15,6 +15,7 @@
#ifndef LLVM_LIB_TARGET_XTENSA_XTENSATARGETMACHINE_H
#define LLVM_LIB_TARGET_XTENSA_XTENSATARGETMACHINE_H
+#include "XtensaSubtarget.h"
#include "llvm/Target/TargetMachine.h"
#include <optional>
@@ -36,10 +37,15 @@ class XtensaTargetMachine : public LLVMTargetMachine {
std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT);
+ const XtensaSubtarget *getSubtargetImpl() const { return &Subtarget; }
+ const XtensaSubtarget *getSubtargetImpl(const Function &F) const override;
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
TargetLoweringObjectFile *getObjFileLowering() const override {
return TLOF.get();
}
+
+protected:
+ XtensaSubtarget Subtarget;
};
} // end namespace llvm
diff --git a/llvm/test/CodeGen/Xtensa/lit.local.cfg b/llvm/test/CodeGen/Xtensa/lit.local.cfg
new file mode 100644
index 00000000000000..e81bfa773f36a8
--- /dev/null
+++ b/llvm/test/CodeGen/Xtensa/lit.local.cfg
@@ -0,0 +1,2 @@
+if not "Xtensa" in config.root.targets:
+ config.unsupported = True
diff --git a/llvm/test/CodeGen/Xtensa/simple.ll b/llvm/test/CodeGen/Xtensa/simple.ll
new file mode 100644
index 00000000000000..a2c55aa5138352
--- /dev/null
+++ b/llvm/test/CodeGen/Xtensa/simple.ll
@@ -0,0 +1,5 @@
+; RUN: llc -mtriple=xtensa -filetype=asm %s -o - | FileCheck %s
+; RUN: llc -mtriple=xtensa -filetype=obj %s -o - | llvm-objdump --arch=xtensa -d - | FileCheck %s --check-prefix=DUMP
+
+; CHECK: .text
+; DUMP: file format elf32-xtensa
>From 34e6e4eff20041d8ff75ff3874a7394d1efa2751 Mon Sep 17 00:00:00 2001
From: Andrei Safronov <safronov at espressif.com>
Date: Thu, 8 Feb 2024 02:18:22 +0300
Subject: [PATCH 2/2] fix
---
llvm/lib/Target/Xtensa/CMakeLists.txt | 1 -
llvm/lib/Target/Xtensa/Xtensa.h | 2 -
llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp | 41 ++++++++++--
llvm/lib/Target/Xtensa/XtensaAsmPrinter.h | 8 ++-
.../lib/Target/Xtensa/XtensaFrameLowering.cpp | 5 --
llvm/lib/Target/Xtensa/XtensaFrameLowering.h | 2 -
llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp | 2 -
llvm/lib/Target/Xtensa/XtensaISelLowering.cpp | 4 +-
llvm/lib/Target/Xtensa/XtensaISelLowering.h | 5 +-
llvm/lib/Target/Xtensa/XtensaInstrInfo.h | 2 +
llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp | 62 -------------------
llvm/lib/Target/Xtensa/XtensaMCInstLower.h | 43 -------------
llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp | 5 +-
llvm/lib/Target/Xtensa/XtensaRegisterInfo.h | 6 +-
llvm/lib/Target/Xtensa/XtensaSubtarget.cpp | 8 +--
llvm/lib/Target/Xtensa/XtensaSubtarget.h | 10 +--
.../lib/Target/Xtensa/XtensaTargetMachine.cpp | 19 +++++-
llvm/lib/Target/Xtensa/XtensaTargetMachine.h | 3 +-
18 files changed, 76 insertions(+), 152 deletions(-)
delete mode 100644 llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp
delete mode 100644 llvm/lib/Target/Xtensa/XtensaMCInstLower.h
diff --git a/llvm/lib/Target/Xtensa/CMakeLists.txt b/llvm/lib/Target/Xtensa/CMakeLists.txt
index 5a4d0a5af8bd00..2064511e75b82e 100644
--- a/llvm/lib/Target/Xtensa/CMakeLists.txt
+++ b/llvm/lib/Target/Xtensa/CMakeLists.txt
@@ -19,7 +19,6 @@ add_llvm_target(XtensaCodeGen
XtensaInstrInfo.cpp
XtensaISelDAGToDAG.cpp
XtensaISelLowering.cpp
- XtensaMCInstLower.cpp
XtensaRegisterInfo.cpp
XtensaSubtarget.cpp
XtensaTargetMachine.cpp
diff --git a/llvm/lib/Target/Xtensa/Xtensa.h b/llvm/lib/Target/Xtensa/Xtensa.h
index 1d6e2a2b32f152..da44e30f367fab 100644
--- a/llvm/lib/Target/Xtensa/Xtensa.h
+++ b/llvm/lib/Target/Xtensa/Xtensa.h
@@ -1,7 +1,5 @@
//===- Xtensa.h - Top-level interface for Xtensa representation -*- C++ -*-===//
//
-// The LLVM Compiler Infrastructure
-//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
diff --git a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
index fc681b1cbe8bd6..87dbf2eb5166cd 100644
--- a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp
@@ -1,7 +1,5 @@
//===- XtensaAsmPrinter.cpp Xtensa LLVM Assembly Printer ------------------===//
//
-// The LLVM Compiler Infrastructure
-//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
@@ -15,7 +13,6 @@
#include "XtensaAsmPrinter.h"
#include "TargetInfo/XtensaTargetInfo.h"
-#include "XtensaMCInstLower.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/CodeGen/MachineModuleInfoImpls.h"
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
@@ -29,13 +26,45 @@
using namespace llvm;
void XtensaAsmPrinter::emitInstruction(const MachineInstr *MI) {
- XtensaMCInstLower Lower(MF->getContext(), *this);
MCInst LoweredMI;
- Lower.lower(MI, LoweredMI);
+ lowerToMCInst(MI, LoweredMI);
EmitToStreamer(*OutStreamer, LoweredMI);
}
-// Force static initialization.
+MCOperand XtensaAsmPrinter::lowerOperand(const MachineOperand &MO,
+ unsigned Offset) const {
+ MachineOperand::MachineOperandType MOTy = MO.getType();
+
+ switch (MOTy) {
+ case MachineOperand::MO_Register:
+ // Ignore all implicit register operands.
+ if (MO.isImplicit())
+ break;
+ return MCOperand::createReg(MO.getReg());
+ case MachineOperand::MO_Immediate:
+ return MCOperand::createImm(MO.getImm() + Offset);
+ case MachineOperand::MO_RegisterMask:
+ break;
+ default:
+ report_fatal_error("unknown operand type");
+ }
+
+ return MCOperand();
+}
+
+void XtensaAsmPrinter::lowerToMCInst(const MachineInstr *MI,
+ MCInst &OutMI) const {
+ OutMI.setOpcode(MI->getOpcode());
+
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ const MachineOperand &MO = MI->getOperand(i);
+ MCOperand MCOp = lowerOperand(MO);
+
+ if (MCOp.isValid())
+ OutMI.addOperand(MCOp);
+ }
+}
+
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXtensaAsmPrinter() {
RegisterAsmPrinter<XtensaAsmPrinter> A(getTheXtensaTarget());
}
diff --git a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h
index 37ead2ddb37f11..dec2a1ee4954f9 100644
--- a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h
+++ b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h
@@ -1,7 +1,5 @@
//===- XtensaAsmPrinter.h - Xtensa LLVM Assembly Printer --------*- C++-*--===//
//
-// The LLVM Compiler Infrastructure
-//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
@@ -36,6 +34,12 @@ class LLVM_LIBRARY_VISIBILITY XtensaAsmPrinter : public AsmPrinter {
StringRef getPassName() const override { return "Xtensa Assembly Printer"; }
void emitInstruction(const MachineInstr *MI) override;
+
+ // Lower MachineInstr MI to MCInst OutMI.
+ void lowerToMCInst(const MachineInstr *MI, MCInst &OutMI) const;
+
+ // Return an MCOperand for MO. Return an empty operand if MO is implicit.
+ MCOperand lowerOperand(const MachineOperand &MO, unsigned Offset = 0) const;
};
} // end namespace llvm
diff --git a/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp
index b201b99813ced1..2092a2d947f866 100644
--- a/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp
@@ -1,7 +1,5 @@
//===- XtensaFrameLowering.cpp - Xtensa Frame Information -----------------===//
//
-// The LLVM Compiler Infrastructure
-//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
@@ -28,9 +26,6 @@ XtensaFrameLowering::XtensaFrameLowering()
: TargetFrameLowering(TargetFrameLowering::StackGrowsDown, Align(4), 0,
Align(4)) {}
-// hasFP - Return true if the specified function should have a dedicated frame
-// pointer register. This is true if the function has variable sized allocas or
-// if frame pointer elimination is disabled.
bool XtensaFrameLowering::hasFP(const MachineFunction &MF) const {
const MachineFrameInfo &MFI = MF.getFrameInfo();
return MF.getTarget().Options.DisableFramePointerElim(MF) ||
diff --git a/llvm/lib/Target/Xtensa/XtensaFrameLowering.h b/llvm/lib/Target/Xtensa/XtensaFrameLowering.h
index a5dfc83b940597..19e52310a99d91 100644
--- a/llvm/lib/Target/Xtensa/XtensaFrameLowering.h
+++ b/llvm/lib/Target/Xtensa/XtensaFrameLowering.h
@@ -1,7 +1,5 @@
//===- XtensaFrameLowering.h - Define frame lowering for Xtensa --*- C++ -*-==//
//
-// The LLVM Compiler Infrastructure
-//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
diff --git a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
index 1c2263109bd850..30073727545228 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp
@@ -1,7 +1,5 @@
//===- XtensaISelDAGToDAG.cpp - A dag to dag inst selector for Xtensa -----===//
//
-// The LLVM Compiler Infrastructure
-//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
index 0b8d908de04764..ad994b509c014b 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp
@@ -1,7 +1,5 @@
//===- XtensaISelLowering.cpp - Xtensa DAG Lowering Implementation --------===//
//
-// The LLVM Compiler Infrastructure
-//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
@@ -56,5 +54,5 @@ SDValue XtensaTargetLowering::LowerOperation(SDValue Op,
}
const char *XtensaTargetLowering::getTargetNodeName(unsigned Opcode) const {
- return NULL;
+ return nullptr;
}
diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h
index d61e9db621ba21..8b03712efc9bb5 100644
--- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h
+++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h
@@ -1,7 +1,5 @@
//===- XtensaISelLowering.h - Xtensa DAG Lowering Interface -----*- C++ -*-===//
//
-// The LLVM Compiler Infrastructure
-//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
@@ -29,8 +27,11 @@ class XtensaTargetLowering : public TargetLowering {
const XtensaSubtarget &STI);
const char *getTargetNodeName(unsigned Opcode) const override;
+
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
+ const XtensaSubtarget &getSubtarget() const { return Subtarget; }
+
private:
const XtensaSubtarget &Subtarget;
};
diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.h b/llvm/lib/Target/Xtensa/XtensaInstrInfo.h
index 7225886b2ce119..0823aec58cde29 100644
--- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.h
+++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.h
@@ -37,6 +37,8 @@ class XtensaInstrInfo : public XtensaGenInstrInfo {
// Return the XtensaRegisterInfo, which this class owns.
const XtensaRegisterInfo &getRegisterInfo() const { return RI; }
+
+ const XtensaSubtarget &getSubtarget() const { return STI; }
};
} // end namespace llvm
diff --git a/llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp b/llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp
deleted file mode 100644
index 5be72f92870e87..00000000000000
--- a/llvm/lib/Target/Xtensa/XtensaMCInstLower.cpp
+++ /dev/null
@@ -1,62 +0,0 @@
-//===- XtensaMCInstLower.cpp - Convert Xtensa MachineInstr to MCInst ------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains code to lower Xtensa MachineInstrs to their corresponding
-// MCInst records.
-//
-//===----------------------------------------------------------------------===//
-
-#include "XtensaMCInstLower.h"
-#include "MCTargetDesc/XtensaMCExpr.h"
-#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/IR/Mangler.h"
-#include "llvm/MC/MCExpr.h"
-#include "llvm/MC/MCInst.h"
-#include "llvm/MC/MCStreamer.h"
-
-using namespace llvm;
-
-XtensaMCInstLower::XtensaMCInstLower(MCContext &ctx,
- XtensaAsmPrinter &asmPrinter)
- : Ctx(ctx), Printer(asmPrinter) {}
-
-MCOperand XtensaMCInstLower::lowerOperand(const MachineOperand &MO,
- unsigned Offset) const {
- MachineOperand::MachineOperandType MOTy = MO.getType();
-
- switch (MOTy) {
- case MachineOperand::MO_Register:
- // Ignore all implicit register operands.
- if (MO.isImplicit())
- break;
- return MCOperand::createReg(MO.getReg());
- case MachineOperand::MO_Immediate:
- return MCOperand::createImm(MO.getImm() + Offset);
- case MachineOperand::MO_RegisterMask:
- break;
- default:
- report_fatal_error("unknown operand type");
- }
-
- return MCOperand();
-}
-
-void XtensaMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
- OutMI.setOpcode(MI->getOpcode());
-
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- const MachineOperand &MO = MI->getOperand(i);
- MCOperand MCOp = lowerOperand(MO);
-
- if (MCOp.isValid())
- OutMI.addOperand(MCOp);
- }
-}
diff --git a/llvm/lib/Target/Xtensa/XtensaMCInstLower.h b/llvm/lib/Target/Xtensa/XtensaMCInstLower.h
deleted file mode 100644
index 2b238417ae3eba..00000000000000
--- a/llvm/lib/Target/Xtensa/XtensaMCInstLower.h
+++ /dev/null
@@ -1,43 +0,0 @@
-//===- XtensaMCInstLower.h - Lower MachineInstr to MCInst ------*- C++ -*--===//
-//
-// The LLVM Compiler Infrastructure
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_LIB_TARGET_XTENSA_XTENSAMCINSTLOWER_H
-#define LLVM_LIB_TARGET_XTENSA_XTENSAMCINSTLOWER_H
-
-#include "XtensaAsmPrinter.h"
-#include "llvm/CodeGen/MachineOperand.h"
-#include "llvm/Support/Compiler.h"
-#include "llvm/Support/DataTypes.h"
-
-namespace llvm {
-class MCContext;
-class MCInst;
-class MCOperand;
-class MCSymbol;
-class MachineInstr;
-class MachineOperand;
-class XtensaAsmPrinter;
-
-class LLVM_LIBRARY_VISIBILITY XtensaMCInstLower {
- MCContext &Ctx;
- XtensaAsmPrinter &Printer;
-
-public:
- XtensaMCInstLower(MCContext &ctx, XtensaAsmPrinter &asmPrinter);
-
- // Lower MachineInstr MI to MCInst OutMI.
- void lower(const MachineInstr *MI, MCInst &OutMI) const;
-
- // Return an MCOperand for MO. Return an empty operand if MO is implicit.
- MCOperand lowerOperand(const MachineOperand &MO, unsigned Offset = 0) const;
-};
-} // end namespace llvm
-
-#endif /* LLVM_LIB_TARGET_XTENSA_XTENSAMCINSTLOWER_H */
diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp
index 4ac99776d3c9eb..f749cc51f96a04 100644
--- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp
@@ -1,7 +1,5 @@
//===- XtensaRegisterInfo.cpp - Xtensa Register Information ---------------===//
//
-// The LLVM Compiler Infrastructure
-//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
@@ -63,10 +61,9 @@ bool XtensaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, unsigned FIOperandNum,
RegScavenger *RS) const {
report_fatal_error("Eliminate frame index not supported yet");
- return false;
}
Register XtensaRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
- return TFI->hasFP(MF) ? (Xtensa::A15) : Xtensa::SP;
+ return TFI->hasFP(MF) ? Xtensa::A15 : Xtensa::SP;
}
diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.h b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.h
index 4f5426acf7a559..a4eda87f4c8b74 100644
--- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.h
+++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.h
@@ -1,7 +1,5 @@
//===-- XtensaRegisterInfo.h - Xtensa Register Information Impl -*- C++ -*-===//
//
-// The LLVM Compiler Infrastructure
-//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
@@ -45,12 +43,14 @@ struct XtensaRegisterInfo : public XtensaGenRegisterInfo {
const uint32_t *getCallPreservedMask(const MachineFunction &MF,
CallingConv::ID) const override;
BitVector getReservedRegs(const MachineFunction &MF) const override;
+
bool eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
unsigned FIOperandNum,
RegScavenger *RS = nullptr) const override;
+
Register getFrameRegister(const MachineFunction &MF) const override;
};
} // end namespace llvm
-#endif /* LLVM_LIB_TARGET_XTENSA_REGISTERINFO_H */
+#endif // LLVM_LIB_TARGET_XTENSA_REGISTERINFO_H
diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
index f76af66cac1efd..10ab92d2a2d38e 100644
--- a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp
@@ -1,7 +1,5 @@
//===- XtensaSubtarget.cpp - Xtensa Subtarget Information -----------------===//
//
-// The LLVM Compiler Infrastructure
-//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
@@ -39,8 +37,8 @@ XtensaSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
return *this;
}
-XtensaSubtarget::XtensaSubtarget(const Triple &TT, const std::string &CPU,
- const std::string &FS, const TargetMachine &TM)
- : XtensaGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), TargetTriple(TT),
+XtensaSubtarget::XtensaSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
+ const TargetMachine &TM)
+ : XtensaGenSubtargetInfo(TT, CPU, /*TuneCPU=*/CPU, FS), TargetTriple(TT),
InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
TSInfo(), FrameLowering() {}
diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.h b/llvm/lib/Target/Xtensa/XtensaSubtarget.h
index 0fca21957adeb6..948dcbc5278eaa 100644
--- a/llvm/lib/Target/Xtensa/XtensaSubtarget.h
+++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.h
@@ -1,7 +1,5 @@
//===-- XtensaSubtarget.h - Define Subtarget for the Xtensa ----*- C++ -*--===//
//
-// The LLVM Compiler Infrastructure
-//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
@@ -32,7 +30,7 @@ class StringRef;
class XtensaSubtarget : public XtensaGenSubtargetInfo {
private:
- Triple TargetTriple;
+ const Triple &TargetTriple;
XtensaInstrInfo InstrInfo;
XtensaTargetLowering TLInfo;
SelectionDAGTargetInfo TSInfo;
@@ -44,8 +42,10 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo {
XtensaSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
public:
- XtensaSubtarget(const Triple &TT, const std::string &CPU,
- const std::string &FS, const TargetMachine &TM);
+ XtensaSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
+ const TargetMachine &TM);
+
+ const Triple &getTargetTriple() const { return TargetTriple; }
const TargetFrameLowering *getFrameLowering() const override {
return &FrameLowering;
diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
index 5ee24c701f074e..49c7faf84df1d3 100644
--- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
+++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.cpp
@@ -52,8 +52,7 @@ XtensaTargetMachine::XtensaTargetMachine(const Target &T, const Triple &TT,
: LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, IsLittle), TT,
CPU, FS, Options, getEffectiveRelocModel(JIT, RM),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
- TLOF(std::make_unique<TargetLoweringObjectFileELF>()),
- Subtarget(TT, std::string(CPU), std::string(FS), *this) {
+ TLOF(std::make_unique<TargetLoweringObjectFileELF>()) {
initAsmInfo();
}
@@ -67,7 +66,21 @@ XtensaTargetMachine::XtensaTargetMachine(const Target &T, const Triple &TT,
const XtensaSubtarget *
XtensaTargetMachine::getSubtargetImpl(const Function &F) const {
- return &Subtarget;
+ Attribute CPUAttr = F.getFnAttribute("target-cpu");
+ Attribute FSAttr = F.getFnAttribute("target-features");
+
+ auto CPU = CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
+ auto FS = FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
+
+ auto &I = SubtargetMap[CPU + FS];
+ if (!I) {
+ // This needs to be done before we create a new subtarget since any
+ // creation will depend on the TM and the code generation flags on the
+ // function that reside in TargetOptions.
+ resetTargetOptions(F);
+ I = std::make_unique<XtensaSubtarget>(TargetTriple, CPU, FS, *this);
+ }
+ return I.get();
}
namespace {
diff --git a/llvm/lib/Target/Xtensa/XtensaTargetMachine.h b/llvm/lib/Target/Xtensa/XtensaTargetMachine.h
index be0886f2a9b0fe..fd5dbab69216d8 100644
--- a/llvm/lib/Target/Xtensa/XtensaTargetMachine.h
+++ b/llvm/lib/Target/Xtensa/XtensaTargetMachine.h
@@ -37,7 +37,6 @@ class XtensaTargetMachine : public LLVMTargetMachine {
std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
bool JIT);
- const XtensaSubtarget *getSubtargetImpl() const { return &Subtarget; }
const XtensaSubtarget *getSubtargetImpl(const Function &F) const override;
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
TargetLoweringObjectFile *getObjFileLowering() const override {
@@ -45,7 +44,7 @@ class XtensaTargetMachine : public LLVMTargetMachine {
}
protected:
- XtensaSubtarget Subtarget;
+ mutable StringMap<std::unique_ptr<XtensaSubtarget>> SubtargetMap;
};
} // end namespace llvm
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