[llvm] [RISCV] Handle fixed length vectors with exact VLEN in loweringEXTRACT_SUBVECTOR (PR #79949)

[Philip Reames via llvm-commits]

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@@ -9680,10 +9710,17 @@ SDValue RISCVTargetLowering::lowerEXTRACT_SUBVECTOR(SDValue Op,
 
   // Slide this vector register down by the desired number of elements in order
   // to place the desired subvector starting at element 0.
-  SDValue SlidedownAmt =
-      DAG.getVScale(DL, XLenVT, APInt(XLenVT.getSizeInBits(), RemIdx));
+  SDValue SlidedownAmt;
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preames wrote:

As a follow up, I think there's room to simplify this via TypeSize and the IRBuilder routines for the same.  We could express RemIdx as a TypeSize quantity, and abstract over the scalable vs fixed aspect of it.  

This is minor, and definitely worthy of it's own review.  

https://github.com/llvm/llvm-project/pull/79949