[llvm] [AArch64][SVE] Handle some cases of uzp1/reinterpret from svbool in isZeroingInactiveLanes (PR #78623)

[Usman Nadeem via llvm-commits]

================
@@ -283,6 +283,24 @@ static bool isZeroingInactiveLanes(SDValue Op) {
     switch (Op.getConstantOperandVal(0)) {
     default:
       return false;
+
+    case Intrinsic::aarch64_sve_uzp1:
+      return isZeroingInactiveLanes(Op.getOperand(1)) &&
+             isZeroingInactiveLanes(Op.getOperand(2));
----------------
UsmanNadeem wrote:

We have some code similar to minimal C example below, implemented using intrinsics. The IR example would be `chainedUzp1_to_svbool` in the tests. The result of icmp is reinterpreted and combined using uzp1 and to/from svbool until we get `vscale x 16 x i1`.

If this function is not an appropriate place for this code then would it make sense to do it in instcombine by simplifying this kind of pattern to a concat using the llvm.vector.insert intrinsic?

```
void test(uint8_t *x, uint8_t *y, uint32_t v, int n) {
  for (int i = 0; i < n; i++) {
    x[i] = y[i]==v;
  }
}
```

https://github.com/llvm/llvm-project/pull/78623