[llvm] [AMDGPU][True16] Support VOP3 source DPP operands. (PR #80892)

[Joe Nash via llvm-commits]

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@@ -1,4 +1,5 @@
-# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,GFX11-REAL16 %s
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
 
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Sisyph wrote:

I don't see any disassembler tests where we disassemble _e64_dpp instructions using hi halves of registers. Can you add them at this time? For example from downstream file gfx11_dasm_vop3_dpp16_from_vop1_hi.txt

https://github.com/llvm/llvm-project/pull/80892