[llvm] c2a91d4 - [X86] combine-movmsk-avx.ll - add full AVX1/AVX2 VTEST/MOVMSK test coverage
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 7 03:12:44 PST 2024
Author: Simon Pilgrim
Date: 2024-02-07T11:12:29Z
New Revision: c2a91d4a33af49cd77c6d6ec731ae25538f746b8
URL: https://github.com/llvm/llvm-project/commit/c2a91d4a33af49cd77c6d6ec731ae25538f746b8
DIFF: https://github.com/llvm/llvm-project/commit/c2a91d4a33af49cd77c6d6ec731ae25538f746b8.diff
LOG: [X86] combine-movmsk-avx.ll - add full AVX1/AVX2 VTEST/MOVMSK test coverage
Test all combos of avx1/avx2 and prefer-movmsk-over-vtest
Added:
Modified:
llvm/test/CodeGen/X86/combine-movmsk-avx.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/combine-movmsk-avx.ll b/llvm/test/CodeGen/X86/combine-movmsk-avx.ll
index b3f4878745193c..6da4102bc2ecd4 100644
--- a/llvm/test/CodeGen/X86/combine-movmsk-avx.ll
+++ b/llvm/test/CodeGen/X86/combine-movmsk-avx.ll
@@ -1,7 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX1
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX2
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+prefer-movmsk-over-vtest | FileCheck %s --check-prefixes=ADL
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,VTEST,VTEST-AVX1
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,VTEST,VTEST-AVX2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+prefer-movmsk-over-vtest | FileCheck %s --check-prefixes=CHECK,MOVMSK,MOVMSK-AVX1
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+prefer-movmsk-over-vtest | FileCheck %s --check-prefixes=CHECK,MOVMSK,MOVMSK-AVX2
declare i32 @llvm.x86.avx.movmsk.pd.256(<4 x double>)
declare i32 @llvm.x86.avx.movmsk.ps.256(<8 x float>)
@@ -9,24 +10,24 @@ declare i32 @llvm.x86.avx.movmsk.ps.256(<8 x float>)
; Use widest possible vector for movmsk comparisons (PR37087)
define i1 @movmskps_noneof_bitcast_v4f64(<4 x double> %a0) {
-; CHECK-LABEL: movmskps_noneof_bitcast_v4f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1
-; CHECK-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0
-; CHECK-NEXT: vtestpd %ymm0, %ymm0
-; CHECK-NEXT: sete %al
-; CHECK-NEXT: vzeroupper
-; CHECK-NEXT: retq
+; VTEST-LABEL: movmskps_noneof_bitcast_v4f64:
+; VTEST: # %bb.0:
+; VTEST-NEXT: vxorpd %xmm1, %xmm1, %xmm1
+; VTEST-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0
+; VTEST-NEXT: vtestpd %ymm0, %ymm0
+; VTEST-NEXT: sete %al
+; VTEST-NEXT: vzeroupper
+; VTEST-NEXT: retq
;
-; ADL-LABEL: movmskps_noneof_bitcast_v4f64:
-; ADL: # %bb.0:
-; ADL-NEXT: vxorpd %xmm1, %xmm1, %xmm1
-; ADL-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0
-; ADL-NEXT: vmovmskpd %ymm0, %eax
-; ADL-NEXT: testl %eax, %eax
-; ADL-NEXT: sete %al
-; ADL-NEXT: vzeroupper
-; ADL-NEXT: retq
+; MOVMSK-LABEL: movmskps_noneof_bitcast_v4f64:
+; MOVMSK: # %bb.0:
+; MOVMSK-NEXT: vxorpd %xmm1, %xmm1, %xmm1
+; MOVMSK-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0
+; MOVMSK-NEXT: vmovmskpd %ymm0, %eax
+; MOVMSK-NEXT: testl %eax, %eax
+; MOVMSK-NEXT: sete %al
+; MOVMSK-NEXT: vzeroupper
+; MOVMSK-NEXT: retq
%1 = fcmp oeq <4 x double> %a0, zeroinitializer
%2 = sext <4 x i1> %1 to <4 x i64>
%3 = bitcast <4 x i64> %2 to <8 x float>
@@ -36,35 +37,35 @@ define i1 @movmskps_noneof_bitcast_v4f64(<4 x double> %a0) {
}
define i1 @movmskps_allof_bitcast_v4f64(<4 x double> %a0) {
-; AVX1-LABEL: movmskps_allof_bitcast_v4f64:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm1
-; AVX1-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0
-; AVX1-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
-; AVX1-NEXT: vtestpd %ymm1, %ymm0
-; AVX1-NEXT: setb %al
-; AVX1-NEXT: vzeroupper
-; AVX1-NEXT: retq
-;
-; AVX2-LABEL: movmskps_allof_bitcast_v4f64:
-; AVX2: # %bb.0:
-; AVX2-NEXT: vxorpd %xmm1, %xmm1, %xmm1
-; AVX2-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0
-; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
-; AVX2-NEXT: vtestpd %ymm1, %ymm0
-; AVX2-NEXT: setb %al
-; AVX2-NEXT: vzeroupper
-; AVX2-NEXT: retq
-;
-; ADL-LABEL: movmskps_allof_bitcast_v4f64:
-; ADL: # %bb.0:
-; ADL-NEXT: vxorpd %xmm1, %xmm1, %xmm1
-; ADL-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0
-; ADL-NEXT: vmovmskpd %ymm0, %eax
-; ADL-NEXT: cmpl $15, %eax
-; ADL-NEXT: sete %al
-; ADL-NEXT: vzeroupper
-; ADL-NEXT: retq
+; VTEST-AVX1-LABEL: movmskps_allof_bitcast_v4f64:
+; VTEST-AVX1: # %bb.0:
+; VTEST-AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm1
+; VTEST-AVX1-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0
+; VTEST-AVX1-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
+; VTEST-AVX1-NEXT: vtestpd %ymm1, %ymm0
+; VTEST-AVX1-NEXT: setb %al
+; VTEST-AVX1-NEXT: vzeroupper
+; VTEST-AVX1-NEXT: retq
+;
+; VTEST-AVX2-LABEL: movmskps_allof_bitcast_v4f64:
+; VTEST-AVX2: # %bb.0:
+; VTEST-AVX2-NEXT: vxorpd %xmm1, %xmm1, %xmm1
+; VTEST-AVX2-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0
+; VTEST-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
+; VTEST-AVX2-NEXT: vtestpd %ymm1, %ymm0
+; VTEST-AVX2-NEXT: setb %al
+; VTEST-AVX2-NEXT: vzeroupper
+; VTEST-AVX2-NEXT: retq
+;
+; MOVMSK-LABEL: movmskps_allof_bitcast_v4f64:
+; MOVMSK: # %bb.0:
+; MOVMSK-NEXT: vxorpd %xmm1, %xmm1, %xmm1
+; MOVMSK-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0
+; MOVMSK-NEXT: vmovmskpd %ymm0, %eax
+; MOVMSK-NEXT: cmpl $15, %eax
+; MOVMSK-NEXT: sete %al
+; MOVMSK-NEXT: vzeroupper
+; MOVMSK-NEXT: retq
%1 = fcmp oeq <4 x double> %a0, zeroinitializer
%2 = sext <4 x i1> %1 to <4 x i64>
%3 = bitcast <4 x i64> %2 to <8 x float>
@@ -78,26 +79,35 @@ define i1 @movmskps_allof_bitcast_v4f64(<4 x double> %a0) {
;
define i32 @movmskpd_cmpgt_v4i64(<4 x i64> %a0) {
-; AVX1-LABEL: movmskpd_cmpgt_v4i64:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; AVX1-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm1
-; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3]
-; AVX1-NEXT: vmovmskpd %ymm0, %eax
-; AVX1-NEXT: vzeroupper
-; AVX1-NEXT: retq
-;
-; AVX2-LABEL: movmskpd_cmpgt_v4i64:
-; AVX2: # %bb.0:
-; AVX2-NEXT: vmovmskpd %ymm0, %eax
-; AVX2-NEXT: vzeroupper
-; AVX2-NEXT: retq
-;
-; ADL-LABEL: movmskpd_cmpgt_v4i64:
-; ADL: # %bb.0:
-; ADL-NEXT: vmovmskpd %ymm0, %eax
-; ADL-NEXT: vzeroupper
-; ADL-NEXT: retq
+; VTEST-AVX1-LABEL: movmskpd_cmpgt_v4i64:
+; VTEST-AVX1: # %bb.0:
+; VTEST-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; VTEST-AVX1-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm1
+; VTEST-AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3]
+; VTEST-AVX1-NEXT: vmovmskpd %ymm0, %eax
+; VTEST-AVX1-NEXT: vzeroupper
+; VTEST-AVX1-NEXT: retq
+;
+; VTEST-AVX2-LABEL: movmskpd_cmpgt_v4i64:
+; VTEST-AVX2: # %bb.0:
+; VTEST-AVX2-NEXT: vmovmskpd %ymm0, %eax
+; VTEST-AVX2-NEXT: vzeroupper
+; VTEST-AVX2-NEXT: retq
+;
+; MOVMSK-AVX1-LABEL: movmskpd_cmpgt_v4i64:
+; MOVMSK-AVX1: # %bb.0:
+; MOVMSK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
+; MOVMSK-AVX1-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm1
+; MOVMSK-AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3]
+; MOVMSK-AVX1-NEXT: vmovmskpd %ymm0, %eax
+; MOVMSK-AVX1-NEXT: vzeroupper
+; MOVMSK-AVX1-NEXT: retq
+;
+; MOVMSK-AVX2-LABEL: movmskpd_cmpgt_v4i64:
+; MOVMSK-AVX2: # %bb.0:
+; MOVMSK-AVX2-NEXT: vmovmskpd %ymm0, %eax
+; MOVMSK-AVX2-NEXT: vzeroupper
+; MOVMSK-AVX2-NEXT: retq
%1 = icmp sgt <4 x i64> zeroinitializer, %a0
%2 = sext <4 x i1> %1 to <4 x i64>
%3 = bitcast <4 x i64> %2 to <4 x double>
@@ -106,25 +116,33 @@ define i32 @movmskpd_cmpgt_v4i64(<4 x i64> %a0) {
}
define i32 @movmskps_ashr_v8i32(<8 x i32> %a0) {
-; AVX1-LABEL: movmskps_ashr_v8i32:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vpsrad $31, %xmm0, %xmm1
-; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7]
-; AVX1-NEXT: vmovmskps %ymm0, %eax
-; AVX1-NEXT: vzeroupper
-; AVX1-NEXT: retq
-;
-; AVX2-LABEL: movmskps_ashr_v8i32:
-; AVX2: # %bb.0:
-; AVX2-NEXT: vmovmskps %ymm0, %eax
-; AVX2-NEXT: vzeroupper
-; AVX2-NEXT: retq
-;
-; ADL-LABEL: movmskps_ashr_v8i32:
-; ADL: # %bb.0:
-; ADL-NEXT: vmovmskps %ymm0, %eax
-; ADL-NEXT: vzeroupper
-; ADL-NEXT: retq
+; VTEST-AVX1-LABEL: movmskps_ashr_v8i32:
+; VTEST-AVX1: # %bb.0:
+; VTEST-AVX1-NEXT: vpsrad $31, %xmm0, %xmm1
+; VTEST-AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7]
+; VTEST-AVX1-NEXT: vmovmskps %ymm0, %eax
+; VTEST-AVX1-NEXT: vzeroupper
+; VTEST-AVX1-NEXT: retq
+;
+; VTEST-AVX2-LABEL: movmskps_ashr_v8i32:
+; VTEST-AVX2: # %bb.0:
+; VTEST-AVX2-NEXT: vmovmskps %ymm0, %eax
+; VTEST-AVX2-NEXT: vzeroupper
+; VTEST-AVX2-NEXT: retq
+;
+; MOVMSK-AVX1-LABEL: movmskps_ashr_v8i32:
+; MOVMSK-AVX1: # %bb.0:
+; MOVMSK-AVX1-NEXT: vpsrad $31, %xmm0, %xmm1
+; MOVMSK-AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7]
+; MOVMSK-AVX1-NEXT: vmovmskps %ymm0, %eax
+; MOVMSK-AVX1-NEXT: vzeroupper
+; MOVMSK-AVX1-NEXT: retq
+;
+; MOVMSK-AVX2-LABEL: movmskps_ashr_v8i32:
+; MOVMSK-AVX2: # %bb.0:
+; MOVMSK-AVX2-NEXT: vmovmskps %ymm0, %eax
+; MOVMSK-AVX2-NEXT: vzeroupper
+; MOVMSK-AVX2-NEXT: retq
%1 = ashr <8 x i32> %a0, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
%2 = bitcast <8 x i32> %1 to <8 x float>
%3 = tail call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %2)
@@ -132,29 +150,39 @@ define i32 @movmskps_ashr_v8i32(<8 x i32> %a0) {
}
define i32 @movmskps_sext_v4i64(<4 x i32> %a0) {
-; AVX1-LABEL: movmskps_sext_v4i64:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vpmovsxdq %xmm0, %xmm1
-; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
-; AVX1-NEXT: vpmovsxdq %xmm0, %xmm0
-; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
-; AVX1-NEXT: vmovmskpd %ymm0, %eax
-; AVX1-NEXT: vzeroupper
-; AVX1-NEXT: retq
-;
-; AVX2-LABEL: movmskps_sext_v4i64:
-; AVX2: # %bb.0:
-; AVX2-NEXT: vpmovsxdq %xmm0, %ymm0
-; AVX2-NEXT: vmovmskpd %ymm0, %eax
-; AVX2-NEXT: vzeroupper
-; AVX2-NEXT: retq
-;
-; ADL-LABEL: movmskps_sext_v4i64:
-; ADL: # %bb.0:
-; ADL-NEXT: vpmovsxdq %xmm0, %ymm0
-; ADL-NEXT: vmovmskpd %ymm0, %eax
-; ADL-NEXT: vzeroupper
-; ADL-NEXT: retq
+; VTEST-AVX1-LABEL: movmskps_sext_v4i64:
+; VTEST-AVX1: # %bb.0:
+; VTEST-AVX1-NEXT: vpmovsxdq %xmm0, %xmm1
+; VTEST-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
+; VTEST-AVX1-NEXT: vpmovsxdq %xmm0, %xmm0
+; VTEST-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; VTEST-AVX1-NEXT: vmovmskpd %ymm0, %eax
+; VTEST-AVX1-NEXT: vzeroupper
+; VTEST-AVX1-NEXT: retq
+;
+; VTEST-AVX2-LABEL: movmskps_sext_v4i64:
+; VTEST-AVX2: # %bb.0:
+; VTEST-AVX2-NEXT: vpmovsxdq %xmm0, %ymm0
+; VTEST-AVX2-NEXT: vmovmskpd %ymm0, %eax
+; VTEST-AVX2-NEXT: vzeroupper
+; VTEST-AVX2-NEXT: retq
+;
+; MOVMSK-AVX1-LABEL: movmskps_sext_v4i64:
+; MOVMSK-AVX1: # %bb.0:
+; MOVMSK-AVX1-NEXT: vpmovsxdq %xmm0, %xmm1
+; MOVMSK-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
+; MOVMSK-AVX1-NEXT: vpmovsxdq %xmm0, %xmm0
+; MOVMSK-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; MOVMSK-AVX1-NEXT: vmovmskpd %ymm0, %eax
+; MOVMSK-AVX1-NEXT: vzeroupper
+; MOVMSK-AVX1-NEXT: retq
+;
+; MOVMSK-AVX2-LABEL: movmskps_sext_v4i64:
+; MOVMSK-AVX2: # %bb.0:
+; MOVMSK-AVX2-NEXT: vpmovsxdq %xmm0, %ymm0
+; MOVMSK-AVX2-NEXT: vmovmskpd %ymm0, %eax
+; MOVMSK-AVX2-NEXT: vzeroupper
+; MOVMSK-AVX2-NEXT: retq
%1 = sext <4 x i32> %a0 to <4 x i64>
%2 = bitcast <4 x i64> %1 to <4 x double>
%3 = tail call i32 @llvm.x86.avx.movmsk.pd.256(<4 x double> %2)
@@ -162,29 +190,39 @@ define i32 @movmskps_sext_v4i64(<4 x i32> %a0) {
}
define i32 @movmskps_sext_v8i32(<8 x i16> %a0) {
-; AVX1-LABEL: movmskps_sext_v8i32:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vpmovsxwd %xmm0, %xmm1
-; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
-; AVX1-NEXT: vpmovsxwd %xmm0, %xmm0
-; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
-; AVX1-NEXT: vmovmskps %ymm0, %eax
-; AVX1-NEXT: vzeroupper
-; AVX1-NEXT: retq
-;
-; AVX2-LABEL: movmskps_sext_v8i32:
-; AVX2: # %bb.0:
-; AVX2-NEXT: vpmovsxwd %xmm0, %ymm0
-; AVX2-NEXT: vmovmskps %ymm0, %eax
-; AVX2-NEXT: vzeroupper
-; AVX2-NEXT: retq
-;
-; ADL-LABEL: movmskps_sext_v8i32:
-; ADL: # %bb.0:
-; ADL-NEXT: vpmovsxwd %xmm0, %ymm0
-; ADL-NEXT: vmovmskps %ymm0, %eax
-; ADL-NEXT: vzeroupper
-; ADL-NEXT: retq
+; VTEST-AVX1-LABEL: movmskps_sext_v8i32:
+; VTEST-AVX1: # %bb.0:
+; VTEST-AVX1-NEXT: vpmovsxwd %xmm0, %xmm1
+; VTEST-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
+; VTEST-AVX1-NEXT: vpmovsxwd %xmm0, %xmm0
+; VTEST-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; VTEST-AVX1-NEXT: vmovmskps %ymm0, %eax
+; VTEST-AVX1-NEXT: vzeroupper
+; VTEST-AVX1-NEXT: retq
+;
+; VTEST-AVX2-LABEL: movmskps_sext_v8i32:
+; VTEST-AVX2: # %bb.0:
+; VTEST-AVX2-NEXT: vpmovsxwd %xmm0, %ymm0
+; VTEST-AVX2-NEXT: vmovmskps %ymm0, %eax
+; VTEST-AVX2-NEXT: vzeroupper
+; VTEST-AVX2-NEXT: retq
+;
+; MOVMSK-AVX1-LABEL: movmskps_sext_v8i32:
+; MOVMSK-AVX1: # %bb.0:
+; MOVMSK-AVX1-NEXT: vpmovsxwd %xmm0, %xmm1
+; MOVMSK-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
+; MOVMSK-AVX1-NEXT: vpmovsxwd %xmm0, %xmm0
+; MOVMSK-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; MOVMSK-AVX1-NEXT: vmovmskps %ymm0, %eax
+; MOVMSK-AVX1-NEXT: vzeroupper
+; MOVMSK-AVX1-NEXT: retq
+;
+; MOVMSK-AVX2-LABEL: movmskps_sext_v8i32:
+; MOVMSK-AVX2: # %bb.0:
+; MOVMSK-AVX2-NEXT: vpmovsxwd %xmm0, %ymm0
+; MOVMSK-AVX2-NEXT: vmovmskps %ymm0, %eax
+; MOVMSK-AVX2-NEXT: vzeroupper
+; MOVMSK-AVX2-NEXT: retq
%1 = sext <8 x i16> %a0 to <8 x i32>
%2 = bitcast <8 x i32> %1 to <8 x float>
%3 = tail call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %2)
@@ -192,23 +230,23 @@ define i32 @movmskps_sext_v8i32(<8 x i16> %a0) {
}
define i32 @movmskps_concat_v4f32(<4 x float> %a0, <4 x float> %a1) {
-; CHECK-LABEL: movmskps_concat_v4f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vorps %xmm1, %xmm0, %xmm0
-; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: vtestps %xmm0, %xmm0
-; CHECK-NEXT: setne %al
-; CHECK-NEXT: negl %eax
-; CHECK-NEXT: retq
+; VTEST-LABEL: movmskps_concat_v4f32:
+; VTEST: # %bb.0:
+; VTEST-NEXT: vorps %xmm1, %xmm0, %xmm0
+; VTEST-NEXT: xorl %eax, %eax
+; VTEST-NEXT: vtestps %xmm0, %xmm0
+; VTEST-NEXT: setne %al
+; VTEST-NEXT: negl %eax
+; VTEST-NEXT: retq
;
-; ADL-LABEL: movmskps_concat_v4f32:
-; ADL: # %bb.0:
-; ADL-NEXT: vorps %xmm1, %xmm0, %xmm0
-; ADL-NEXT: vmovmskps %xmm0, %ecx
-; ADL-NEXT: xorl %eax, %eax
-; ADL-NEXT: negl %ecx
-; ADL-NEXT: sbbl %eax, %eax
-; ADL-NEXT: retq
+; MOVMSK-LABEL: movmskps_concat_v4f32:
+; MOVMSK: # %bb.0:
+; MOVMSK-NEXT: vorps %xmm1, %xmm0, %xmm0
+; MOVMSK-NEXT: vmovmskps %xmm0, %ecx
+; MOVMSK-NEXT: xorl %eax, %eax
+; MOVMSK-NEXT: negl %ecx
+; MOVMSK-NEXT: sbbl %eax, %eax
+; MOVMSK-NEXT: retq
%1 = shufflevector <4 x float> %a0, <4 x float> %a1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%2 = tail call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %1)
%3 = icmp ne i32 %2, 0
@@ -225,15 +263,6 @@ define i32 @movmskps_demanded_concat_v4f32(<4 x float> %a0, <4 x float> %a1) {
; CHECK-NEXT: negl %ecx
; CHECK-NEXT: sbbl %eax, %eax
; CHECK-NEXT: retq
-;
-; ADL-LABEL: movmskps_demanded_concat_v4f32:
-; ADL: # %bb.0:
-; ADL-NEXT: vmovmskps %xmm0, %ecx
-; ADL-NEXT: andl $3, %ecx
-; ADL-NEXT: xorl %eax, %eax
-; ADL-NEXT: negl %ecx
-; ADL-NEXT: sbbl %eax, %eax
-; ADL-NEXT: retq
%1 = shufflevector <4 x float> %a0, <4 x float> %a1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%2 = tail call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %1)
%3 = and i32 %2, 3
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