[llvm] [NFC] clang-format utils/TableGen (PR #80973)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 7 03:07:54 PST 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-selectiondag
Author: Pierre van Houtryve (Pierre-vh)
<details>
<summary>Changes</summary>
```
find llvm/utils/TableGen -iname "*.h" -o -iname "*.cpp" | xargs clang-format-16 -i
```
Split from #<!-- -->80847 - there is quite a bit more reformatting going on here because this is a full reformating of every file.
---
Patch is 691.81 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/80973.diff
61 Files Affected:
- (modified) llvm/utils/TableGen/AsmMatcherEmitter.cpp (+326-267)
- (modified) llvm/utils/TableGen/AsmWriterEmitter.cpp (+135-107)
- (modified) llvm/utils/TableGen/AsmWriterInst.cpp (+36-33)
- (modified) llvm/utils/TableGen/AsmWriterInst.h (+83-83)
- (modified) llvm/utils/TableGen/CTagsEmitter.cpp (+6-2)
- (modified) llvm/utils/TableGen/CallingConvEmitter.cpp (+26-22)
- (modified) llvm/utils/TableGen/CodeEmitterGen.cpp (+24-17)
- (modified) llvm/utils/TableGen/CodeGenDAGPatterns.cpp (+280-299)
- (modified) llvm/utils/TableGen/CodeGenDAGPatterns.h (+96-113)
- (modified) llvm/utils/TableGen/CodeGenHwModes.cpp (+8-8)
- (modified) llvm/utils/TableGen/CodeGenHwModes.h (+35-35)
- (modified) llvm/utils/TableGen/CodeGenInstruction.cpp (+72-75)
- (modified) llvm/utils/TableGen/CodeGenInstruction.h (+296-300)
- (modified) llvm/utils/TableGen/CodeGenIntrinsics.h (+7-9)
- (modified) llvm/utils/TableGen/CodeGenMapTable.cpp (+67-65)
- (modified) llvm/utils/TableGen/CodeGenRegisters.cpp (+148-138)
- (modified) llvm/utils/TableGen/CodeGenRegisters.h (+671-683)
- (modified) llvm/utils/TableGen/CodeGenSchedule.cpp (+166-172)
- (modified) llvm/utils/TableGen/CodeGenSchedule.h (+25-24)
- (modified) llvm/utils/TableGen/CodeGenTarget.cpp (+30-32)
- (modified) llvm/utils/TableGen/CodeGenTarget.h (+21-17)
- (modified) llvm/utils/TableGen/DAGISelEmitter.cpp (+22-13)
- (modified) llvm/utils/TableGen/DAGISelMatcher.cpp (+35-39)
- (modified) llvm/utils/TableGen/DAGISelMatcher.h (+249-269)
- (modified) llvm/utils/TableGen/DAGISelMatcherEmitter.cpp (+83-84)
- (modified) llvm/utils/TableGen/DAGISelMatcherGen.cpp (+149-155)
- (modified) llvm/utils/TableGen/DAGISelMatcherOpt.cpp (+2-3)
- (modified) llvm/utils/TableGen/DFAEmitter.cpp (+4-6)
- (modified) llvm/utils/TableGen/DFAPacketizerEmitter.cpp (+3-3)
- (modified) llvm/utils/TableGen/DXILEmitter.cpp (+5-4)
- (modified) llvm/utils/TableGen/DecoderEmitter.cpp (+70-66)
- (modified) llvm/utils/TableGen/DisassemblerEmitter.cpp (+2-2)
- (modified) llvm/utils/TableGen/FastISelEmitter.cpp (+75-64)
- (modified) llvm/utils/TableGen/InfoByHwMode.cpp (+30-33)
- (modified) llvm/utils/TableGen/InfoByHwMode.h (+17-24)
- (modified) llvm/utils/TableGen/InstrDocsEmitter.cpp (+18-8)
- (modified) llvm/utils/TableGen/InstrInfoEmitter.cpp (+108-70)
- (modified) llvm/utils/TableGen/IntrinsicEmitter.cpp (+21-21)
- (modified) llvm/utils/TableGen/OptParserEmitter.cpp (+4-5)
- (modified) llvm/utils/TableGen/PredicateExpander.cpp (+2-2)
- (modified) llvm/utils/TableGen/PseudoLoweringEmitter.cpp (+48-46)
- (modified) llvm/utils/TableGen/RegisterBankEmitter.cpp (+6-4)
- (modified) llvm/utils/TableGen/RegisterInfoEmitter.cpp (+111-115)
- (modified) llvm/utils/TableGen/SDNodeProperties.h (+1-1)
- (modified) llvm/utils/TableGen/SearchableTableEmitter.cpp (+22-20)
- (modified) llvm/utils/TableGen/SequenceToOffsetTable.h (+6-6)
- (modified) llvm/utils/TableGen/SubtargetEmitter.cpp (+189-190)
- (modified) llvm/utils/TableGen/SubtargetFeatureInfo.cpp (+1-1)
- (modified) llvm/utils/TableGen/SubtargetFeatureInfo.h (+2-1)
- (modified) llvm/utils/TableGen/TableGenBackends.h (-2)
- (modified) llvm/utils/TableGen/Types.cpp (+3-1)
- (modified) llvm/utils/TableGen/Types.h (+1-1)
- (modified) llvm/utils/TableGen/WebAssemblyDisassemblerEmitter.cpp (+4-2)
- (modified) llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp (+6-5)
- (modified) llvm/utils/TableGen/X86DisassemblerShared.h (+1-3)
- (modified) llvm/utils/TableGen/X86DisassemblerTables.cpp (+13-8)
- (modified) llvm/utils/TableGen/X86DisassemblerTables.h (+22-30)
- (modified) llvm/utils/TableGen/X86ModRMFilters.cpp (+6-6)
- (modified) llvm/utils/TableGen/X86ModRMFilters.h (+14-15)
- (modified) llvm/utils/TableGen/X86RecognizableInstr.cpp (+2-1)
- (modified) llvm/utils/TableGen/X86RecognizableInstr.h (+2-1)
``````````diff
diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
index 011d96a48d61d..9065885618069 100644
--- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
@@ -140,10 +140,11 @@ class AsmMatcherInfo;
// RegisterSets can be seen in the outputted AsmMatcher tables occasionally, and
// can even affect compiler output (at least seen in diagnostics produced when
// all matches fail). So we use a type that sorts them consistently.
-typedef std::set<Record*, LessRecordByID> RegisterSet;
+typedef std::set<Record *, LessRecordByID> RegisterSet;
class AsmMatcherEmitter {
RecordKeeper &Records;
+
public:
AsmMatcherEmitter(RecordKeeper &R) : Records(R) {}
@@ -166,7 +167,7 @@ struct ClassInfo {
/// The (first) user defined class, subsequent user defined classes are
/// UserClass0+1, and so on.
- UserClass0 = 1<<16
+ UserClass0 = 1 << 16
};
/// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
@@ -176,7 +177,7 @@ struct ClassInfo {
/// SuperClasses - The super classes of this class. Note that for simplicities
/// sake user operands only record their immediate super class, while register
/// operands include all superclasses.
- std::vector<ClassInfo*> SuperClasses;
+ std::vector<ClassInfo *> SuperClasses;
/// Name - The full class name, suitable for use in an enum.
std::string Name;
@@ -204,10 +205,12 @@ struct ClassInfo {
/// For register classes: the records for all the registers in this class.
RegisterSet Registers;
- /// For custom match classes: the diagnostic kind for when the predicate fails.
+ /// For custom match classes: the diagnostic kind for when the predicate
+ /// fails.
std::string DiagnosticType;
- /// For custom match classes: the diagnostic string for when the predicate fails.
+ /// For custom match classes: the diagnostic string for when the predicate
+ /// fails.
std::string DiagnosticString;
/// Is this operand optional and not always required.
@@ -224,9 +227,7 @@ struct ClassInfo {
}
/// isUserClass() - Check if this is a user defined class.
- bool isUserClass() const {
- return Kind >= UserClass0;
- }
+ bool isUserClass() const { return Kind >= UserClass0; }
/// isRelatedTo - Check whether this class is "related" to \p RHS. Classes
/// are related if they are in the same class hierarchy.
@@ -244,8 +245,8 @@ struct ClassInfo {
RegisterSet Tmp;
std::insert_iterator<RegisterSet> II(Tmp, Tmp.begin());
std::set_intersection(Registers.begin(), Registers.end(),
- RHS.Registers.begin(), RHS.Registers.end(),
- II, LessRecordByID());
+ RHS.Registers.begin(), RHS.Registers.end(), II,
+ LessRecordByID());
return !Tmp.empty();
}
@@ -469,7 +470,7 @@ struct MatchableInfo {
unsigned SrcOperand2) {
ResOperand X;
X.Kind = TiedOperand;
- X.TiedOperands = { TiedOperandNum, SrcOperand1, SrcOperand2 };
+ X.TiedOperands = {TiedOperandNum, SrcOperand1, SrcOperand2};
X.MINumOperands = 1;
return X;
}
@@ -503,7 +504,7 @@ struct MatchableInfo {
Record *const TheDef;
/// DefRec - This is the definition that it came from.
- PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec;
+ PointerUnion<const CodeGenInstruction *, const CodeGenInstAlias *> DefRec;
const CodeGenInstruction *getResultInst() const {
if (isa<const CodeGenInstruction *>(DefRec))
@@ -542,16 +543,13 @@ struct MatchableInfo {
bool UseInstAsmMatchConverter;
MatchableInfo(const CodeGenInstruction &CGI)
- : AsmVariantID(0), AsmString(CGI.AsmString), TheDef(CGI.TheDef), DefRec(&CGI),
- UseInstAsmMatchConverter(true) {
- }
+ : AsmVariantID(0), AsmString(CGI.AsmString), TheDef(CGI.TheDef),
+ DefRec(&CGI), UseInstAsmMatchConverter(true) {}
MatchableInfo(std::unique_ptr<const CodeGenInstAlias> Alias)
- : AsmVariantID(0), AsmString(Alias->AsmString), TheDef(Alias->TheDef),
- DefRec(Alias.release()),
- UseInstAsmMatchConverter(
- TheDef->getValueAsBit("UseInstAsmMatchConverter")) {
- }
+ : AsmVariantID(0), AsmString(Alias->AsmString), TheDef(Alias->TheDef),
+ DefRec(Alias.release()), UseInstAsmMatchConverter(TheDef->getValueAsBit(
+ "UseInstAsmMatchConverter")) {}
// Could remove this and the dtor if PointerUnion supported unique_ptr
// elements with a dynamic failure/assertion (like the one below) in the case
@@ -576,9 +574,8 @@ struct MatchableInfo {
void formTwoOperandAlias(StringRef Constraint);
void initialize(const AsmMatcherInfo &Info,
- SmallPtrSetImpl<Record*> &SingletonRegisters,
- AsmVariantInfo const &Variant,
- bool HasMnemonicFirst);
+ SmallPtrSetImpl<Record *> &SingletonRegisters,
+ AsmVariantInfo const &Variant, bool HasMnemonicFirst);
/// validate - Return true if this matchable is a valid thing to match against
/// and perform a bunch of validity checking.
@@ -603,9 +600,9 @@ struct MatchableInfo {
}
int findAsmOperandOriginallyNamed(StringRef N) const {
- auto I =
- find_if(AsmOperands,
- [&](const AsmOperand &Op) { return Op.OrigSrcOpName == N; });
+ auto I = find_if(AsmOperands, [&](const AsmOperand &Op) {
+ return Op.OrigSrcOpName == N;
+ });
return (I != AsmOperands.end()) ? I - AsmOperands.begin() : -1;
}
@@ -706,7 +703,7 @@ struct MatchableInfo {
struct OperandMatchEntry {
unsigned OperandMask;
- const MatchableInfo* MI;
+ const MatchableInfo *MI;
ClassInfo *CI;
static OperandMatchEntry create(const MatchableInfo *mi, ClassInfo *ci,
@@ -740,21 +737,21 @@ class AsmMatcherInfo {
std::vector<OperandMatchEntry> OperandMatchInfo;
/// Map of Register records to their class information.
- typedef std::map<Record*, ClassInfo*, LessRecordByID> RegisterClassesTy;
+ typedef std::map<Record *, ClassInfo *, LessRecordByID> RegisterClassesTy;
RegisterClassesTy RegisterClasses;
/// Map of Predicate records to their subtarget information.
std::map<Record *, SubtargetFeatureInfo, LessRecordByID> SubtargetFeatures;
/// Map of AsmOperandClass records to their class information.
- std::map<Record*, ClassInfo*> AsmOperandClasses;
+ std::map<Record *, ClassInfo *> AsmOperandClasses;
/// Map of RegisterClass records to their class information.
- std::map<Record*, ClassInfo*> RegisterClassClasses;
+ std::map<Record *, ClassInfo *> RegisterClassClasses;
private:
/// Map of token to class information which has already been constructed.
- std::map<std::string, ClassInfo*> TokenClasses;
+ std::map<std::string, ClassInfo *> TokenClasses;
private:
/// getTokenClass - Lookup or create the class for the given token.
@@ -767,7 +764,7 @@ class AsmMatcherInfo {
/// buildRegisterClasses - Build the ClassInfo* instances for register
/// classes.
- void buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters);
+ void buildRegisterClasses(SmallPtrSetImpl<Record *> &SingletonRegisters);
/// buildOperandClasses - Build the ClassInfo* instances for user defined
/// operand classes.
@@ -779,8 +776,7 @@ class AsmMatcherInfo {
MatchableInfo::AsmOperand &Op);
public:
- AsmMatcherInfo(Record *AsmParser,
- CodeGenTarget &Target,
+ AsmMatcherInfo(Record *AsmParser, CodeGenTarget &Target,
RecordKeeper &Records);
/// Construct the various tables used during matching.
@@ -798,9 +794,7 @@ class AsmMatcherInfo {
return I == SubtargetFeatures.end() ? nullptr : &I->second;
}
- RecordKeeper &getRecords() const {
- return Records;
- }
+ RecordKeeper &getRecords() const { return Records; }
bool hasOptionalOperands() const {
return any_of(Classes,
@@ -812,7 +806,8 @@ class AsmMatcherInfo {
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
LLVM_DUMP_METHOD void MatchableInfo::dump() const {
- errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n";
+ errs() << TheDef->getName() << " -- "
+ << "flattened:\"" << AsmString << "\"\n";
errs() << " variant: " << AsmVariantID << "\n";
@@ -850,7 +845,7 @@ parseTwoOperandConstraint(StringRef S, ArrayRef<SMLoc> Loc) {
void MatchableInfo::formTwoOperandAlias(StringRef Constraint) {
// Figure out which operands are aliased and mark them as tied.
std::pair<StringRef, StringRef> Ops =
- parseTwoOperandConstraint(Constraint, TheDef->getLoc());
+ parseTwoOperandConstraint(Constraint, TheDef->getLoc());
// Find the AsmOperands that refer to the operands we're aliasing.
int SrcAsmOperand = findAsmOperandNamed(Ops.first);
@@ -858,11 +853,11 @@ void MatchableInfo::formTwoOperandAlias(StringRef Constraint) {
if (SrcAsmOperand == -1)
PrintFatalError(TheDef->getLoc(),
"unknown source two-operand alias operand '" + Ops.first +
- "'.");
+ "'.");
if (DstAsmOperand == -1)
PrintFatalError(TheDef->getLoc(),
"unknown destination two-operand alias operand '" +
- Ops.second + "'.");
+ Ops.second + "'.");
// Find the ResOperand that refers to the operand we're aliasing away
// and update it to refer to the combined operand instead.
@@ -878,7 +873,7 @@ void MatchableInfo::formTwoOperandAlias(StringRef Constraint) {
// Adjust the ResOperand references to any AsmOperands that followed
// the one we just deleted.
for (ResOperand &Op : ResOperands) {
- switch(Op.Kind) {
+ switch (Op.Kind) {
default:
// Nothing to do for operands that don't reference AsmOperands.
break;
@@ -892,10 +887,9 @@ void MatchableInfo::formTwoOperandAlias(StringRef Constraint) {
/// extractSingletonRegisterForAsmOperand - Extract singleton register,
/// if present, from specified token.
-static void
-extractSingletonRegisterForAsmOperand(MatchableInfo::AsmOperand &Op,
- const AsmMatcherInfo &Info,
- StringRef RegisterPrefix) {
+static void extractSingletonRegisterForAsmOperand(MatchableInfo::AsmOperand &Op,
+ const AsmMatcherInfo &Info,
+ StringRef RegisterPrefix) {
StringRef Tok = Op.Token;
// If this token is not an isolated token, i.e., it isn't separated from
@@ -922,13 +916,12 @@ extractSingletonRegisterForAsmOperand(MatchableInfo::AsmOperand &Op,
}
void MatchableInfo::initialize(const AsmMatcherInfo &Info,
- SmallPtrSetImpl<Record*> &SingletonRegisters,
+ SmallPtrSetImpl<Record *> &SingletonRegisters,
AsmVariantInfo const &Variant,
bool HasMnemonicFirst) {
AsmVariantID = Variant.AsmVariantNo;
- AsmString =
- CodeGenInstruction::FlattenAsmStringVariants(AsmString,
- Variant.AsmVariantNo);
+ AsmString = CodeGenInstruction::FlattenAsmStringVariants(
+ AsmString, Variant.AsmVariantNo);
tokenizeAsmString(Info, Variant);
@@ -936,7 +929,7 @@ void MatchableInfo::initialize(const AsmMatcherInfo &Info,
// simple string, not a $foo variable or a singleton register.
if (AsmOperands.empty())
PrintFatalError(TheDef->getLoc(),
- "Instruction '" + TheDef->getName() + "' has no tokens");
+ "Instruction '" + TheDef->getName() + "' has no tokens");
assert(!AsmOperands[0].Token.empty());
if (HasMnemonicFirst) {
@@ -1045,7 +1038,7 @@ void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info,
size_t EndPos = String.find('}', i);
assert(EndPos != StringRef::npos &&
"Missing brace in operand reference!");
- addAsmOperand(String.slice(i, EndPos+1), IsIsolatedToken);
+ addAsmOperand(String.slice(i, EndPos + 1), IsIsolatedToken);
Prev = EndPos + 1;
i = EndPos;
IsIsolatedToken = false;
@@ -1070,16 +1063,16 @@ bool MatchableInfo::validate(StringRef CommentDelimiter, bool IsAlias) const {
// isCodeGenOnly if they are pseudo instructions.
if (AsmString.find('\n') != std::string::npos)
PrintFatalError(TheDef->getLoc(),
- "multiline instruction is not valid for the asmparser, "
- "mark it isCodeGenOnly");
+ "multiline instruction is not valid for the asmparser, "
+ "mark it isCodeGenOnly");
// Remove comments from the asm string. We know that the asmstring only
// has one line.
if (!CommentDelimiter.empty() &&
StringRef(AsmString).contains(CommentDelimiter))
PrintFatalError(TheDef->getLoc(),
- "asmstring for instruction has comment character in it, "
- "mark it isCodeGenOnly");
+ "asmstring for instruction has comment character in it, "
+ "mark it isCodeGenOnly");
// Reject matchables with operand modifiers, these aren't something we can
// handle, the target should be refactored to use operands instead of
@@ -1092,17 +1085,17 @@ bool MatchableInfo::validate(StringRef CommentDelimiter, bool IsAlias) const {
for (const AsmOperand &Op : AsmOperands) {
StringRef Tok = Op.Token;
if (Tok[0] == '$' && Tok.contains(':'))
- PrintFatalError(TheDef->getLoc(),
- "matchable with operand modifier '" + Tok +
- "' not supported by asm matcher. Mark isCodeGenOnly!");
+ PrintFatalError(
+ TheDef->getLoc(),
+ "matchable with operand modifier '" + Tok +
+ "' not supported by asm matcher. Mark isCodeGenOnly!");
// Verify that any operand is only mentioned once.
// We reject aliases and ignore instructions for now.
if (!IsAlias && TheDef->getValueAsString("AsmMatchConverter").empty() &&
Tok[0] == '$' && !OperandNames.insert(std::string(Tok)).second) {
LLVM_DEBUG({
errs() << "warning: '" << TheDef->getName() << "': "
- << "ignoring instruction with tied operand '"
- << Tok << "'\n";
+ << "ignoring instruction with tied operand '" << Tok << "'\n";
});
return false;
}
@@ -1116,15 +1109,33 @@ static std::string getEnumNameForToken(StringRef Str) {
for (char C : Str) {
switch (C) {
- case '*': Res += "_STAR_"; break;
- case '%': Res += "_PCT_"; break;
- case ':': Res += "_COLON_"; break;
- case '!': Res += "_EXCLAIM_"; break;
- case '.': Res += "_DOT_"; break;
- case '<': Res += "_LT_"; break;
- case '>': Res += "_GT_"; break;
- case '-': Res += "_MINUS_"; break;
- case '#': Res += "_HASH_"; break;
+ case '*':
+ Res += "_STAR_";
+ break;
+ case '%':
+ Res += "_PCT_";
+ break;
+ case ':':
+ Res += "_COLON_";
+ break;
+ case '!':
+ Res += "_EXCLAIM_";
+ break;
+ case '.':
+ Res += "_DOT_";
+ break;
+ case '<':
+ Res += "_LT_";
+ break;
+ case '>':
+ Res += "_GT_";
+ break;
+ case '-':
+ Res += "_MINUS_";
+ break;
+ case '#':
+ Res += "_HASH_";
+ break;
default:
if (isAlnum(C))
Res += C;
@@ -1166,8 +1177,7 @@ AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI,
return getOperandClass(Rec, SubOpIdx);
}
-ClassInfo *
-AsmMatcherInfo::getOperandClass(Record *Rec, int SubOpIdx) {
+ClassInfo *AsmMatcherInfo::getOperandClass(Record *Rec, int SubOpIdx) {
if (Rec->isSubClassOf("RegisterOperand")) {
// RegisterOperand may have an associated ParserMatchClass. If it does,
// use it, else just fall back to the underlying register class.
@@ -1177,7 +1187,7 @@ AsmMatcherInfo::getOperandClass(Record *Rec, int SubOpIdx) {
"Record `" + Rec->getName() +
"' does not have a ParserMatchClass!\n");
- if (DefInit *DI= dyn_cast<DefInit>(R->getValue())) {
+ if (DefInit *DI = dyn_cast<DefInit>(R->getValue())) {
Record *MatchClass = DI->getDef();
if (ClassInfo *CI = AsmOperandClasses[MatchClass])
return CI;
@@ -1186,8 +1196,9 @@ AsmMatcherInfo::getOperandClass(Record *Rec, int SubOpIdx) {
// No custom match class. Just use the register class.
Record *ClassRec = Rec->getValueAsDef("RegClass");
if (!ClassRec)
- PrintFatalError(Rec->getLoc(), "RegisterOperand `" + Rec->getName() +
- "' has no associated register class!\n");
+ PrintFatalError(Rec->getLoc(),
+ "RegisterOperand `" + Rec->getName() +
+ "' has no associated register class!\n");
if (ClassInfo *CI = RegisterClassClasses[ClassRec])
return CI;
PrintFatalError(Rec->getLoc(), "register class has no class info!");
@@ -1200,8 +1211,9 @@ AsmMatcherInfo::getOperandClass(Record *Rec, int SubOpIdx) {
}
if (!Rec->isSubClassOf("Operand"))
- PrintFatalError(Rec->getLoc(), "Operand `" + Rec->getName() +
- "' does not derive from class Operand!\n");
+ PrintFatalError(Rec->getLoc(),
+ "Operand `" + Rec->getName() +
+ "' does not derive from class Operand!\n");
Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
if (ClassInfo *CI = AsmOperandClasses[MatchClass])
return CI;
@@ -1210,19 +1222,18 @@ AsmMatcherInfo::getOperandClass(Record *Rec, int SubOpIdx) {
}
struct LessRegisterSet {
- bool operator() (const RegisterSet &LHS, const RegisterSet & RHS) const {
+ bool operator()(const RegisterSet &LHS, const RegisterSet &RHS) const {
// std::set<T> defines its own compariso "operator<", but it
// performs a lexicographical comparison by T's innate comparison
// for some reason. We don't want non-deterministic pointer
// comparisons so use this instead.
- return std::lexicographical_compare(LHS.begin(), LHS.end(),
- RHS.begin(), RHS.end(),
- LessRecordByID());
+ return std::lexicographical_compare(LHS.begin(), LHS.end(), RHS.begin(),
+ RHS.end(), LessRecordByID());
}
};
-void AsmMatcherInfo::
-buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters) {
+void AsmMatcherInfo::buildRegisterClasses(
+ SmallPtrSetImpl<Record *> &SingletonRegisters) {
const auto &Registers = Target.getRegBank().getRegisters();
auto &RegClassList = Target.getRegBank().getRegClasses();
@@ -1244,7 +1255,7 @@ buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters) {
// Introduce derived sets where necessary (when a register does not determine
// a unique register set class), and build the mapping of registers to the set
// they should classify to.
- std::map<Record*, RegisterSet> RegisterMap;
+ std::map<Record *, RegisterSet> RegisterMap;
for (const CodeGenRegister &CGR : Registers) {
// Compute the intersection of all sets containing this register.
RegisterSet ContainingSet;
@@ -1273,7 +1284,7 @@ buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters) {
}
// Construct the register classes.
- std::map<RegisterSet, ClassInfo*, LessRegisterSet> RegisterSetClasses;
+ std::map<RegisterSet, ClassInfo *, LessRegisterSet> RegisterSetClasses;
unsigned Index = 0;
for (const RegisterSet &RS : RegisterSets) {
Classes.emplace_front();
@@ -1298,9 +1309,8 @@ buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters) {
for (const RegisterSet &RS : RegisterSets) {
ClassInfo *CI = RegisterSetClasses[RS];
for (const RegisterSet &RS2 : RegisterSets)
- if (RS != RS2 &&
- std::includes(RS2.begin(), RS2.end(), RS.begin(), RS.end(),
- LessRecordByID()))
+ if (RS != RS2 && std::includes(RS2.begin(), RS2.end(), RS.begin(),
+ RS.end(), LessRecord...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/80973
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