[llvm] [AArch64][GloablISel] Refactor Combine G_CONCAT_VECTOR (PR #80866)

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``````````bash
git-clang-format --diff 1b87ebce924e507cbc27c2e0dc623941d16388c9 54ec87dddded77ec376b1e8fbd7bd9a8d0565ca4 -- llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
index 6445fc2ee6..6a805ee40a 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
@@ -232,14 +232,10 @@ public:
   /// needed to produce the flattened build_vector.
   ///
   /// \pre MI.getOpcode() == G_CONCAT_VECTORS.
-  bool
-  matchCombineConcatVectors(MachineInstr &MI,
-                            SmallVector<Register> &Ops);
+  bool matchCombineConcatVectors(MachineInstr &MI, SmallVector<Register> &Ops);
   /// Replace \p MI with a flattened build_vector with \p Ops
   /// or an implicit_def if \p Ops is empty.
-  void
-  applyCombineConcatVectors(MachineInstr &MI,
-                            SmallVector<Register> &Ops);
+  void applyCombineConcatVectors(MachineInstr &MI, SmallVector<Register> &Ops);
 
   /// Try to combine G_SHUFFLE_VECTOR into G_CONCAT_VECTORS.
   /// Returns true if MI changed.
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index 3120a766c4..b400eb34e2 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -222,8 +222,8 @@ void CombinerHelper::applyCombineCopy(MachineInstr &MI) {
   replaceRegWith(MRI, DstReg, SrcReg);
 }
 
-bool CombinerHelper::matchCombineConcatVectors(
-    MachineInstr &MI, SmallVector<Register> &Ops) {
+bool CombinerHelper::matchCombineConcatVectors(MachineInstr &MI,
+                                               SmallVector<Register> &Ops) {
   assert(MI.getOpcode() == TargetOpcode::G_CONCAT_VECTORS &&
          "Invalid instruction");
   bool IsUndef = true;
@@ -270,8 +270,8 @@ bool CombinerHelper::matchCombineConcatVectors(
 
   // Check if the combine is illegal
   LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
-  if (!isLegalOrBeforeLegalizer({TargetOpcode::G_BUILD_VECTOR,
-                                 {DstTy, MRI.getType(Ops[0])}})) {
+  if (!isLegalOrBeforeLegalizer(
+          {TargetOpcode::G_BUILD_VECTOR, {DstTy, MRI.getType(Ops[0])}})) {
     return false;
   }
 
@@ -280,8 +280,8 @@ bool CombinerHelper::matchCombineConcatVectors(
 
   return true;
 }
-void CombinerHelper::applyCombineConcatVectors(
-    MachineInstr &MI, SmallVector<Register> &Ops) {
+void CombinerHelper::applyCombineConcatVectors(MachineInstr &MI,
+                                               SmallVector<Register> &Ops) {
   // We determined that the concat_vectors can be flatten.
   // Generate the flattened build_vector.
   Register DstReg = MI.getOperand(0).getReg();

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https://github.com/llvm/llvm-project/pull/80866