[llvm] [RISCV] Combine build_vector of extract_vector_elts to vector_shuffle (PR #80883)

[Luke Lau via llvm-commits]

lukel97 wrote:

> Did you explore the impact of adjusting SDAG construction to pad the mask with undefs in this case? That would seem like a more reasonable canonical form that then explode and build. We could maybe have it behind a hook to preserve existing target behavior if needed.

I checked and the blast radius is quite large on other targets as we might expect. But even on RISC-V this breaks another lowering pattern for deinterleave shuffles, where we are relying on the build_vector -> vector_shuffle transform to emit shuffles of the form:

vector_shuffle (extract_subvector v, 0), (extract_subvector v, 4), <0, 2, 4, 6>

The same shuffle if we build it directly in SelectionDAGBuilder is

extract_subvector (vector_shuffle v, undef, <0, 2, 4, 6, u, u, u, u>), 0

We could try and add another combine for this or teach our deinterleave shuffle lowering to recognize this specific case, but that seems like more code.

https://github.com/llvm/llvm-project/pull/80883