[llvm] [ARM] Resolve FIXME: Swap adds <-> subs offset is 0 (PR #78870)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 6 22:28:31 PST 2024
https://github.com/AtariDreams updated https://github.com/llvm/llvm-project/pull/78870
>From 83ac36ef9e9998a73d727e543f94ff31f5f20b47 Mon Sep 17 00:00:00 2001
From: Rose <83477269+AtariDreams at users.noreply.github.com>
Date: Sat, 20 Jan 2024 19:13:27 -0500
Subject: [PATCH] [ARM] Resolve FIXME: Swap adds <-> subs offset is 0
Also erase instruction if offset is 0
---
llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 22 +++++++++++++------
1 file changed, 15 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index ed9d30c3c3ab9..fb7c8be0ccef8 100644
--- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -525,13 +525,21 @@ void ARMLoadStoreOpt::UpdateBaseRegUses(MachineBasicBlock &MBB,
// Merge it with the update; if the merged offset is too large,
// insert a new sub instead.
MachineOperand &MO =
- MBBI->getOperand(MBBI->getDesc().getNumOperands() - 3);
- Offset = (Opc == ARM::tSUBi8) ?
- MO.getImm() + WordOffset * 4 :
- MO.getImm() - WordOffset * 4 ;
- if (Offset >= 0 && TL->isLegalAddImmediate(Offset)) {
- // FIXME: Swap ADDS<->SUBS if Offset < 0, erase instruction if
- // Offset == 0.
+ MBBI->getOperand(MBBI->getDesc().getNumOperands() - 3);
+ Offset = (Opc == ARM::tSUBi8) ? MO.getImm() + WordOffset * 4
+ : MO.getImm() - WordOffset * 4;
+ if (TL->isLegalAddImmediate(Offset)) {
+ if (Offset < 0) {
+ // Swap ADDS<->SUBS if Offset < 0
+ Opc = (Opc == ARM::tSUBi8) ? ARM::tADDi8 : ARM::tSUBi8;
+ Offset = -Offset;
+ } else if (Offset == 0) {
+ // Erase instruction if Offset == 0
+ LLVM_DEBUG(dbgs() << " Erasing instruction due to offset being 0: "
+ << *MBBI);
+ MBB.erase(MBBI);
+ return;
+ }
MO.setImm(Offset);
// The base register has now been reset, so exit early.
return;
More information about the llvm-commits
mailing list