[llvm] [AMDGPU]: Accept constant zero bytes in v_perm OrCombine (PR #66533)

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github-actions[bot] wrote:

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``````````bash
git-clang-format --diff bcd1490496a5bf06ce98470ef622db29a8eebbf7 c8037640d248751d1ff22e7ff86113325fafd14b -- llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 772e73465a..cac76838db 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -11625,8 +11625,7 @@ calculateSrcByte(const SDValue Op, uint64_t DestByte, uint64_t SrcIndex = 0,
         return std::nullopt;
 
       SrcIndex = VecIdx * ScalarSize / 8 + SrcIndex;
-      return calculateSrcByte(Op->getOperand(0), DestByte, SrcIndex,
-                              Depth + 1);
+      return calculateSrcByte(Op->getOperand(0), DestByte, SrcIndex, Depth + 1);
     }
 
     // The scalar is 32 bits, so just use the scalar
@@ -12032,7 +12031,6 @@ static SDValue matchPERM(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
       (N->getOperand(1) == Op || N->getOperand(1) == OtherOp))
     return SDValue();
 
-
   // Check that we are not just extracting the bytes in order from an op
   if (Op == OtherOp && Op.getValueSizeInBits() == 32) {
     int Low16 = PermMask & 0xffff;

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https://github.com/llvm/llvm-project/pull/66533