[llvm] [clang] [SPARC] Support reserving arbitrary general purpose registers (PR #74927)

[Sergei Barannikov via llvm-commits]

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@@ -82,6 +88,13 @@ class SparcSubtarget : public SparcGenSubtargetInfo {
     return is64Bit() ? 2047 : 0;
   }
 
+  bool isRegisterReserved(MCPhysReg PhysReg) const {
+    if (PhysReg >= SP::G0 && PhysReg <= SP::O7)
+      return ReserveRegister[PhysReg - SP::G0];
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s-barannikov wrote:

I wouldn't bother "compacting" a BitVector. This would also allow reserving other registers in the future and not depend on exact values of enum members.

https://github.com/llvm/llvm-project/pull/74927