[llvm] [RFC][TableGen] Restructure TableGen Source (PR #80847)
Pierre van Houtryve via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 6 07:21:47 PST 2024
https://github.com/Pierre-vh created https://github.com/llvm/llvm-project/pull/80847
Lately, while trying to move as much code out of the GlobalISel Combiner Backend, I've been hitting more and more linker issues. I've had to revert one of my recent patches because a buildbot just wouldn't let it slide due to weirdness in how the dependencies were declared. It seems like the library structure was due for an overhaul, so I created #80647
I'm proposing this refactor of the llvm-tblgen source into:
- a "Basic" library, which contains the bare minimum utilities to build `llvm-min-tablegen`
- a "Common" library which contains all of the helpers for TableGen backends. Such helpers can be shared by more than one backend, and even unit tested (e.g. CodeExpander is, maybe we can add more over time)
The backends remain in place and just make use of the new include paths.
I did a directory structure that I hope makes sense, but it's completely fine if it's not what we want and it needs to be redone. We can take our time reviewing this to make sure we won't need to re-do the library structure again anytime soon. This is why I'm tagging this as a RFC.
Fixes #80647
>From 13b4604c7530157d2065199075c7021f65952f7a Mon Sep 17 00:00:00 2001
From: pvanhout <pierre.vanhoutryve at amd.com>
Date: Tue, 6 Feb 2024 16:17:43 +0100
Subject: [PATCH] [RFC][TableGen] Restructure TableGen Source
Lately, while trying to move as much code out of the GlobalISel Combiner Backend, I've been hitting more and more linker issues. It seems like the
library structure was due for an overhaul, so I created #80647
I'm proposing this refactor of the llvm-tblgen source into:
- a "Basic" library, which contains the bare minimum utilities to build `llvm-min-tablegen`
- a "Common" library which contains all of the helpers for TableGen backends. Such helpers can be shared by more than one backend, and even unit tested (e.g. CodeExpander is, maybe we can add more over time)
The backends remain in place and just make use of the new include paths.
Solves #80647
---
llvm/unittests/TableGen/CMakeLists.txt | 2 +-
llvm/unittests/TableGen/CodeExpanderTest.cpp | 4 +-
llvm/utils/TableGen/AsmMatcherEmitter.cpp | 12 +-
llvm/utils/TableGen/AsmWriterEmitter.cpp | 18 +-
llvm/utils/TableGen/AsmWriterInst.h | 107 ---
llvm/utils/TableGen/Basic/CMakeLists.txt | 21 +
.../{ => Basic}/CodeGenIntrinsics.cpp | 0
.../TableGen/{ => Basic}/CodeGenIntrinsics.h | 16 +-
.../TableGen/{ => Basic}/SDNodeProperties.cpp | 0
.../TableGen/{ => Basic}/SDNodeProperties.h | 2 +-
.../{ => Basic}/SequenceToOffsetTable.h | 12 +-
llvm/utils/TableGen/CMakeLists.txt | 67 +-
llvm/utils/TableGen/CallingConvEmitter.cpp | 8 +-
llvm/utils/TableGen/CodeEmitterGen.cpp | 16 +-
llvm/utils/TableGen/CodeGenHwModes.h | 67 --
llvm/utils/TableGen/CodeGenInstruction.h | 343 -------
llvm/utils/TableGen/CodeGenMapTable.cpp | 4 +-
llvm/utils/TableGen/CodeGenRegisters.h | 854 ------------------
.../TableGen/{ => Common}/AsmWriterInst.cpp | 69 +-
llvm/utils/TableGen/Common/AsmWriterInst.h | 107 +++
llvm/utils/TableGen/Common/CMakeLists.txt | 48 +
.../{ => Common}/CodeGenDAGPatterns.cpp | 579 ++++++------
.../{ => Common}/CodeGenDAGPatterns.h | 213 ++---
.../TableGen/{ => Common}/CodeGenHwModes.cpp | 16 +-
llvm/utils/TableGen/Common/CodeGenHwModes.h | 67 ++
.../{ => Common}/CodeGenInstAlias.cpp | 0
.../TableGen/{ => Common}/CodeGenInstAlias.h | 0
.../{ => Common}/CodeGenInstruction.cpp | 147 ++-
.../TableGen/Common/CodeGenInstruction.h | 339 +++++++
.../{ => Common}/CodeGenRegisters.cpp | 286 +++---
llvm/utils/TableGen/Common/CodeGenRegisters.h | 842 +++++++++++++++++
.../TableGen/{ => Common}/CodeGenSchedule.cpp | 338 ++++---
.../TableGen/{ => Common}/CodeGenSchedule.h | 49 +-
.../TableGen/{ => Common}/CodeGenTarget.cpp | 62 +-
.../TableGen/{ => Common}/CodeGenTarget.h | 40 +-
.../TableGen/{ => Common}/DAGISelMatcher.cpp | 74 +-
.../TableGen/{ => Common}/DAGISelMatcher.h | 518 +++++------
.../{ => Common}/GlobalISel/CXXPredicates.cpp | 0
.../{ => Common}/GlobalISel/CXXPredicates.h | 0
.../{ => Common}/GlobalISel/CodeExpander.cpp | 0
.../{ => Common}/GlobalISel/CodeExpander.h | 0
.../{ => Common}/GlobalISel/CodeExpansions.h | 0
.../{ => Common}/GlobalISel/CombinerUtils.h | 0
.../GlobalISel}/GlobalISelMatchTable.cpp | 4 +-
.../GlobalISel}/GlobalISelMatchTable.h | 2 +-
.../GlobalISelMatchTableExecutorEmitter.cpp | 0
.../GlobalISelMatchTableExecutorEmitter.h | 2 +-
.../{ => Common}/GlobalISel/MatchDataInfo.cpp | 0
.../{ => Common}/GlobalISel/MatchDataInfo.h | 0
.../{ => Common}/GlobalISel/Patterns.cpp | 4 +-
.../{ => Common}/GlobalISel/Patterns.h | 0
.../TableGen/{ => Common}/InfoByHwMode.cpp | 63 +-
.../TableGen/{ => Common}/InfoByHwMode.h | 41 +-
.../TableGen/{ => Common}/OptEmitter.cpp | 0
llvm/utils/TableGen/{ => Common}/OptEmitter.h | 0
.../{ => Common}/PredicateExpander.cpp | 4 +-
.../TableGen/{ => Common}/PredicateExpander.h | 0
.../{ => Common}/SubtargetFeatureInfo.cpp | 2 +-
.../{ => Common}/SubtargetFeatureInfo.h | 3 +-
llvm/utils/TableGen/{ => Common}/Types.cpp | 4 +-
llvm/utils/TableGen/{ => Common}/Types.h | 2 +-
.../{ => Common}/VarLenCodeEmitterGen.cpp | 0
.../{ => Common}/VarLenCodeEmitterGen.h | 0
llvm/utils/TableGen/CompressInstEmitter.cpp | 6 +-
llvm/utils/TableGen/DAGISelEmitter.cpp | 8 +-
llvm/utils/TableGen/DAGISelMatcherEmitter.cpp | 12 +-
llvm/utils/TableGen/DAGISelMatcherGen.cpp | 14 +-
llvm/utils/TableGen/DAGISelMatcherOpt.cpp | 6 +-
llvm/utils/TableGen/DFAEmitter.cpp | 2 +-
llvm/utils/TableGen/DFAPacketizerEmitter.cpp | 4 +-
llvm/utils/TableGen/DXILEmitter.cpp | 2 +-
llvm/utils/TableGen/DecoderEmitter.cpp | 10 +-
llvm/utils/TableGen/DisassemblerEmitter.cpp | 2 +-
llvm/utils/TableGen/FastISelEmitter.cpp | 10 +-
llvm/utils/TableGen/GlobalISel/CMakeLists.txt | 20 -
.../TableGen/GlobalISelCombinerEmitter.cpp | 24 +-
llvm/utils/TableGen/GlobalISelEmitter.cpp | 18 +-
llvm/utils/TableGen/InstrDocsEmitter.cpp | 6 +-
llvm/utils/TableGen/InstrInfoEmitter.cpp | 16 +-
llvm/utils/TableGen/IntrinsicEmitter.cpp | 4 +-
.../TableGen/MacroFusionPredicatorEmitter.cpp | 4 +-
llvm/utils/TableGen/OptParserEmitter.cpp | 2 +-
llvm/utils/TableGen/OptRSTEmitter.cpp | 2 +-
llvm/utils/TableGen/PseudoLoweringEmitter.cpp | 4 +-
llvm/utils/TableGen/RegisterBankEmitter.cpp | 6 +-
llvm/utils/TableGen/RegisterInfoEmitter.cpp | 12 +-
.../utils/TableGen/SearchableTableEmitter.cpp | 38 +-
llvm/utils/TableGen/SubtargetEmitter.cpp | 8 +-
.../WebAssemblyDisassemblerEmitter.cpp | 2 +-
.../TableGen/X86CompressEVEXTablesEmitter.cpp | 4 +-
llvm/utils/TableGen/X86FoldTablesEmitter.cpp | 4 +-
llvm/utils/TableGen/X86MnemonicTables.cpp | 4 +-
llvm/utils/TableGen/X86RecognizableInstr.h | 2 +-
93 files changed, 2846 insertions(+), 2888 deletions(-)
delete mode 100644 llvm/utils/TableGen/AsmWriterInst.h
create mode 100644 llvm/utils/TableGen/Basic/CMakeLists.txt
rename llvm/utils/TableGen/{ => Basic}/CodeGenIntrinsics.cpp (100%)
rename llvm/utils/TableGen/{ => Basic}/CodeGenIntrinsics.h (91%)
rename llvm/utils/TableGen/{ => Basic}/SDNodeProperties.cpp (100%)
rename llvm/utils/TableGen/{ => Basic}/SDNodeProperties.h (98%)
rename llvm/utils/TableGen/{ => Basic}/SequenceToOffsetTable.h (93%)
delete mode 100644 llvm/utils/TableGen/CodeGenHwModes.h
delete mode 100644 llvm/utils/TableGen/CodeGenInstruction.h
delete mode 100644 llvm/utils/TableGen/CodeGenRegisters.h
rename llvm/utils/TableGen/{ => Common}/AsmWriterInst.cpp (83%)
create mode 100644 llvm/utils/TableGen/Common/AsmWriterInst.h
create mode 100644 llvm/utils/TableGen/Common/CMakeLists.txt
rename llvm/utils/TableGen/{ => Common}/CodeGenDAGPatterns.cpp (92%)
rename llvm/utils/TableGen/{ => Common}/CodeGenDAGPatterns.h (89%)
rename llvm/utils/TableGen/{ => Common}/CodeGenHwModes.cpp (89%)
create mode 100644 llvm/utils/TableGen/Common/CodeGenHwModes.h
rename llvm/utils/TableGen/{ => Common}/CodeGenInstAlias.cpp (100%)
rename llvm/utils/TableGen/{ => Common}/CodeGenInstAlias.h (100%)
rename llvm/utils/TableGen/{ => Common}/CodeGenInstruction.cpp (83%)
create mode 100644 llvm/utils/TableGen/Common/CodeGenInstruction.h
rename llvm/utils/TableGen/{ => Common}/CodeGenRegisters.cpp (92%)
create mode 100644 llvm/utils/TableGen/Common/CodeGenRegisters.h
rename llvm/utils/TableGen/{ => Common}/CodeGenSchedule.cpp (90%)
rename llvm/utils/TableGen/{ => Common}/CodeGenSchedule.h (93%)
rename llvm/utils/TableGen/{ => Common}/CodeGenTarget.cpp (94%)
rename llvm/utils/TableGen/{ => Common}/CodeGenTarget.h (90%)
rename llvm/utils/TableGen/{ => Common}/DAGISelMatcher.cpp (89%)
rename llvm/utils/TableGen/{ => Common}/DAGISelMatcher.h (74%)
rename llvm/utils/TableGen/{ => Common}/GlobalISel/CXXPredicates.cpp (100%)
rename llvm/utils/TableGen/{ => Common}/GlobalISel/CXXPredicates.h (100%)
rename llvm/utils/TableGen/{ => Common}/GlobalISel/CodeExpander.cpp (100%)
rename llvm/utils/TableGen/{ => Common}/GlobalISel/CodeExpander.h (100%)
rename llvm/utils/TableGen/{ => Common}/GlobalISel/CodeExpansions.h (100%)
rename llvm/utils/TableGen/{ => Common}/GlobalISel/CombinerUtils.h (100%)
rename llvm/utils/TableGen/{ => Common/GlobalISel}/GlobalISelMatchTable.cpp (99%)
rename llvm/utils/TableGen/{ => Common/GlobalISel}/GlobalISelMatchTable.h (99%)
rename llvm/utils/TableGen/{ => Common/GlobalISel}/GlobalISelMatchTableExecutorEmitter.cpp (100%)
rename llvm/utils/TableGen/{ => Common/GlobalISel}/GlobalISelMatchTableExecutorEmitter.h (99%)
rename llvm/utils/TableGen/{ => Common}/GlobalISel/MatchDataInfo.cpp (100%)
rename llvm/utils/TableGen/{ => Common}/GlobalISel/MatchDataInfo.h (100%)
rename llvm/utils/TableGen/{ => Common}/GlobalISel/Patterns.cpp (99%)
rename llvm/utils/TableGen/{ => Common}/GlobalISel/Patterns.h (100%)
rename llvm/utils/TableGen/{ => Common}/InfoByHwMode.cpp (80%)
rename llvm/utils/TableGen/{ => Common}/InfoByHwMode.h (84%)
rename llvm/utils/TableGen/{ => Common}/OptEmitter.cpp (100%)
rename llvm/utils/TableGen/{ => Common}/OptEmitter.h (100%)
rename llvm/utils/TableGen/{ => Common}/PredicateExpander.cpp (99%)
rename llvm/utils/TableGen/{ => Common}/PredicateExpander.h (100%)
rename llvm/utils/TableGen/{ => Common}/SubtargetFeatureInfo.cpp (99%)
rename llvm/utils/TableGen/{ => Common}/SubtargetFeatureInfo.h (97%)
rename llvm/utils/TableGen/{ => Common}/Types.cpp (90%)
rename llvm/utils/TableGen/{ => Common}/Types.h (97%)
rename llvm/utils/TableGen/{ => Common}/VarLenCodeEmitterGen.cpp (100%)
rename llvm/utils/TableGen/{ => Common}/VarLenCodeEmitterGen.h (100%)
delete mode 100644 llvm/utils/TableGen/GlobalISel/CMakeLists.txt
diff --git a/llvm/unittests/TableGen/CMakeLists.txt b/llvm/unittests/TableGen/CMakeLists.txt
index 7830e021804589..fae0eee06e4b0c 100644
--- a/llvm/unittests/TableGen/CMakeLists.txt
+++ b/llvm/unittests/TableGen/CMakeLists.txt
@@ -15,4 +15,4 @@ add_llvm_unittest(TableGenTests DISABLE_LLVM_LINK_LLVM_DYLIB
ParserEntryPointTest.cpp
)
-target_link_libraries(TableGenTests PRIVATE LLVMTableGenGlobalISel LLVMTableGen)
+target_link_libraries(TableGenTests PRIVATE LLVMTableGenCommon LLVMTableGen)
diff --git a/llvm/unittests/TableGen/CodeExpanderTest.cpp b/llvm/unittests/TableGen/CodeExpanderTest.cpp
index 4a9a0e8c114bc0..1528884ffdf65b 100644
--- a/llvm/unittests/TableGen/CodeExpanderTest.cpp
+++ b/llvm/unittests/TableGen/CodeExpanderTest.cpp
@@ -6,8 +6,8 @@
//
//===----------------------------------------------------------------------===//
-#include "GlobalISel/CodeExpander.h"
-#include "GlobalISel/CodeExpansions.h"
+#include "Common/GlobalISel/CodeExpander.h"
+#include "Common/GlobalISel/CodeExpansions.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/TableGen/Error.h"
diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
index 011d96a48d61da..13e8a8a62fa572 100644
--- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
@@ -95,12 +95,12 @@
//
//===----------------------------------------------------------------------===//
-#include "CodeGenInstAlias.h"
-#include "CodeGenInstruction.h"
-#include "CodeGenRegisters.h"
-#include "CodeGenTarget.h"
-#include "SubtargetFeatureInfo.h"
-#include "Types.h"
+#include "Common/CodeGenInstAlias.h"
+#include "Common/CodeGenInstruction.h"
+#include "Common/CodeGenRegisters.h"
+#include "Common/CodeGenTarget.h"
+#include "Common/SubtargetFeatureInfo.h"
+#include "Common/Types.h"
#include "llvm/ADT/CachedHashString.h"
#include "llvm/ADT/PointerUnion.h"
#include "llvm/ADT/STLExtras.h"
diff --git a/llvm/utils/TableGen/AsmWriterEmitter.cpp b/llvm/utils/TableGen/AsmWriterEmitter.cpp
index e0cd5fad3254de..9a7956d9124a33 100644
--- a/llvm/utils/TableGen/AsmWriterEmitter.cpp
+++ b/llvm/utils/TableGen/AsmWriterEmitter.cpp
@@ -11,13 +11,13 @@
//
//===----------------------------------------------------------------------===//
-#include "AsmWriterInst.h"
-#include "CodeGenInstAlias.h"
-#include "CodeGenInstruction.h"
-#include "CodeGenRegisters.h"
-#include "CodeGenTarget.h"
-#include "SequenceToOffsetTable.h"
-#include "Types.h"
+#include "Basic/SequenceToOffsetTable.h"
+#include "Common/AsmWriterInst.h"
+#include "Common/CodeGenInstAlias.h"
+#include "Common/CodeGenInstruction.h"
+#include "Common/CodeGenRegisters.h"
+#include "Common/CodeGenTarget.h"
+#include "Common/Types.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/STLExtras.h"
@@ -1262,14 +1262,14 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
<< " break;\n";
}
O << " }\n";
- }
+ }
O << "}\n\n";
if (!MCOpPredicates.empty()) {
O << "static bool " << Target.getName() << ClassName
<< "ValidateMCOperand(const MCOperand &MCOp,\n"
<< " const MCSubtargetInfo &STI,\n"
- << " unsigned PredicateIndex) {\n"
+ << " unsigned PredicateIndex) {\n"
<< " switch (PredicateIndex) {\n"
<< " default:\n"
<< " llvm_unreachable(\"Unknown MCOperandPredicate kind\");\n"
diff --git a/llvm/utils/TableGen/AsmWriterInst.h b/llvm/utils/TableGen/AsmWriterInst.h
deleted file mode 100644
index 9c93e82b611b6b..00000000000000
--- a/llvm/utils/TableGen/AsmWriterInst.h
+++ /dev/null
@@ -1,107 +0,0 @@
-//===- AsmWriterInst.h - Classes encapsulating a printable inst -*- C++ -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// These classes implement a parser for assembly strings. The parser splits
-// the string into operands, which can be literal strings (the constant bits of
-// the string), actual operands (i.e., operands from the MachineInstr), and
-// dynamically-generated text, specified by raw C++ code.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_UTILS_TABLEGEN_ASMWRITERINST_H
-#define LLVM_UTILS_TABLEGEN_ASMWRITERINST_H
-
-#include <string>
-#include <vector>
-
-namespace llvm {
- class CodeGenInstruction;
-
- struct AsmWriterOperand {
- enum OpType {
- // Output this text surrounded by quotes to the asm.
- isLiteralTextOperand,
- // This is the name of a routine to call to print the operand.
- isMachineInstrOperand,
- // Output this text verbatim to the asm writer. It is code that
- // will output some text to the asm.
- isLiteralStatementOperand
- } OperandType;
-
- /// MiOpNo - For isMachineInstrOperand, this is the operand number of the
- /// machine instruction.
- unsigned MIOpNo = 0;
-
- /// Str - For isLiteralTextOperand, this IS the literal text. For
- /// isMachineInstrOperand, this is the PrinterMethodName for the operand..
- /// For isLiteralStatementOperand, this is the code to insert verbatim
- /// into the asm writer.
- std::string Str;
-
- /// MiModifier - For isMachineInstrOperand, this is the modifier string for
- /// an operand, specified with syntax like ${opname:modifier}.
- std::string MiModifier;
-
- bool PCRel = false;
-
- // To make VS STL happy
- AsmWriterOperand(OpType op = isLiteralTextOperand):OperandType(op) {}
-
- AsmWriterOperand(const std::string &LitStr,
- OpType op = isLiteralTextOperand)
- : OperandType(op), Str(LitStr) {}
-
- AsmWriterOperand(const std::string &Printer, unsigned _MIOpNo,
- const std::string &Modifier,
- OpType op = isMachineInstrOperand, bool PCRel = false)
- : OperandType(op), MIOpNo(_MIOpNo), Str(Printer), MiModifier(Modifier),
- PCRel(PCRel) {}
-
- bool operator!=(const AsmWriterOperand &Other) const {
- if (OperandType != Other.OperandType || Str != Other.Str) return true;
- if (OperandType == isMachineInstrOperand)
- return MIOpNo != Other.MIOpNo || MiModifier != Other.MiModifier ||
- PCRel != Other.PCRel;
- return false;
- }
- bool operator==(const AsmWriterOperand &Other) const {
- return !operator!=(Other);
- }
-
- /// getCode - Return the code that prints this operand.
- std::string getCode(bool PassSubtarget) const;
- };
-
- class AsmWriterInst {
- public:
- std::vector<AsmWriterOperand> Operands;
- const CodeGenInstruction *CGI;
- unsigned CGIIndex;
-
- AsmWriterInst(const CodeGenInstruction &CGI, unsigned CGIIndex,
- unsigned Variant);
-
- /// MatchesAllButOneOp - If this instruction is exactly identical to the
- /// specified instruction except for one differing operand, return the
- /// differing operand number. Otherwise return ~0.
- unsigned MatchesAllButOneOp(const AsmWriterInst &Other) const;
-
- private:
- void AddLiteralString(const std::string &Str) {
- // If the last operand was already a literal text string, append this to
- // it, otherwise add a new operand.
- if (!Operands.empty() &&
- Operands.back().OperandType == AsmWriterOperand::isLiteralTextOperand)
- Operands.back().Str.append(Str);
- else
- Operands.push_back(AsmWriterOperand(Str));
- }
- };
-}
-
-#endif
diff --git a/llvm/utils/TableGen/Basic/CMakeLists.txt b/llvm/utils/TableGen/Basic/CMakeLists.txt
new file mode 100644
index 00000000000000..f2927d05c175c3
--- /dev/null
+++ b/llvm/utils/TableGen/Basic/CMakeLists.txt
@@ -0,0 +1,21 @@
+# The basic TableGen library contains as little dependencies as possible.
+# In particular, it does not depend on vt_gen -> it does not use ValueTypes.
+#
+# This library is the only thing included in `llvm-min-tablegen`.
+
+set(LLVM_LINK_COMPONENTS
+ Support
+ TableGen
+ )
+
+add_llvm_library(LLVMTableGenBasic STATIC OBJECT EXCLUDE_FROM_ALL
+ CodeGenIntrinsics.cpp
+ SDNodeProperties.cpp
+)
+set_target_properties(LLVMTableGenBasic PROPERTIES FOLDER "Tablegenning")
+
+# Users may include its headers as "Basic/*.h"
+target_include_directories(LLVMTableGenBasic
+ INTERFACE
+ $<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/..>
+ )
diff --git a/llvm/utils/TableGen/CodeGenIntrinsics.cpp b/llvm/utils/TableGen/Basic/CodeGenIntrinsics.cpp
similarity index 100%
rename from llvm/utils/TableGen/CodeGenIntrinsics.cpp
rename to llvm/utils/TableGen/Basic/CodeGenIntrinsics.cpp
diff --git a/llvm/utils/TableGen/CodeGenIntrinsics.h b/llvm/utils/TableGen/Basic/CodeGenIntrinsics.h
similarity index 91%
rename from llvm/utils/TableGen/CodeGenIntrinsics.h
rename to llvm/utils/TableGen/Basic/CodeGenIntrinsics.h
index f3452f5acea804..da9e386d64d18b 100644
--- a/llvm/utils/TableGen/CodeGenIntrinsics.h
+++ b/llvm/utils/TableGen/Basic/CodeGenIntrinsics.h
@@ -25,12 +25,12 @@ class Record;
class RecordKeeper;
struct CodeGenIntrinsic {
- Record *TheDef; // The actual record defining this intrinsic.
- std::string Name; // The name of the LLVM function "llvm.bswap.i32"
- std::string EnumName; // The name of the enum "bswap_i32"
+ Record *TheDef; // The actual record defining this intrinsic.
+ std::string Name; // The name of the LLVM function "llvm.bswap.i32"
+ std::string EnumName; // The name of the enum "bswap_i32"
std::string ClangBuiltinName; // Name of the corresponding GCC builtin, or "".
- std::string MSBuiltinName; // Name of the corresponding MS builtin, or "".
- std::string TargetPrefix; // Target prefix, e.g. "ppc" for t-s intrinsics.
+ std::string MSBuiltinName; // Name of the corresponding MS builtin, or "".
+ std::string TargetPrefix; // Target prefix, e.g. "ppc" for t-s intrinsics.
/// This structure holds the return values and parameter values of an
/// intrinsic. If the number of return values is > 1, then the intrinsic
@@ -136,9 +136,7 @@ struct CodeGenIntrinsic {
void addArgAttribute(unsigned Idx, ArgAttrKind AK, uint64_t V = 0);
- bool hasProperty(enum SDNP Prop) const {
- return Properties & (1 << Prop);
- }
+ bool hasProperty(enum SDNP Prop) const { return Properties & (1 << Prop); }
/// Goes through all IntrProperties that have IsDefault
/// value set and sets the property.
@@ -182,6 +180,6 @@ class CodeGenIntrinsicTable {
return Intrinsics[Pos];
}
};
-}
+} // namespace llvm
#endif
diff --git a/llvm/utils/TableGen/SDNodeProperties.cpp b/llvm/utils/TableGen/Basic/SDNodeProperties.cpp
similarity index 100%
rename from llvm/utils/TableGen/SDNodeProperties.cpp
rename to llvm/utils/TableGen/Basic/SDNodeProperties.cpp
diff --git a/llvm/utils/TableGen/SDNodeProperties.h b/llvm/utils/TableGen/Basic/SDNodeProperties.h
similarity index 98%
rename from llvm/utils/TableGen/SDNodeProperties.h
rename to llvm/utils/TableGen/Basic/SDNodeProperties.h
index 66a04e63150c40..5715423285249f 100644
--- a/llvm/utils/TableGen/SDNodeProperties.h
+++ b/llvm/utils/TableGen/Basic/SDNodeProperties.h
@@ -34,6 +34,6 @@ enum SDNP {
unsigned parseSDPatternOperatorProperties(Record *R);
-}
+} // namespace llvm
#endif
diff --git a/llvm/utils/TableGen/SequenceToOffsetTable.h b/llvm/utils/TableGen/Basic/SequenceToOffsetTable.h
similarity index 93%
rename from llvm/utils/TableGen/SequenceToOffsetTable.h
rename to llvm/utils/TableGen/Basic/SequenceToOffsetTable.h
index 77a404d07b7d39..7db39a9af72092 100644
--- a/llvm/utils/TableGen/SequenceToOffsetTable.h
+++ b/llvm/utils/TableGen/Basic/SequenceToOffsetTable.h
@@ -44,7 +44,7 @@ static inline void printChar(raw_ostream &OS, char C) {
///
/// @tparam SeqT The sequence container. (vector or string).
/// @tparam Less A stable comparator for SeqT elements.
-template<typename SeqT, typename Less = std::less<typename SeqT::value_type> >
+template <typename SeqT, typename Less = std::less<typename SeqT::value_type>>
class SequenceToOffsetTable {
typedef typename SeqT::value_type ElemT;
@@ -53,8 +53,8 @@ class SequenceToOffsetTable {
struct SeqLess {
Less L;
bool operator()(const SeqT &A, const SeqT &B) const {
- return std::lexicographical_compare(A.rbegin(), A.rend(),
- B.rbegin(), B.rend(), L);
+ return std::lexicographical_compare(A.rbegin(), A.rend(), B.rbegin(),
+ B.rend(), L);
}
};
@@ -153,15 +153,15 @@ class SequenceToOffsetTable {
/// emit - Print out the table as the body of an array initializer.
/// Use the Print function to print elements.
- void emit(raw_ostream &OS,
- void (*Print)(raw_ostream&, ElemT),
+ void emit(raw_ostream &OS, void (*Print)(raw_ostream &, ElemT),
const char *Term = "0") const {
assert((empty() || Entries) && "Call layout() before emit()");
for (typename SeqMap::const_iterator I = Seqs.begin(), E = Seqs.end();
I != E; ++I) {
OS << " /* " << I->second << " */ ";
for (typename SeqT::const_iterator SI = I->first.begin(),
- SE = I->first.end(); SI != SE; ++SI) {
+ SE = I->first.end();
+ SI != SE; ++SI) {
Print(OS, *SI);
OS << ", ";
}
diff --git a/llvm/utils/TableGen/CMakeLists.txt b/llvm/utils/TableGen/CMakeLists.txt
index 0100bf345ec29e..14690329cabf70 100644
--- a/llvm/utils/TableGen/CMakeLists.txt
+++ b/llvm/utils/TableGen/CMakeLists.txt
@@ -1,26 +1,25 @@
-add_subdirectory(GlobalISel)
+# Basic utilities which is the strict minimum needed to build
+# llvm-min-tblgen.
+add_subdirectory(Basic)
+# Common utilities are all of the reusable components and helper
+# code needed by the backends.
+add_subdirectory(Common)
-add_llvm_library(LLVMTableGenCommon STATIC OBJECT EXCLUDE_FROM_ALL
+set(LLVM_LINK_COMPONENTS Support)
+
+# llvm-min-tablegen only contains a subset of backends necessary to
+# build llvm/include. It must not depend on TableGenCommon, as
+# TableGenCommon depends on this already to generate things such as
+# ValueType definitions.
+add_tablegen(llvm-min-tblgen LLVM_HEADERS
+ TableGen.cpp
Attributes.cpp
- CodeGenIntrinsics.cpp
DirectiveEmitter.cpp
IntrinsicEmitter.cpp
RISCVTargetDefEmitter.cpp
- SDNodeProperties.cpp
VTEmitter.cpp
- PARTIAL_SOURCES_INTENDED
-
- LINK_COMPONENTS
- Support
- TableGen
- )
-set_target_properties(LLVMTableGenCommon PROPERTIES FOLDER "Tablegenning")
+ $<TARGET_OBJECTS:obj.LLVMTableGenBasic>
-set(LLVM_LINK_COMPONENTS Support)
-
-add_tablegen(llvm-min-tblgen LLVM_HEADERS
- TableGen.cpp
- $<TARGET_OBJECTS:obj.LLVMTableGenCommon>
PARTIAL_SOURCES_INTENDED
)
set_target_properties(llvm-min-tblgen PROPERTIES FOLDER "Tablegenning")
@@ -35,63 +34,51 @@ add_tablegen(llvm-tblgen LLVM
EXPORT LLVM
AsmMatcherEmitter.cpp
AsmWriterEmitter.cpp
- AsmWriterInst.cpp
- CTagsEmitter.cpp
+ Attributes.cpp
CallingConvEmitter.cpp
CodeEmitterGen.cpp
- CodeGenDAGPatterns.cpp
- CodeGenHwModes.cpp
- CodeGenInstAlias.cpp
- CodeGenInstruction.cpp
CodeGenMapTable.cpp
- CodeGenRegisters.cpp
- CodeGenSchedule.cpp
- CodeGenTarget.cpp
+ CompressInstEmitter.cpp
+ CTagsEmitter.cpp
DAGISelEmitter.cpp
DAGISelMatcherEmitter.cpp
DAGISelMatcherGen.cpp
DAGISelMatcherOpt.cpp
- DAGISelMatcher.cpp
DecoderEmitter.cpp
DFAEmitter.cpp
DFAPacketizerEmitter.cpp
+ DirectiveEmitter.cpp
DisassemblerEmitter.cpp
DXILEmitter.cpp
ExegesisEmitter.cpp
FastISelEmitter.cpp
GlobalISelCombinerEmitter.cpp
GlobalISelEmitter.cpp
- GlobalISelMatchTable.cpp
- GlobalISelMatchTableExecutorEmitter.cpp
- InfoByHwMode.cpp
- InstrInfoEmitter.cpp
InstrDocsEmitter.cpp
- OptEmitter.cpp
+ InstrInfoEmitter.cpp
+ IntrinsicEmitter.cpp
+ MacroFusionPredicatorEmitter.cpp
OptParserEmitter.cpp
OptRSTEmitter.cpp
- PredicateExpander.cpp
PseudoLoweringEmitter.cpp
- CompressInstEmitter.cpp
- MacroFusionPredicatorEmitter.cpp
RegisterBankEmitter.cpp
RegisterInfoEmitter.cpp
+ RISCVTargetDefEmitter.cpp
SearchableTableEmitter.cpp
SubtargetEmitter.cpp
- SubtargetFeatureInfo.cpp
TableGen.cpp
- Types.cpp
- VarLenCodeEmitterGen.cpp
- X86DisassemblerTables.cpp
+ VTEmitter.cpp
+ WebAssemblyDisassemblerEmitter.cpp
X86CompressEVEXTablesEmitter.cpp
+ X86DisassemblerTables.cpp
X86FoldTablesEmitter.cpp
X86MnemonicTables.cpp
X86ModRMFilters.cpp
X86RecognizableInstr.cpp
- WebAssemblyDisassemblerEmitter.cpp
$<TARGET_OBJECTS:obj.LLVMTableGenCommon>
DEPENDS
intrinsics_gen # via llvm-min-tablegen
)
-target_link_libraries(llvm-tblgen PRIVATE LLVMTableGenGlobalISel)
+target_link_libraries(llvm-tblgen PRIVATE LLVMTableGenCommon)
set_target_properties(llvm-tblgen PROPERTIES FOLDER "Tablegenning")
diff --git a/llvm/utils/TableGen/CallingConvEmitter.cpp b/llvm/utils/TableGen/CallingConvEmitter.cpp
index 02e7000130cde1..0d232f1c04663e 100644
--- a/llvm/utils/TableGen/CallingConvEmitter.cpp
+++ b/llvm/utils/TableGen/CallingConvEmitter.cpp
@@ -11,7 +11,7 @@
//
//===----------------------------------------------------------------------===//
-#include "CodeGenTarget.h"
+#include "Common/CodeGenTarget.h"
#include "llvm/TableGen/Error.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
@@ -117,7 +117,7 @@ void CallingConvEmitter::EmitCallingConv(Record *CC, raw_ostream &O) {
O << "\n";
EmitAction(Action, 2, O);
}
-
+
O << "\n return true; // CC didn't match.\n";
O << "}\n";
}
@@ -128,7 +128,7 @@ void CallingConvEmitter::EmitAction(Record *Action,
if (Action->isSubClassOf("CCPredicateAction")) {
O << IndentStr << "if (";
-
+
if (Action->isSubClassOf("CCIfType")) {
ListInit *VTs = Action->getValueAsListInit("VTs");
for (unsigned i = 0, e = VTs->size(); i != e; ++i) {
@@ -143,7 +143,7 @@ void CallingConvEmitter::EmitAction(Record *Action,
errs() << *Action;
PrintFatalError(Action->getLoc(), "Unknown CCPredicateAction!");
}
-
+
O << ") {\n";
EmitAction(Action->getValueAsDef("SubAction"), Indent+2, O);
O << IndentStr << "}\n";
diff --git a/llvm/utils/TableGen/CodeEmitterGen.cpp b/llvm/utils/TableGen/CodeEmitterGen.cpp
index 48ed319bf06f47..50a5d482ac939a 100644
--- a/llvm/utils/TableGen/CodeEmitterGen.cpp
+++ b/llvm/utils/TableGen/CodeEmitterGen.cpp
@@ -22,11 +22,11 @@
//
//===----------------------------------------------------------------------===//
-#include "CodeGenHwModes.h"
-#include "CodeGenInstruction.h"
-#include "CodeGenTarget.h"
-#include "InfoByHwMode.h"
-#include "VarLenCodeEmitterGen.h"
+#include "Common/CodeGenHwModes.h"
+#include "Common/CodeGenInstruction.h"
+#include "Common/CodeGenTarget.h"
+#include "Common/InfoByHwMode.h"
+#include "Common/VarLenCodeEmitterGen.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/StringExtras.h"
@@ -107,10 +107,10 @@ bool CodeEmitterGen::addCodeToMergeInOperand(Record *R, BitsInit *BI,
for (; bit >= 0; ) {
if (getVariableBit(VarName, BI, bit) != -1)
break;
-
+
--bit;
}
-
+
// If we found no bits, ignore this value, otherwise emit the call to get the
// operand encoding.
if (bit < 0)
@@ -195,7 +195,7 @@ bool CodeEmitterGen::addCodeToMergeInOperand(Record *R, BitsInit *BI,
unsigned BitOffset = -1;
for (; bit >= 0; ) {
int varBit = getVariableBit(VarName, BI, bit);
-
+
// If this bit isn't from a variable, skip it.
if (varBit == -1) {
--bit;
diff --git a/llvm/utils/TableGen/CodeGenHwModes.h b/llvm/utils/TableGen/CodeGenHwModes.h
deleted file mode 100644
index 09d20ad85c5ec1..00000000000000
--- a/llvm/utils/TableGen/CodeGenHwModes.h
+++ /dev/null
@@ -1,67 +0,0 @@
-//===--- CodeGenHwModes.h ---------------------------------------*- C++ -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-// Classes to parse and store HW mode information for instruction selection.
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_UTILS_TABLEGEN_CODEGENHWMODES_H
-#define LLVM_UTILS_TABLEGEN_CODEGENHWMODES_H
-
-#include "llvm/ADT/DenseMap.h"
-#include "llvm/ADT/StringRef.h"
-#include <cassert>
-#include <map>
-#include <string>
-#include <utility>
-#include <vector>
-
-// HwModeId -> list of predicates (definition)
-
-namespace llvm {
- class Record;
- class RecordKeeper;
-
- struct CodeGenHwModes;
-
- struct HwMode {
- HwMode(Record *R);
- StringRef Name;
- std::string Features;
- std::string Predicates;
- void dump() const;
- };
-
- struct HwModeSelect {
- HwModeSelect(Record *R, CodeGenHwModes &CGH);
- typedef std::pair<unsigned, Record*> PairType;
- std::vector<PairType> Items;
- void dump() const;
- };
-
- struct CodeGenHwModes {
- enum : unsigned { DefaultMode = 0 };
- static StringRef DefaultModeName;
-
- CodeGenHwModes(RecordKeeper &R);
- unsigned getHwModeId(Record *R) const;
- const HwMode &getMode(unsigned Id) const {
- assert(Id != 0 && "Mode id of 0 is reserved for the default mode");
- return Modes[Id-1];
- }
- const HwModeSelect &getHwModeSelect(Record *R) const;
- unsigned getNumModeIds() const { return Modes.size()+1; }
- void dump() const;
-
- private:
- RecordKeeper &Records;
- DenseMap<Record *, unsigned> ModeIds; // HwMode Record -> HwModeId
- std::vector<HwMode> Modes;
- std::map<Record*,HwModeSelect> ModeSelects;
- };
-}
-
-#endif // LLVM_UTILS_TABLEGEN_CODEGENHWMODES_H
diff --git a/llvm/utils/TableGen/CodeGenInstruction.h b/llvm/utils/TableGen/CodeGenInstruction.h
deleted file mode 100644
index 8b3e670d3ff7cd..00000000000000
--- a/llvm/utils/TableGen/CodeGenInstruction.h
+++ /dev/null
@@ -1,343 +0,0 @@
-//===- CodeGenInstruction.h - Instruction Class Wrapper ---------*- C++ -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines a wrapper class for the 'Instruction' TableGen class.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_UTILS_TABLEGEN_CODEGENINSTRUCTION_H
-#define LLVM_UTILS_TABLEGEN_CODEGENINSTRUCTION_H
-
-#include "llvm/ADT/BitVector.h"
-#include "llvm/ADT/StringMap.h"
-#include "llvm/ADT/StringRef.h"
-#include "llvm/CodeGenTypes/MachineValueType.h"
-#include <cassert>
-#include <string>
-#include <utility>
-#include <vector>
-
-namespace llvm {
- class Record;
- class DagInit;
- class CodeGenTarget;
-
- class CGIOperandList {
- public:
- class ConstraintInfo {
- enum { None, EarlyClobber, Tied } Kind = None;
- unsigned OtherTiedOperand = 0;
-
- public:
- ConstraintInfo() = default;
-
- static ConstraintInfo getEarlyClobber() {
- ConstraintInfo I;
- I.Kind = EarlyClobber;
- I.OtherTiedOperand = 0;
- return I;
- }
-
- static ConstraintInfo getTied(unsigned Op) {
- ConstraintInfo I;
- I.Kind = Tied;
- I.OtherTiedOperand = Op;
- return I;
- }
-
- bool isNone() const { return Kind == None; }
- bool isEarlyClobber() const { return Kind == EarlyClobber; }
- bool isTied() const { return Kind == Tied; }
-
- unsigned getTiedOperand() const {
- assert(isTied());
- return OtherTiedOperand;
- }
-
- bool operator==(const ConstraintInfo &RHS) const {
- if (Kind != RHS.Kind)
- return false;
- if (Kind == Tied && OtherTiedOperand != RHS.OtherTiedOperand)
- return false;
- return true;
- }
- bool operator!=(const ConstraintInfo &RHS) const {
- return !(*this == RHS);
- }
- };
-
- /// OperandInfo - The information we keep track of for each operand in the
- /// operand list for a tablegen instruction.
- struct OperandInfo {
- /// Rec - The definition this operand is declared as.
- ///
- Record *Rec;
-
- /// Name - If this operand was assigned a symbolic name, this is it,
- /// otherwise, it's empty.
- std::string Name;
-
- /// The names of sub-operands, if given, otherwise empty.
- std::vector<std::string> SubOpNames;
-
- /// PrinterMethodName - The method used to print operands of this type in
- /// the asmprinter.
- std::string PrinterMethodName;
-
- /// The method used to get the machine operand value for binary
- /// encoding, per sub-operand. If empty, uses "getMachineOpValue".
- std::vector<std::string> EncoderMethodNames;
-
- /// OperandType - A value from MCOI::OperandType representing the type of
- /// the operand.
- std::string OperandType;
-
- /// MIOperandNo - Currently (this is meant to be phased out), some logical
- /// operands correspond to multiple MachineInstr operands. In the X86
- /// target for example, one address operand is represented as 4
- /// MachineOperands. Because of this, the operand number in the
- /// OperandList may not match the MachineInstr operand num. Until it
- /// does, this contains the MI operand index of this operand.
- unsigned MIOperandNo;
- unsigned MINumOperands; // The number of operands.
-
- /// DoNotEncode - Bools are set to true in this vector for each operand in
- /// the DisableEncoding list. These should not be emitted by the code
- /// emitter.
- BitVector DoNotEncode;
-
- /// MIOperandInfo - Default MI operand type. Note an operand may be made
- /// up of multiple MI operands.
- DagInit *MIOperandInfo;
-
- /// Constraint info for this operand. This operand can have pieces, so we
- /// track constraint info for each.
- std::vector<ConstraintInfo> Constraints;
-
- OperandInfo(Record *R, const std::string &N, const std::string &PMN,
- const std::string &OT, unsigned MION, unsigned MINO,
- DagInit *MIOI)
- : Rec(R), Name(N), SubOpNames(MINO), PrinterMethodName(PMN),
- EncoderMethodNames(MINO), OperandType(OT), MIOperandNo(MION),
- MINumOperands(MINO), DoNotEncode(MINO), MIOperandInfo(MIOI),
- Constraints(MINO) {}
-
- /// getTiedOperand - If this operand is tied to another one, return the
- /// other operand number. Otherwise, return -1.
- int getTiedRegister() const {
- for (unsigned j = 0, e = Constraints.size(); j != e; ++j) {
- const CGIOperandList::ConstraintInfo &CI = Constraints[j];
- if (CI.isTied()) return CI.getTiedOperand();
- }
- return -1;
- }
- };
-
- CGIOperandList(Record *D);
-
- Record *TheDef; // The actual record containing this OperandList.
-
- /// NumDefs - Number of def operands declared, this is the number of
- /// elements in the instruction's (outs) list.
- ///
- unsigned NumDefs;
-
- /// OperandList - The list of declared operands, along with their declared
- /// type (which is a record).
- std::vector<OperandInfo> OperandList;
-
- /// SubOpAliases - List of alias names for suboperands.
- StringMap<std::pair<unsigned, unsigned>> SubOpAliases;
-
- // Information gleaned from the operand list.
- bool isPredicable;
- bool hasOptionalDef;
- bool isVariadic;
-
- // Provide transparent accessors to the operand list.
- bool empty() const { return OperandList.empty(); }
- unsigned size() const { return OperandList.size(); }
- const OperandInfo &operator[](unsigned i) const { return OperandList[i]; }
- OperandInfo &operator[](unsigned i) { return OperandList[i]; }
- OperandInfo &back() { return OperandList.back(); }
- const OperandInfo &back() const { return OperandList.back(); }
-
- typedef std::vector<OperandInfo>::iterator iterator;
- typedef std::vector<OperandInfo>::const_iterator const_iterator;
- iterator begin() { return OperandList.begin(); }
- const_iterator begin() const { return OperandList.begin(); }
- iterator end() { return OperandList.end(); }
- const_iterator end() const { return OperandList.end(); }
-
- /// getOperandNamed - Return the index of the operand with the specified
- /// non-empty name. If the instruction does not have an operand with the
- /// specified name, abort.
- unsigned getOperandNamed(StringRef Name) const;
-
- /// hasOperandNamed - Query whether the instruction has an operand of the
- /// given name. If so, return true and set OpIdx to the index of the
- /// operand. Otherwise, return false.
- bool hasOperandNamed(StringRef Name, unsigned &OpIdx) const;
-
- bool hasSubOperandAlias(StringRef Name,
- std::pair<unsigned, unsigned> &SubOp) const;
-
- /// ParseOperandName - Parse an operand name like "$foo" or "$foo.bar",
- /// where $foo is a whole operand and $foo.bar refers to a suboperand.
- /// This aborts if the name is invalid. If AllowWholeOp is true, references
- /// to operands with suboperands are allowed, otherwise not.
- std::pair<unsigned,unsigned> ParseOperandName(StringRef Op,
- bool AllowWholeOp = true);
-
- /// getFlattenedOperandNumber - Flatten a operand/suboperand pair into a
- /// flat machineinstr operand #.
- unsigned getFlattenedOperandNumber(std::pair<unsigned,unsigned> Op) const {
- return OperandList[Op.first].MIOperandNo + Op.second;
- }
-
- /// getSubOperandNumber - Unflatten a operand number into an
- /// operand/suboperand pair.
- std::pair<unsigned,unsigned> getSubOperandNumber(unsigned Op) const {
- for (unsigned i = 0; ; ++i) {
- assert(i < OperandList.size() && "Invalid flat operand #");
- if (OperandList[i].MIOperandNo+OperandList[i].MINumOperands > Op)
- return std::make_pair(i, Op-OperandList[i].MIOperandNo);
- }
- }
-
-
- /// isFlatOperandNotEmitted - Return true if the specified flat operand #
- /// should not be emitted with the code emitter.
- bool isFlatOperandNotEmitted(unsigned FlatOpNo) const {
- std::pair<unsigned,unsigned> Op = getSubOperandNumber(FlatOpNo);
- if (OperandList[Op.first].DoNotEncode.size() > Op.second)
- return OperandList[Op.first].DoNotEncode[Op.second];
- return false;
- }
-
- void ProcessDisableEncoding(StringRef Value);
- };
-
-
- class CodeGenInstruction {
- public:
- Record *TheDef; // The actual record defining this instruction.
- StringRef Namespace; // The namespace the instruction is in.
-
- /// AsmString - The format string used to emit a .s file for the
- /// instruction.
- std::string AsmString;
-
- /// Operands - This is information about the (ins) and (outs) list specified
- /// to the instruction.
- CGIOperandList Operands;
-
- /// ImplicitDefs/ImplicitUses - These are lists of registers that are
- /// implicitly defined and used by the instruction.
- std::vector<Record*> ImplicitDefs, ImplicitUses;
-
- // Various boolean values we track for the instruction.
- bool isPreISelOpcode : 1;
- bool isReturn : 1;
- bool isEHScopeReturn : 1;
- bool isBranch : 1;
- bool isIndirectBranch : 1;
- bool isCompare : 1;
- bool isMoveImm : 1;
- bool isMoveReg : 1;
- bool isBitcast : 1;
- bool isSelect : 1;
- bool isBarrier : 1;
- bool isCall : 1;
- bool isAdd : 1;
- bool isTrap : 1;
- bool canFoldAsLoad : 1;
- bool mayLoad : 1;
- bool mayLoad_Unset : 1;
- bool mayStore : 1;
- bool mayStore_Unset : 1;
- bool mayRaiseFPException : 1;
- bool isPredicable : 1;
- bool isConvertibleToThreeAddress : 1;
- bool isCommutable : 1;
- bool isTerminator : 1;
- bool isReMaterializable : 1;
- bool hasDelaySlot : 1;
- bool usesCustomInserter : 1;
- bool hasPostISelHook : 1;
- bool hasCtrlDep : 1;
- bool isNotDuplicable : 1;
- bool hasSideEffects : 1;
- bool hasSideEffects_Unset : 1;
- bool isAsCheapAsAMove : 1;
- bool hasExtraSrcRegAllocReq : 1;
- bool hasExtraDefRegAllocReq : 1;
- bool isCodeGenOnly : 1;
- bool isPseudo : 1;
- bool isMeta : 1;
- bool isRegSequence : 1;
- bool isExtractSubreg : 1;
- bool isInsertSubreg : 1;
- bool isConvergent : 1;
- bool hasNoSchedulingInfo : 1;
- bool FastISelShouldIgnore : 1;
- bool hasChain : 1;
- bool hasChain_Inferred : 1;
- bool variadicOpsAreDefs : 1;
- bool isAuthenticated : 1;
-
- std::string DeprecatedReason;
- bool HasComplexDeprecationPredicate;
-
- /// Are there any undefined flags?
- bool hasUndefFlags() const {
- return mayLoad_Unset || mayStore_Unset || hasSideEffects_Unset;
- }
-
- // The record used to infer instruction flags, or NULL if no flag values
- // have been inferred.
- Record *InferredFrom;
-
- CodeGenInstruction(Record *R);
-
- /// HasOneImplicitDefWithKnownVT - If the instruction has at least one
- /// implicit def and it has a known VT, return the VT, otherwise return
- /// MVT::Other.
- MVT::SimpleValueType
- HasOneImplicitDefWithKnownVT(const CodeGenTarget &TargetInfo) const;
-
-
- /// FlattenAsmStringVariants - Flatten the specified AsmString to only
- /// include text from the specified variant, returning the new string.
- static std::string FlattenAsmStringVariants(StringRef AsmString,
- unsigned Variant);
-
- // Is the specified operand in a generic instruction implicitly a pointer.
- // This can be used on intructions that use typeN or ptypeN to identify
- // operands that should be considered as pointers even though SelectionDAG
- // didn't make a distinction between integer and pointers.
- bool isInOperandAPointer(unsigned i) const {
- return isOperandImpl("InOperandList", i, "IsPointer");
- }
-
- bool isOutOperandAPointer(unsigned i) const {
- return isOperandImpl("OutOperandList", i, "IsPointer");
- }
-
- /// Check if the operand is required to be an immediate.
- bool isInOperandImmArg(unsigned i) const {
- return isOperandImpl("InOperandList", i, "IsImmediate");
- }
-
- private:
- bool isOperandImpl(StringRef OpListName, unsigned i,
- StringRef PropertyName) const;
- };
-} // namespace llvm
-
-#endif
diff --git a/llvm/utils/TableGen/CodeGenMapTable.cpp b/llvm/utils/TableGen/CodeGenMapTable.cpp
index fd375735dfd2ad..f182be6b887960 100644
--- a/llvm/utils/TableGen/CodeGenMapTable.cpp
+++ b/llvm/utils/TableGen/CodeGenMapTable.cpp
@@ -75,8 +75,8 @@
//
//===----------------------------------------------------------------------===//
-#include "CodeGenInstruction.h"
-#include "CodeGenTarget.h"
+#include "Common/CodeGenInstruction.h"
+#include "Common/CodeGenTarget.h"
#include "llvm/TableGen/Error.h"
#include "llvm/TableGen/Record.h"
using namespace llvm;
diff --git a/llvm/utils/TableGen/CodeGenRegisters.h b/llvm/utils/TableGen/CodeGenRegisters.h
deleted file mode 100644
index 97f60811a7d864..00000000000000
--- a/llvm/utils/TableGen/CodeGenRegisters.h
+++ /dev/null
@@ -1,854 +0,0 @@
-//===- CodeGenRegisters.h - Register and RegisterClass Info -----*- C++ -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines structures to encapsulate information gleaned from the
-// target register and register class definitions.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H
-#define LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H
-
-#include "CodeGenHwModes.h"
-#include "InfoByHwMode.h"
-#include "llvm/ADT/ArrayRef.h"
-#include "llvm/ADT/BitVector.h"
-#include "llvm/ADT/DenseMap.h"
-#include "llvm/ADT/STLExtras.h"
-#include "llvm/ADT/SetVector.h"
-#include "llvm/ADT/SmallPtrSet.h"
-#include "llvm/ADT/SmallVector.h"
-#include "llvm/ADT/SparseBitVector.h"
-#include "llvm/ADT/StringMap.h"
-#include "llvm/ADT/StringRef.h"
-#include "llvm/MC/LaneBitmask.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/TableGen/Record.h"
-#include "llvm/TableGen/SetTheory.h"
-#include <cassert>
-#include <cstdint>
-#include <deque>
-#include <functional>
-#include <list>
-#include <map>
-#include <memory>
-#include <optional>
-#include <string>
-#include <utility>
-#include <vector>
-
-namespace llvm {
-
- class CodeGenRegBank;
-
- /// Used to encode a step in a register lane mask transformation.
- /// Mask the bits specified in Mask, then rotate them Rol bits to the left
- /// assuming a wraparound at 32bits.
- struct MaskRolPair {
- LaneBitmask Mask;
- uint8_t RotateLeft;
-
- bool operator==(const MaskRolPair Other) const {
- return Mask == Other.Mask && RotateLeft == Other.RotateLeft;
- }
- bool operator!=(const MaskRolPair Other) const {
- return Mask != Other.Mask || RotateLeft != Other.RotateLeft;
- }
- };
-
- /// CodeGenSubRegIndex - Represents a sub-register index.
- class CodeGenSubRegIndex {
- Record *const TheDef;
- std::string Name;
- std::string Namespace;
-
- public:
- uint16_t Size;
- uint16_t Offset;
- const unsigned EnumValue;
- mutable LaneBitmask LaneMask;
- mutable SmallVector<MaskRolPair,1> CompositionLaneMaskTransform;
-
- /// A list of subregister indexes concatenated resulting in this
- /// subregister index. This is the reverse of CodeGenRegBank::ConcatIdx.
- SmallVector<CodeGenSubRegIndex*,4> ConcatenationOf;
-
- // Are all super-registers containing this SubRegIndex covered by their
- // sub-registers?
- bool AllSuperRegsCovered;
- // A subregister index is "artificial" if every subregister obtained
- // from applying this index is artificial. Artificial subregister
- // indexes are not used to create new register classes.
- bool Artificial;
-
- CodeGenSubRegIndex(Record *R, unsigned Enum);
- CodeGenSubRegIndex(StringRef N, StringRef Nspace, unsigned Enum);
- CodeGenSubRegIndex(CodeGenSubRegIndex&) = delete;
-
- const std::string &getName() const { return Name; }
- const std::string &getNamespace() const { return Namespace; }
- std::string getQualifiedName() const;
-
- // Map of composite subreg indices.
- typedef std::map<CodeGenSubRegIndex *, CodeGenSubRegIndex *,
- deref<std::less<>>>
- CompMap;
-
- // Returns the subreg index that results from composing this with Idx.
- // Returns NULL if this and Idx don't compose.
- CodeGenSubRegIndex *compose(CodeGenSubRegIndex *Idx) const {
- CompMap::const_iterator I = Composed.find(Idx);
- return I == Composed.end() ? nullptr : I->second;
- }
-
- // Add a composite subreg index: this+A = B.
- // Return a conflicting composite, or NULL
- CodeGenSubRegIndex *addComposite(CodeGenSubRegIndex *A,
- CodeGenSubRegIndex *B) {
- assert(A && B);
- std::pair<CompMap::iterator, bool> Ins =
- Composed.insert(std::make_pair(A, B));
- // Synthetic subreg indices that aren't contiguous (for instance ARM
- // register tuples) don't have a bit range, so it's OK to let
- // B->Offset == -1. For the other cases, accumulate the offset and set
- // the size here. Only do so if there is no offset yet though.
- if ((Offset != (uint16_t)-1 && A->Offset != (uint16_t)-1) &&
- (B->Offset == (uint16_t)-1)) {
- B->Offset = Offset + A->Offset;
- B->Size = A->Size;
- }
- return (Ins.second || Ins.first->second == B) ? nullptr
- : Ins.first->second;
- }
-
- // Update the composite maps of components specified in 'ComposedOf'.
- void updateComponents(CodeGenRegBank&);
-
- // Return the map of composites.
- const CompMap &getComposites() const { return Composed; }
-
- // Compute LaneMask from Composed. Return LaneMask.
- LaneBitmask computeLaneMask() const;
-
- void setConcatenationOf(ArrayRef<CodeGenSubRegIndex*> Parts);
-
- /// Replaces subregister indexes in the `ConcatenationOf` list with
- /// list of subregisters they are composed of (if any). Do this recursively.
- void computeConcatTransitiveClosure();
-
- bool operator<(const CodeGenSubRegIndex &RHS) const {
- return this->EnumValue < RHS.EnumValue;
- }
-
- private:
- CompMap Composed;
- };
-
- /// CodeGenRegister - Represents a register definition.
- class CodeGenRegister {
- public:
- Record *TheDef;
- unsigned EnumValue;
- std::vector<int64_t> CostPerUse;
- bool CoveredBySubRegs = true;
- bool HasDisjunctSubRegs = false;
- bool Artificial = true;
- bool Constant = false;
-
- // Map SubRegIndex -> Register.
- typedef std::map<CodeGenSubRegIndex *, CodeGenRegister *,
- deref<std::less<>>>
- SubRegMap;
-
- CodeGenRegister(Record *R, unsigned Enum);
-
- StringRef getName() const;
-
- // Extract more information from TheDef. This is used to build an object
- // graph after all CodeGenRegister objects have been created.
- void buildObjectGraph(CodeGenRegBank&);
-
- // Lazily compute a map of all sub-registers.
- // This includes unique entries for all sub-sub-registers.
- const SubRegMap &computeSubRegs(CodeGenRegBank&);
-
- // Compute extra sub-registers by combining the existing sub-registers.
- void computeSecondarySubRegs(CodeGenRegBank&);
-
- // Add this as a super-register to all sub-registers after the sub-register
- // graph has been built.
- void computeSuperRegs(CodeGenRegBank&);
-
- const SubRegMap &getSubRegs() const {
- assert(SubRegsComplete && "Must precompute sub-registers");
- return SubRegs;
- }
-
- // Add sub-registers to OSet following a pre-order defined by the .td file.
- void addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet,
- CodeGenRegBank&) const;
-
- // Return the sub-register index naming Reg as a sub-register of this
- // register. Returns NULL if Reg is not a sub-register.
- CodeGenSubRegIndex *getSubRegIndex(const CodeGenRegister *Reg) const {
- return SubReg2Idx.lookup(Reg);
- }
-
- typedef std::vector<const CodeGenRegister*> SuperRegList;
-
- // Get the list of super-registers in topological order, small to large.
- // This is valid after computeSubRegs visits all registers during RegBank
- // construction.
- const SuperRegList &getSuperRegs() const {
- assert(SubRegsComplete && "Must precompute sub-registers");
- return SuperRegs;
- }
-
- // Get the list of ad hoc aliases. The graph is symmetric, so the list
- // contains all registers in 'Aliases', and all registers that mention this
- // register in 'Aliases'.
- ArrayRef<CodeGenRegister*> getExplicitAliases() const {
- return ExplicitAliases;
- }
-
- // Get the topological signature of this register. This is a small integer
- // less than RegBank.getNumTopoSigs(). Registers with the same TopoSig have
- // identical sub-register structure. That is, they support the same set of
- // sub-register indices mapping to the same kind of sub-registers
- // (TopoSig-wise).
- unsigned getTopoSig() const {
- assert(SuperRegsComplete && "TopoSigs haven't been computed yet.");
- return TopoSig;
- }
-
- // List of register units in ascending order.
- typedef SparseBitVector<> RegUnitList;
- typedef SmallVector<LaneBitmask, 16> RegUnitLaneMaskList;
-
- // How many entries in RegUnitList are native?
- RegUnitList NativeRegUnits;
-
- // Get the list of register units.
- // This is only valid after computeSubRegs() completes.
- const RegUnitList &getRegUnits() const { return RegUnits; }
-
- ArrayRef<LaneBitmask> getRegUnitLaneMasks() const {
- return ArrayRef(RegUnitLaneMasks).slice(0, NativeRegUnits.count());
- }
-
- // Get the native register units. This is a prefix of getRegUnits().
- RegUnitList getNativeRegUnits() const {
- return NativeRegUnits;
- }
-
- void setRegUnitLaneMasks(const RegUnitLaneMaskList &LaneMasks) {
- RegUnitLaneMasks = LaneMasks;
- }
-
- // Inherit register units from subregisters.
- // Return true if the RegUnits changed.
- bool inheritRegUnits(CodeGenRegBank &RegBank);
-
- // Adopt a register unit for pressure tracking.
- // A unit is adopted iff its unit number is >= NativeRegUnits.count().
- void adoptRegUnit(unsigned RUID) { RegUnits.set(RUID); }
-
- // Get the sum of this register's register unit weights.
- unsigned getWeight(const CodeGenRegBank &RegBank) const;
-
- // Canonically ordered set.
- typedef std::vector<const CodeGenRegister*> Vec;
-
- private:
- bool SubRegsComplete;
- bool SuperRegsComplete;
- unsigned TopoSig;
-
- // The sub-registers explicit in the .td file form a tree.
- SmallVector<CodeGenSubRegIndex*, 8> ExplicitSubRegIndices;
- SmallVector<CodeGenRegister*, 8> ExplicitSubRegs;
-
- // Explicit ad hoc aliases, symmetrized to form an undirected graph.
- SmallVector<CodeGenRegister*, 8> ExplicitAliases;
-
- // Super-registers where this is the first explicit sub-register.
- SuperRegList LeadingSuperRegs;
-
- SubRegMap SubRegs;
- SuperRegList SuperRegs;
- DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*> SubReg2Idx;
- RegUnitList RegUnits;
- RegUnitLaneMaskList RegUnitLaneMasks;
- };
-
- inline bool operator<(const CodeGenRegister &A, const CodeGenRegister &B) {
- return A.EnumValue < B.EnumValue;
- }
-
- inline bool operator==(const CodeGenRegister &A, const CodeGenRegister &B) {
- return A.EnumValue == B.EnumValue;
- }
-
- class CodeGenRegisterClass {
- CodeGenRegister::Vec Members;
- // Allocation orders. Order[0] always contains all registers in Members.
- std::vector<SmallVector<Record*, 16>> Orders;
- // Bit mask of sub-classes including this, indexed by their EnumValue.
- BitVector SubClasses;
- // List of super-classes, topologocally ordered to have the larger classes
- // first. This is the same as sorting by EnumValue.
- SmallVector<CodeGenRegisterClass*, 4> SuperClasses;
- Record *TheDef;
- std::string Name;
-
- // For a synthesized class, inherit missing properties from the nearest
- // super-class.
- void inheritProperties(CodeGenRegBank&);
-
- // Map SubRegIndex -> sub-class. This is the largest sub-class where all
- // registers have a SubRegIndex sub-register.
- DenseMap<const CodeGenSubRegIndex *, CodeGenRegisterClass *>
- SubClassWithSubReg;
-
- // Map SubRegIndex -> set of super-reg classes. This is all register
- // classes SuperRC such that:
- //
- // R:SubRegIndex in this RC for all R in SuperRC.
- //
- DenseMap<const CodeGenSubRegIndex *, SmallPtrSet<CodeGenRegisterClass *, 8>>
- SuperRegClasses;
-
- // Bit vector of TopoSigs for the registers in this class. This will be
- // very sparse on regular architectures.
- BitVector TopoSigs;
-
- public:
- unsigned EnumValue;
- StringRef Namespace;
- SmallVector<ValueTypeByHwMode, 4> VTs;
- RegSizeInfoByHwMode RSI;
- int CopyCost;
- bool Allocatable;
- StringRef AltOrderSelect;
- uint8_t AllocationPriority;
- bool GlobalPriority;
- uint8_t TSFlags;
- /// Contains the combination of the lane masks of all subregisters.
- LaneBitmask LaneMask;
- /// True if there are at least 2 subregisters which do not interfere.
- bool HasDisjunctSubRegs;
- bool CoveredBySubRegs;
- /// A register class is artificial if all its members are artificial.
- bool Artificial;
- /// Generate register pressure set for this register class and any class
- /// synthesized from it.
- bool GeneratePressureSet;
-
- // Return the Record that defined this class, or NULL if the class was
- // created by TableGen.
- Record *getDef() const { return TheDef; }
-
- std::string getNamespaceQualification() const;
- const std::string &getName() const { return Name; }
- std::string getQualifiedName() const;
- std::string getIdName() const;
- std::string getQualifiedIdName() const;
- ArrayRef<ValueTypeByHwMode> getValueTypes() const { return VTs; }
- unsigned getNumValueTypes() const { return VTs.size(); }
- bool hasType(const ValueTypeByHwMode &VT) const;
-
- const ValueTypeByHwMode &getValueTypeNum(unsigned VTNum) const {
- if (VTNum < VTs.size())
- return VTs[VTNum];
- llvm_unreachable("VTNum greater than number of ValueTypes in RegClass!");
- }
-
- // Return true if this class contains the register.
- bool contains(const CodeGenRegister*) const;
-
- // Returns true if RC is a subclass.
- // RC is a sub-class of this class if it is a valid replacement for any
- // instruction operand where a register of this classis required. It must
- // satisfy these conditions:
- //
- // 1. All RC registers are also in this.
- // 2. The RC spill size must not be smaller than our spill size.
- // 3. RC spill alignment must be compatible with ours.
- //
- bool hasSubClass(const CodeGenRegisterClass *RC) const {
- return SubClasses.test(RC->EnumValue);
- }
-
- // getSubClassWithSubReg - Returns the largest sub-class where all
- // registers have a SubIdx sub-register.
- CodeGenRegisterClass *
- getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const {
- return SubClassWithSubReg.lookup(SubIdx);
- }
-
- /// Find largest subclass where all registers have SubIdx subregisters in
- /// SubRegClass and the largest subregister class that contains those
- /// subregisters without (as far as possible) also containing additional registers.
- ///
- /// This can be used to find a suitable pair of classes for subregister copies.
- /// \return std::pair<SubClass, SubRegClass> where SubClass is a SubClass is
- /// a class where every register has SubIdx and SubRegClass is a class where
- /// every register is covered by the SubIdx subregister of SubClass.
- std::optional<std::pair<CodeGenRegisterClass *, CodeGenRegisterClass *>>
- getMatchingSubClassWithSubRegs(CodeGenRegBank &RegBank,
- const CodeGenSubRegIndex *SubIdx) const;
-
- void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx,
- CodeGenRegisterClass *SubRC) {
- SubClassWithSubReg[SubIdx] = SubRC;
- }
-
- // getSuperRegClasses - Returns a bit vector of all register classes
- // containing only SubIdx super-registers of this class.
- void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
- BitVector &Out) const;
-
- // addSuperRegClass - Add a class containing only SubIdx super-registers.
- void addSuperRegClass(CodeGenSubRegIndex *SubIdx,
- CodeGenRegisterClass *SuperRC) {
- SuperRegClasses[SubIdx].insert(SuperRC);
- }
-
- // getSubClasses - Returns a constant BitVector of subclasses indexed by
- // EnumValue.
- // The SubClasses vector includes an entry for this class.
- const BitVector &getSubClasses() const { return SubClasses; }
-
- // getSuperClasses - Returns a list of super classes ordered by EnumValue.
- // The array does not include an entry for this class.
- ArrayRef<CodeGenRegisterClass*> getSuperClasses() const {
- return SuperClasses;
- }
-
- // Returns an ordered list of class members.
- // The order of registers is the same as in the .td file.
- // No = 0 is the default allocation order, No = 1 is the first alternative.
- ArrayRef<Record*> getOrder(unsigned No = 0) const {
- return Orders[No];
- }
-
- // Return the total number of allocation orders available.
- unsigned getNumOrders() const { return Orders.size(); }
-
- // Get the set of registers. This set contains the same registers as
- // getOrder(0).
- const CodeGenRegister::Vec &getMembers() const { return Members; }
-
- // Get a bit vector of TopoSigs present in this register class.
- const BitVector &getTopoSigs() const { return TopoSigs; }
-
- // Get a weight of this register class.
- unsigned getWeight(const CodeGenRegBank&) const;
-
- // Populate a unique sorted list of units from a register set.
- void buildRegUnitSet(const CodeGenRegBank &RegBank,
- std::vector<unsigned> &RegUnits) const;
-
- CodeGenRegisterClass(CodeGenRegBank&, Record *R);
- CodeGenRegisterClass(CodeGenRegisterClass&) = delete;
-
- // A key representing the parts of a register class used for forming
- // sub-classes. Note the ordering provided by this key is not the same as
- // the topological order used for the EnumValues.
- struct Key {
- const CodeGenRegister::Vec *Members;
- RegSizeInfoByHwMode RSI;
-
- Key(const CodeGenRegister::Vec *M, const RegSizeInfoByHwMode &I)
- : Members(M), RSI(I) {}
-
- Key(const CodeGenRegisterClass &RC)
- : Members(&RC.getMembers()), RSI(RC.RSI) {}
-
- // Lexicographical order of (Members, RegSizeInfoByHwMode).
- bool operator<(const Key&) const;
- };
-
- // Create a non-user defined register class.
- CodeGenRegisterClass(CodeGenRegBank&, StringRef Name, Key Props);
-
- // Called by CodeGenRegBank::CodeGenRegBank().
- static void computeSubClasses(CodeGenRegBank&);
-
- // Get ordering value among register base classes.
- std::optional<int> getBaseClassOrder() const {
- if (TheDef && !TheDef->isValueUnset("BaseClassOrder"))
- return TheDef->getValueAsInt("BaseClassOrder");
- return {};
- }
- };
-
- // Register categories are used when we need to deterine the category a
- // register falls into (GPR, vector, fixed, etc.) without having to know
- // specific information about the target architecture.
- class CodeGenRegisterCategory {
- Record *TheDef;
- std::string Name;
- std::list<CodeGenRegisterClass *> Classes;
-
- public:
- CodeGenRegisterCategory(CodeGenRegBank &, Record *R);
- CodeGenRegisterCategory(CodeGenRegisterCategory &) = delete;
-
- // Return the Record that defined this class, or NULL if the class was
- // created by TableGen.
- Record *getDef() const { return TheDef; }
-
- std::string getName() const { return Name; }
- std::list<CodeGenRegisterClass *> getClasses() const { return Classes; }
- };
-
- // Register units are used to model interference and register pressure.
- // Every register is assigned one or more register units such that two
- // registers overlap if and only if they have a register unit in common.
- //
- // Normally, one register unit is created per leaf register. Non-leaf
- // registers inherit the units of their sub-registers.
- struct RegUnit {
- // Weight assigned to this RegUnit for estimating register pressure.
- // This is useful when equalizing weights in register classes with mixed
- // register topologies.
- unsigned Weight;
-
- // Each native RegUnit corresponds to one or two root registers. The full
- // set of registers containing this unit can be computed as the union of
- // these two registers and their super-registers.
- const CodeGenRegister *Roots[2];
-
- // Index into RegClassUnitSets where we can find the list of UnitSets that
- // contain this unit.
- unsigned RegClassUnitSetsIdx;
- // A register unit is artificial if at least one of its roots is
- // artificial.
- bool Artificial;
-
- RegUnit() : Weight(0), RegClassUnitSetsIdx(0), Artificial(false) {
- Roots[0] = Roots[1] = nullptr;
- }
-
- ArrayRef<const CodeGenRegister*> getRoots() const {
- assert(!(Roots[1] && !Roots[0]) && "Invalid roots array");
- return ArrayRef(Roots, !!Roots[0] + !!Roots[1]);
- }
- };
-
- // Each RegUnitSet is a sorted vector with a name.
- struct RegUnitSet {
- typedef std::vector<unsigned>::const_iterator iterator;
-
- std::string Name;
- std::vector<unsigned> Units;
- unsigned Weight = 0; // Cache the sum of all unit weights.
- unsigned Order = 0; // Cache the sort key.
-
- RegUnitSet() = default;
- };
-
- // Base vector for identifying TopoSigs. The contents uniquely identify a
- // TopoSig, only computeSuperRegs needs to know how.
- typedef SmallVector<unsigned, 16> TopoSigId;
-
- // CodeGenRegBank - Represent a target's registers and the relations between
- // them.
- class CodeGenRegBank {
- SetTheory Sets;
-
- const CodeGenHwModes &CGH;
-
- std::deque<CodeGenSubRegIndex> SubRegIndices;
- DenseMap<Record*, CodeGenSubRegIndex*> Def2SubRegIdx;
-
- CodeGenSubRegIndex *createSubRegIndex(StringRef Name, StringRef NameSpace);
-
- typedef std::map<SmallVector<CodeGenSubRegIndex*, 8>,
- CodeGenSubRegIndex*> ConcatIdxMap;
- ConcatIdxMap ConcatIdx;
-
- // Registers.
- std::deque<CodeGenRegister> Registers;
- StringMap<CodeGenRegister*> RegistersByName;
- DenseMap<Record*, CodeGenRegister*> Def2Reg;
- unsigned NumNativeRegUnits;
-
- std::map<TopoSigId, unsigned> TopoSigs;
-
- // Includes native (0..NumNativeRegUnits-1) and adopted register units.
- SmallVector<RegUnit, 8> RegUnits;
-
- // Register classes.
- std::list<CodeGenRegisterClass> RegClasses;
- DenseMap<Record*, CodeGenRegisterClass*> Def2RC;
- typedef std::map<CodeGenRegisterClass::Key, CodeGenRegisterClass*> RCKeyMap;
- RCKeyMap Key2RC;
-
- // Register categories.
- std::list<CodeGenRegisterCategory> RegCategories;
- DenseMap<Record *, CodeGenRegisterCategory *> Def2RCat;
- using RCatKeyMap =
- std::map<CodeGenRegisterClass::Key, CodeGenRegisterCategory *>;
- RCatKeyMap Key2RCat;
-
- // Remember each unique set of register units. Initially, this contains a
- // unique set for each register class. Simliar sets are coalesced with
- // pruneUnitSets and new supersets are inferred during computeRegUnitSets.
- std::vector<RegUnitSet> RegUnitSets;
-
- // Map RegisterClass index to the index of the RegUnitSet that contains the
- // class's units and any inferred RegUnit supersets.
- //
- // NOTE: This could grow beyond the number of register classes when we map
- // register units to lists of unit sets. If the list of unit sets does not
- // already exist for a register class, we create a new entry in this vector.
- std::vector<std::vector<unsigned>> RegClassUnitSets;
-
- // Give each register unit set an order based on sorting criteria.
- std::vector<unsigned> RegUnitSetOrder;
-
- // Keep track of synthesized definitions generated in TupleExpander.
- std::vector<std::unique_ptr<Record>> SynthDefs;
-
- // Add RC to *2RC maps.
- void addToMaps(CodeGenRegisterClass*);
-
- // Create a synthetic sub-class if it is missing.
- CodeGenRegisterClass *getOrCreateSubClass(const CodeGenRegisterClass *RC,
- const CodeGenRegister::Vec *Membs,
- StringRef Name);
-
- // Infer missing register classes.
- void computeInferredRegisterClasses();
- void inferCommonSubClass(CodeGenRegisterClass *RC);
- void inferSubClassWithSubReg(CodeGenRegisterClass *RC);
-
- void inferMatchingSuperRegClass(CodeGenRegisterClass *RC) {
- inferMatchingSuperRegClass(RC, RegClasses.begin());
- }
-
- void inferMatchingSuperRegClass(
- CodeGenRegisterClass *RC,
- std::list<CodeGenRegisterClass>::iterator FirstSubRegRC);
-
- // Iteratively prune unit sets.
- void pruneUnitSets();
-
- // Compute a weight for each register unit created during getSubRegs.
- void computeRegUnitWeights();
-
- // Create a RegUnitSet for each RegClass and infer superclasses.
- void computeRegUnitSets();
-
- // Populate the Composite map from sub-register relationships.
- void computeComposites();
-
- // Compute a lane mask for each sub-register index.
- void computeSubRegLaneMasks();
-
- /// Computes a lane mask for each register unit enumerated by a physical
- /// register.
- void computeRegUnitLaneMasks();
-
- public:
- CodeGenRegBank(RecordKeeper&, const CodeGenHwModes&);
- CodeGenRegBank(CodeGenRegBank&) = delete;
-
- SetTheory &getSets() { return Sets; }
-
- const CodeGenHwModes &getHwModes() const { return CGH; }
-
- // Sub-register indices. The first NumNamedIndices are defined by the user
- // in the .td files. The rest are synthesized such that all sub-registers
- // have a unique name.
- const std::deque<CodeGenSubRegIndex> &getSubRegIndices() const {
- return SubRegIndices;
- }
-
- // Find a SubRegIndex from its Record def or add to the list if it does
- // not exist there yet.
- CodeGenSubRegIndex *getSubRegIdx(Record*);
-
- // Find a SubRegIndex from its Record def.
- const CodeGenSubRegIndex *findSubRegIdx(const Record* Def) const;
-
- // Find or create a sub-register index representing the A+B composition.
- CodeGenSubRegIndex *getCompositeSubRegIndex(CodeGenSubRegIndex *A,
- CodeGenSubRegIndex *B);
-
- // Find or create a sub-register index representing the concatenation of
- // non-overlapping sibling indices.
- CodeGenSubRegIndex *
- getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8>&);
-
- const std::deque<CodeGenRegister> &getRegisters() const {
- return Registers;
- }
-
- const StringMap<CodeGenRegister *> &getRegistersByName() const {
- return RegistersByName;
- }
-
- // Find a register from its Record def.
- CodeGenRegister *getReg(Record*);
-
- // Get a Register's index into the Registers array.
- unsigned getRegIndex(const CodeGenRegister *Reg) const {
- return Reg->EnumValue - 1;
- }
-
- // Return the number of allocated TopoSigs. The first TopoSig representing
- // leaf registers is allocated number 0.
- unsigned getNumTopoSigs() const {
- return TopoSigs.size();
- }
-
- // Find or create a TopoSig for the given TopoSigId.
- // This function is only for use by CodeGenRegister::computeSuperRegs().
- // Others should simply use Reg->getTopoSig().
- unsigned getTopoSig(const TopoSigId &Id) {
- return TopoSigs.insert(std::make_pair(Id, TopoSigs.size())).first->second;
- }
-
- // Create a native register unit that is associated with one or two root
- // registers.
- unsigned newRegUnit(CodeGenRegister *R0, CodeGenRegister *R1 = nullptr) {
- RegUnits.resize(RegUnits.size() + 1);
- RegUnit &RU = RegUnits.back();
- RU.Roots[0] = R0;
- RU.Roots[1] = R1;
- RU.Artificial = R0->Artificial;
- if (R1)
- RU.Artificial |= R1->Artificial;
- return RegUnits.size() - 1;
- }
-
- // Create a new non-native register unit that can be adopted by a register
- // to increase its pressure. Note that NumNativeRegUnits is not increased.
- unsigned newRegUnit(unsigned Weight) {
- RegUnits.resize(RegUnits.size() + 1);
- RegUnits.back().Weight = Weight;
- return RegUnits.size() - 1;
- }
-
- // Native units are the singular unit of a leaf register. Register aliasing
- // is completely characterized by native units. Adopted units exist to give
- // register additional weight but don't affect aliasing.
- bool isNativeUnit(unsigned RUID) const {
- return RUID < NumNativeRegUnits;
- }
-
- unsigned getNumNativeRegUnits() const {
- return NumNativeRegUnits;
- }
-
- RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; }
- const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; }
-
- std::list<CodeGenRegisterClass> &getRegClasses() { return RegClasses; }
-
- const std::list<CodeGenRegisterClass> &getRegClasses() const {
- return RegClasses;
- }
-
- std::list<CodeGenRegisterCategory> &getRegCategories() {
- return RegCategories;
- }
-
- const std::list<CodeGenRegisterCategory> &getRegCategories() const {
- return RegCategories;
- }
-
- // Find a register class from its def.
- CodeGenRegisterClass *getRegClass(const Record *) const;
-
- /// getRegisterClassForRegister - Find the register class that contains the
- /// specified physical register. If the register is not in a register
- /// class, return null. If the register is in multiple classes, and the
- /// classes have a superset-subset relationship and the same set of types,
- /// return the superclass. Otherwise return null.
- const CodeGenRegisterClass* getRegClassForRegister(Record *R);
-
- // Analog of TargetRegisterInfo::getMinimalPhysRegClass. Unlike
- // getRegClassForRegister, this tries to find the smallest class containing
- // the physical register. If \p VT is specified, it will only find classes
- // with a matching type
- const CodeGenRegisterClass *
- getMinimalPhysRegClass(Record *RegRecord, ValueTypeByHwMode *VT = nullptr);
-
- // Get the sum of unit weights.
- unsigned getRegUnitSetWeight(const std::vector<unsigned> &Units) const {
- unsigned Weight = 0;
- for (unsigned Unit : Units)
- Weight += getRegUnit(Unit).Weight;
- return Weight;
- }
-
- unsigned getRegSetIDAt(unsigned Order) const {
- return RegUnitSetOrder[Order];
- }
-
- const RegUnitSet &getRegSetAt(unsigned Order) const {
- return RegUnitSets[RegUnitSetOrder[Order]];
- }
-
- // Increase a RegUnitWeight.
- void increaseRegUnitWeight(unsigned RUID, unsigned Inc) {
- getRegUnit(RUID).Weight += Inc;
- }
-
- // Get the number of register pressure dimensions.
- unsigned getNumRegPressureSets() const { return RegUnitSets.size(); }
-
- // Get a set of register unit IDs for a given dimension of pressure.
- const RegUnitSet &getRegPressureSet(unsigned Idx) const {
- return RegUnitSets[Idx];
- }
-
- // The number of pressure set lists may be larget than the number of
- // register classes if some register units appeared in a list of sets that
- // did not correspond to an existing register class.
- unsigned getNumRegClassPressureSetLists() const {
- return RegClassUnitSets.size();
- }
-
- // Get a list of pressure set IDs for a register class. Liveness of a
- // register in this class impacts each pressure set in this list by the
- // weight of the register. An exact solution requires all registers in a
- // class to have the same class, but it is not strictly guaranteed.
- ArrayRef<unsigned> getRCPressureSetIDs(unsigned RCIdx) const {
- return RegClassUnitSets[RCIdx];
- }
-
- // Computed derived records such as missing sub-register indices.
- void computeDerivedInfo();
-
- // Compute the set of registers completely covered by the registers in Regs.
- // The returned BitVector will have a bit set for each register in Regs,
- // all sub-registers, and all super-registers that are covered by the
- // registers in Regs.
- //
- // This is used to compute the mask of call-preserved registers from a list
- // of callee-saves.
- BitVector computeCoveredRegisters(ArrayRef<Record*> Regs);
-
- // Bit mask of lanes that cover their registers. A sub-register index whose
- // LaneMask is contained in CoveringLanes will be completely covered by
- // another sub-register with the same or larger lane mask.
- LaneBitmask CoveringLanes;
-
- // Helper function for printing debug information. Handles artificial
- // (non-native) reg units.
- void printRegUnitName(unsigned Unit) const;
- };
-
-} // end namespace llvm
-
-#endif // LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H
diff --git a/llvm/utils/TableGen/AsmWriterInst.cpp b/llvm/utils/TableGen/Common/AsmWriterInst.cpp
similarity index 83%
rename from llvm/utils/TableGen/AsmWriterInst.cpp
rename to llvm/utils/TableGen/Common/AsmWriterInst.cpp
index c9558593e142cd..1fa609e9000514 100644
--- a/llvm/utils/TableGen/AsmWriterInst.cpp
+++ b/llvm/utils/TableGen/Common/AsmWriterInst.cpp
@@ -57,54 +57,55 @@ AsmWriterInst::AsmWriterInst(const CodeGenInstruction &CGI, unsigned CGIIndex,
std::string::size_type LastEmitted = 0;
while (LastEmitted != AsmString.size()) {
std::string::size_type DollarPos =
- AsmString.find_first_of("$\\", LastEmitted);
- if (DollarPos == std::string::npos) DollarPos = AsmString.size();
+ AsmString.find_first_of("$\\", LastEmitted);
+ if (DollarPos == std::string::npos)
+ DollarPos = AsmString.size();
// Emit a constant string fragment.
if (DollarPos != LastEmitted) {
for (; LastEmitted != DollarPos; ++LastEmitted)
switch (AsmString[LastEmitted]) {
- case '\n':
- AddLiteralString("\\n");
- break;
- case '\t':
- AddLiteralString("\\t");
- break;
- case '"':
- AddLiteralString("\\\"");
- break;
- case '\\':
- AddLiteralString("\\\\");
- break;
- default:
- AddLiteralString(std::string(1, AsmString[LastEmitted]));
- break;
+ case '\n':
+ AddLiteralString("\\n");
+ break;
+ case '\t':
+ AddLiteralString("\\t");
+ break;
+ case '"':
+ AddLiteralString("\\\"");
+ break;
+ case '\\':
+ AddLiteralString("\\\\");
+ break;
+ default:
+ AddLiteralString(std::string(1, AsmString[LastEmitted]));
+ break;
}
} else if (AsmString[DollarPos] == '\\') {
- if (DollarPos+1 != AsmString.size()) {
- if (AsmString[DollarPos+1] == 'n') {
+ if (DollarPos + 1 != AsmString.size()) {
+ if (AsmString[DollarPos + 1] == 'n') {
AddLiteralString("\\n");
- } else if (AsmString[DollarPos+1] == 't') {
+ } else if (AsmString[DollarPos + 1] == 't') {
AddLiteralString("\\t");
- } else if (std::string("${|}\\").find(AsmString[DollarPos+1])
- != std::string::npos) {
- AddLiteralString(std::string(1, AsmString[DollarPos+1]));
+ } else if (std::string("${|}\\").find(AsmString[DollarPos + 1]) !=
+ std::string::npos) {
+ AddLiteralString(std::string(1, AsmString[DollarPos + 1]));
} else {
PrintFatalError(
CGI.TheDef->getLoc(),
"Non-supported escaped character found in instruction '" +
CGI.TheDef->getName() + "'!");
}
- LastEmitted = DollarPos+2;
+ LastEmitted = DollarPos + 2;
continue;
}
- } else if (DollarPos+1 != AsmString.size() &&
- AsmString[DollarPos+1] == '$') {
- AddLiteralString("$"); // "$$" -> $
- LastEmitted = DollarPos+2;
+ } else if (DollarPos + 1 != AsmString.size() &&
+ AsmString[DollarPos + 1] == '$') {
+ AddLiteralString("$"); // "$$" -> $
+ LastEmitted = DollarPos + 2;
} else {
// Get the name of the variable.
- std::string::size_type VarEnd = DollarPos+1;
+ std::string::size_type VarEnd = DollarPos + 1;
// handle ${foo}bar as $foo by detecting whether the character following
// the dollar sign is a curly brace. If so, advance VarEnd and DollarPos
@@ -118,7 +119,8 @@ AsmWriterInst::AsmWriterInst(const CodeGenInstruction &CGI, unsigned CGIIndex,
while (VarEnd < AsmString.size() && isIdentChar(AsmString[VarEnd]))
++VarEnd;
- StringRef VarName(AsmString.data()+DollarPos+1, VarEnd-DollarPos-1);
+ StringRef VarName(AsmString.data() + DollarPos + 1,
+ VarEnd - DollarPos - 1);
// Modifier - Support ${foo:modifier} syntax, where "modifier" is passed
// into printOperand. Also support ${:feature}, which is passed into
@@ -190,13 +192,14 @@ AsmWriterInst::AsmWriterInst(const CodeGenInstruction &CGI, unsigned CGIIndex,
/// specified instruction except for one differing operand, return the differing
/// operand number. If more than one operand mismatches, return ~1, otherwise
/// if the instructions are identical return ~0.
-unsigned AsmWriterInst::MatchesAllButOneOp(const AsmWriterInst &Other)const{
- if (Operands.size() != Other.Operands.size()) return ~1;
+unsigned AsmWriterInst::MatchesAllButOneOp(const AsmWriterInst &Other) const {
+ if (Operands.size() != Other.Operands.size())
+ return ~1;
unsigned MismatchOperand = ~0U;
for (unsigned i = 0, e = Operands.size(); i != e; ++i) {
if (Operands[i] != Other.Operands[i]) {
- if (MismatchOperand != ~0U) // Already have one mismatch?
+ if (MismatchOperand != ~0U) // Already have one mismatch?
return ~1U;
MismatchOperand = i;
}
diff --git a/llvm/utils/TableGen/Common/AsmWriterInst.h b/llvm/utils/TableGen/Common/AsmWriterInst.h
new file mode 100644
index 00000000000000..f0ebf799d91051
--- /dev/null
+++ b/llvm/utils/TableGen/Common/AsmWriterInst.h
@@ -0,0 +1,107 @@
+//===- AsmWriterInst.h - Classes encapsulating a printable inst -*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// These classes implement a parser for assembly strings. The parser splits
+// the string into operands, which can be literal strings (the constant bits of
+// the string), actual operands (i.e., operands from the MachineInstr), and
+// dynamically-generated text, specified by raw C++ code.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_UTILS_TABLEGEN_ASMWRITERINST_H
+#define LLVM_UTILS_TABLEGEN_ASMWRITERINST_H
+
+#include <string>
+#include <vector>
+
+namespace llvm {
+class CodeGenInstruction;
+
+struct AsmWriterOperand {
+ enum OpType {
+ // Output this text surrounded by quotes to the asm.
+ isLiteralTextOperand,
+ // This is the name of a routine to call to print the operand.
+ isMachineInstrOperand,
+ // Output this text verbatim to the asm writer. It is code that
+ // will output some text to the asm.
+ isLiteralStatementOperand
+ } OperandType;
+
+ /// MiOpNo - For isMachineInstrOperand, this is the operand number of the
+ /// machine instruction.
+ unsigned MIOpNo = 0;
+
+ /// Str - For isLiteralTextOperand, this IS the literal text. For
+ /// isMachineInstrOperand, this is the PrinterMethodName for the operand..
+ /// For isLiteralStatementOperand, this is the code to insert verbatim
+ /// into the asm writer.
+ std::string Str;
+
+ /// MiModifier - For isMachineInstrOperand, this is the modifier string for
+ /// an operand, specified with syntax like ${opname:modifier}.
+ std::string MiModifier;
+
+ bool PCRel = false;
+
+ // To make VS STL happy
+ AsmWriterOperand(OpType op = isLiteralTextOperand) : OperandType(op) {}
+
+ AsmWriterOperand(const std::string &LitStr, OpType op = isLiteralTextOperand)
+ : OperandType(op), Str(LitStr) {}
+
+ AsmWriterOperand(const std::string &Printer, unsigned _MIOpNo,
+ const std::string &Modifier,
+ OpType op = isMachineInstrOperand, bool PCRel = false)
+ : OperandType(op), MIOpNo(_MIOpNo), Str(Printer), MiModifier(Modifier),
+ PCRel(PCRel) {}
+
+ bool operator!=(const AsmWriterOperand &Other) const {
+ if (OperandType != Other.OperandType || Str != Other.Str)
+ return true;
+ if (OperandType == isMachineInstrOperand)
+ return MIOpNo != Other.MIOpNo || MiModifier != Other.MiModifier ||
+ PCRel != Other.PCRel;
+ return false;
+ }
+ bool operator==(const AsmWriterOperand &Other) const {
+ return !operator!=(Other);
+ }
+
+ /// getCode - Return the code that prints this operand.
+ std::string getCode(bool PassSubtarget) const;
+};
+
+class AsmWriterInst {
+public:
+ std::vector<AsmWriterOperand> Operands;
+ const CodeGenInstruction *CGI;
+ unsigned CGIIndex;
+
+ AsmWriterInst(const CodeGenInstruction &CGI, unsigned CGIIndex,
+ unsigned Variant);
+
+ /// MatchesAllButOneOp - If this instruction is exactly identical to the
+ /// specified instruction except for one differing operand, return the
+ /// differing operand number. Otherwise return ~0.
+ unsigned MatchesAllButOneOp(const AsmWriterInst &Other) const;
+
+private:
+ void AddLiteralString(const std::string &Str) {
+ // If the last operand was already a literal text string, append this to
+ // it, otherwise add a new operand.
+ if (!Operands.empty() &&
+ Operands.back().OperandType == AsmWriterOperand::isLiteralTextOperand)
+ Operands.back().Str.append(Str);
+ else
+ Operands.push_back(AsmWriterOperand(Str));
+ }
+};
+} // namespace llvm
+
+#endif
diff --git a/llvm/utils/TableGen/Common/CMakeLists.txt b/llvm/utils/TableGen/Common/CMakeLists.txt
new file mode 100644
index 00000000000000..491d9bd2949dce
--- /dev/null
+++ b/llvm/utils/TableGen/Common/CMakeLists.txt
@@ -0,0 +1,48 @@
+# The common library is similar to the basic library except it can
+# depend on vt_gen.
+#
+# This library contains the bulk of the supporting code for all
+# TableGen backends. It's split off as a separate library to
+# allow unit-testing those components.
+
+set(LLVM_LINK_COMPONENTS
+ Support
+ TableGen
+ )
+
+add_llvm_library(LLVMTableGenCommon STATIC OBJECT EXCLUDE_FROM_ALL
+ GlobalISel/CodeExpander.cpp
+ GlobalISel/CXXPredicates.cpp
+ GlobalISel/GlobalISelMatchTable.cpp
+ GlobalISel/GlobalISelMatchTableExecutorEmitter.cpp
+ GlobalISel/MatchDataInfo.cpp
+ GlobalISel/Patterns.cpp
+
+ AsmWriterInst.cpp
+ CodeGenDAGPatterns.cpp
+ CodeGenHwModes.cpp
+ CodeGenInstAlias.cpp
+ CodeGenInstruction.cpp
+ CodeGenRegisters.cpp
+ CodeGenSchedule.cpp
+ CodeGenTarget.cpp
+ DAGISelMatcher.cpp
+ InfoByHwMode.cpp
+ OptEmitter.cpp
+ PredicateExpander.cpp
+ SubtargetFeatureInfo.cpp
+ Types.cpp
+ VarLenCodeEmitterGen.cpp
+ $<TARGET_OBJECTS:obj.LLVMTableGenBasic>
+
+ DEPENDS
+ vt_gen
+ )
+set_target_properties(LLVMTableGenCommon PROPERTIES FOLDER "Tablegenning")
+target_link_libraries(LLVMTableGenCommon PUBLIC LLVMTableGenBasic)
+
+# Users may include its headers as "Common/*.h"
+target_include_directories(LLVMTableGenCommon
+ PUBLIC
+ $<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/..>
+ )
diff --git a/llvm/utils/TableGen/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
similarity index 92%
rename from llvm/utils/TableGen/CodeGenDAGPatterns.cpp
rename to llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
index f88e25ea1d167d..62e048216e79c7 100644
--- a/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
@@ -38,18 +38,10 @@ using namespace llvm;
static inline bool isIntegerOrPtr(MVT VT) {
return VT.isInteger() || VT == MVT::iPTR;
}
-static inline bool isFloatingPoint(MVT VT) {
- return VT.isFloatingPoint();
-}
-static inline bool isVector(MVT VT) {
- return VT.isVector();
-}
-static inline bool isScalar(MVT VT) {
- return !VT.isVector();
-}
-static inline bool isScalarInteger(MVT VT) {
- return VT.isScalarInteger();
-}
+static inline bool isFloatingPoint(MVT VT) { return VT.isFloatingPoint(); }
+static inline bool isVector(MVT VT) { return VT.isVector(); }
+static inline bool isScalar(MVT VT) { return !VT.isVector(); }
+static inline bool isScalarInteger(MVT VT) { return VT.isScalarInteger(); }
template <typename Predicate>
static bool berase_if(MachineValueTypeSet &S, Predicate P) {
@@ -173,8 +165,7 @@ bool TypeSetByHwMode::constrain(const TypeSetByHwMode &VTS) {
return Changed;
}
-template <typename Predicate>
-bool TypeSetByHwMode::constrain(Predicate P) {
+template <typename Predicate> bool TypeSetByHwMode::constrain(Predicate P) {
bool Changed = false;
for (auto &I : *this)
Changed |= berase_if(I.second, [&P](MVT VT) { return !P(VT); });
@@ -257,20 +248,18 @@ bool TypeSetByHwMode::operator==(const TypeSetByHwMode &VTS) const {
}
namespace llvm {
- raw_ostream &operator<<(raw_ostream &OS, const MachineValueTypeSet &T) {
- T.writeToStream(OS);
- return OS;
- }
- raw_ostream &operator<<(raw_ostream &OS, const TypeSetByHwMode &T) {
- T.writeToStream(OS);
- return OS;
- }
+raw_ostream &operator<<(raw_ostream &OS, const MachineValueTypeSet &T) {
+ T.writeToStream(OS);
+ return OS;
+}
+raw_ostream &operator<<(raw_ostream &OS, const TypeSetByHwMode &T) {
+ T.writeToStream(OS);
+ return OS;
}
+} // namespace llvm
LLVM_DUMP_METHOD
-void TypeSetByHwMode::dump() const {
- dbgs() << *this << '\n';
-}
+void TypeSetByHwMode::dump() const { dbgs() << *this << '\n'; }
bool TypeSetByHwMode::intersect(SetType &Out, const SetType &In) {
bool OutP = Out.count(MVT::iPTR), InP = In.count(MVT::iPTR);
@@ -335,7 +324,7 @@ bool TypeSetByHwMode::intersect(SetType &Out, const SetType &In) {
// OutP == true
SetType InOnly = subtract(In, Out);
unsigned SizeOut = Out.size();
- berase_if(Out, CompIn); // This will remove at least the iPTR.
+ berase_if(Out, CompIn); // This will remove at least the iPTR.
unsigned NumI = llvm::count_if(InOnly, isScalarInteger);
if (NumI == 0) {
// iPTR deleted from Out.
@@ -568,29 +557,29 @@ bool TypeInfer::EnforceSmallerThan(TypeSetByHwMode &Small, TypeSetByHwMode &Big,
// smaller-or-equal than MinS.
auto MinS = min_if(S.begin(), S.end(), isScalar, LT);
if (MinS != S.end())
- Changed |= berase_if(B, std::bind(SameKindLE,
- std::placeholders::_1, *MinS));
+ Changed |=
+ berase_if(B, std::bind(SameKindLE, std::placeholders::_1, *MinS));
// MaxS = max scalar in Big, remove all scalars from Small that are
// larger than MaxS.
auto MaxS = max_if(B.begin(), B.end(), isScalar, LT);
if (MaxS != B.end())
- Changed |= berase_if(S, std::bind(SameKindLE,
- *MaxS, std::placeholders::_1));
+ Changed |=
+ berase_if(S, std::bind(SameKindLE, *MaxS, std::placeholders::_1));
// MinV = min vector in Small, remove all vectors from Big that are
// smaller-or-equal than MinV.
auto MinV = min_if(S.begin(), S.end(), isVector, LT);
if (MinV != S.end())
- Changed |= berase_if(B, std::bind(SameKindLE,
- std::placeholders::_1, *MinV));
+ Changed |=
+ berase_if(B, std::bind(SameKindLE, std::placeholders::_1, *MinV));
// MaxV = max vector in Big, remove all vectors from Small that are
// larger than MaxV.
auto MaxV = max_if(B.begin(), B.end(), isVector, LT);
if (MaxV != B.end())
- Changed |= berase_if(S, std::bind(SameKindLE,
- *MaxV, std::placeholders::_1));
+ Changed |=
+ berase_if(S, std::bind(SameKindLE, *MaxV, std::placeholders::_1));
}
return Changed;
@@ -618,8 +607,8 @@ bool TypeInfer::EnforceVectorEltTypeIs(TypeSetByHwMode &Vec,
TypeSetByHwMode::SetType &V = Vec.get(M);
TypeSetByHwMode::SetType &E = Elem.get(M);
- Changed |= berase_if(V, isScalar); // Scalar = !vector
- Changed |= berase_if(E, isVector); // Vector = !scalar
+ Changed |= berase_if(V, isScalar); // Scalar = !vector
+ Changed |= berase_if(E, isVector); // Vector = !scalar
assert(!V.empty() && !E.empty());
MachineValueTypeSet VT, ST;
@@ -632,8 +621,8 @@ bool TypeInfer::EnforceVectorEltTypeIs(TypeSetByHwMode &Vec,
// Remove from V all (vector) types whose element type is not in S.
Changed |= berase_if(V, [&ST](MVT T) -> bool {
- return !ST.count(T.getVectorElementType());
- });
+ return !ST.count(T.getVectorElementType());
+ });
// Remove from E all (scalar) types, for which there is no corresponding
// type in V.
Changed |= berase_if(E, [&VT](MVT T) -> bool { return !VT.count(T); });
@@ -887,7 +876,6 @@ TypeInfer::ValidateOnExit::~ValidateOnExit() {
}
}
-
//===----------------------------------------------------------------------===//
// ScopedName Implementation
//===----------------------------------------------------------------------===//
@@ -896,10 +884,7 @@ bool ScopedName::operator==(const ScopedName &o) const {
return Scope == o.Scope && Identifier == o.Identifier;
}
-bool ScopedName::operator!=(const ScopedName &o) const {
- return !(*this == o);
-}
-
+bool ScopedName::operator!=(const ScopedName &o) const { return !(*this == o); }
//===----------------------------------------------------------------------===//
// TreePredicateFn Implementation
@@ -1011,8 +996,9 @@ std::string TreePredicateFn::getPredCode() const {
PrintFatalError(getOrigPatFragRecord()->getRecord()->getLoc(),
"IsAtomicOrderingAcquireRelease requires IsAtomic");
if (isAtomicOrderingSequentiallyConsistent())
- PrintFatalError(getOrigPatFragRecord()->getRecord()->getLoc(),
- "IsAtomicOrderingSequentiallyConsistent requires IsAtomic");
+ PrintFatalError(
+ getOrigPatFragRecord()->getRecord()->getLoc(),
+ "IsAtomicOrderingSequentiallyConsistent requires IsAtomic");
if (isAtomicOrderingAcquireOrStronger())
PrintFatalError(getOrigPatFragRecord()->getRecord()->getLoc(),
"IsAtomicOrderingAcquireOrStronger requires IsAtomic");
@@ -1027,7 +1013,7 @@ std::string TreePredicateFn::getPredCode() const {
if (isLoad() || isStore() || isAtomic()) {
if (ListInit *AddressSpaces = getAddressSpaces()) {
Code += "unsigned AddrSpace = cast<MemSDNode>(N)->getAddressSpace();\n"
- " if (";
+ " if (";
ListSeparator LS(" && ");
for (Init *Val : AddressSpaces->getValues()) {
@@ -1077,18 +1063,22 @@ std::string TreePredicateFn::getPredCode() const {
"AtomicOrdering::SequentiallyConsistent) return false;\n";
if (isAtomic() && isAtomicOrderingAcquireOrStronger())
- Code += "if (!isAcquireOrStronger(cast<AtomicSDNode>(N)->getMergedOrdering())) "
- "return false;\n";
+ Code +=
+ "if (!isAcquireOrStronger(cast<AtomicSDNode>(N)->getMergedOrdering())) "
+ "return false;\n";
if (isAtomic() && isAtomicOrderingWeakerThanAcquire())
- Code += "if (isAcquireOrStronger(cast<AtomicSDNode>(N)->getMergedOrdering())) "
- "return false;\n";
+ Code +=
+ "if (isAcquireOrStronger(cast<AtomicSDNode>(N)->getMergedOrdering())) "
+ "return false;\n";
if (isAtomic() && isAtomicOrderingReleaseOrStronger())
- Code += "if (!isReleaseOrStronger(cast<AtomicSDNode>(N)->getMergedOrdering())) "
- "return false;\n";
+ Code +=
+ "if (!isReleaseOrStronger(cast<AtomicSDNode>(N)->getMergedOrdering())) "
+ "return false;\n";
if (isAtomic() && isAtomicOrderingWeakerThanRelease())
- Code += "if (isReleaseOrStronger(cast<AtomicSDNode>(N)->getMergedOrdering())) "
- "return false;\n";
+ Code +=
+ "if (isReleaseOrStronger(cast<AtomicSDNode>(N)->getMergedOrdering())) "
+ "return false;\n";
// TODO: Handle atomic sextload/zextload normally when ATOMIC_LOAD is removed.
if (isAtomic() && (isZeroExtLoad() || isSignExtLoad()))
@@ -1239,16 +1229,20 @@ bool TreePredicateFn::isAtomicOrderingSequentiallyConsistent() const {
true);
}
bool TreePredicateFn::isAtomicOrderingAcquireOrStronger() const {
- return isPredefinedPredicateEqualTo("IsAtomicOrderingAcquireOrStronger", true);
+ return isPredefinedPredicateEqualTo("IsAtomicOrderingAcquireOrStronger",
+ true);
}
bool TreePredicateFn::isAtomicOrderingWeakerThanAcquire() const {
- return isPredefinedPredicateEqualTo("IsAtomicOrderingAcquireOrStronger", false);
+ return isPredefinedPredicateEqualTo("IsAtomicOrderingAcquireOrStronger",
+ false);
}
bool TreePredicateFn::isAtomicOrderingReleaseOrStronger() const {
- return isPredefinedPredicateEqualTo("IsAtomicOrderingReleaseOrStronger", true);
+ return isPredefinedPredicateEqualTo("IsAtomicOrderingReleaseOrStronger",
+ true);
}
bool TreePredicateFn::isAtomicOrderingWeakerThanRelease() const {
- return isPredefinedPredicateEqualTo("IsAtomicOrderingReleaseOrStronger", false);
+ return isPredefinedPredicateEqualTo("IsAtomicOrderingReleaseOrStronger",
+ false);
}
Record *TreePredicateFn::getMemoryVT() const {
Record *R = getOrigPatFragRecord()->getRecord();
@@ -1428,7 +1422,7 @@ static bool isImmAllOnesAllZerosMatch(const TreePatternNode *P) {
/// pattern.
static unsigned getPatternSize(const TreePatternNode *P,
const CodeGenDAGPatterns &CGP) {
- unsigned Size = 3; // The node itself.
+ unsigned Size = 3; // The node itself.
// If the root node is a ConstantSDNode, increases its size.
// e.g. (set R32:$dst, 0).
if (P->isLeaf() && isa<IntInit>(P->getLeafValue()))
@@ -1459,7 +1453,7 @@ static unsigned getPatternSize(const TreePatternNode *P,
}
if (Child->isLeaf()) {
if (isa<IntInit>(Child->getLeafValue()))
- Size += 5; // Matches a ConstantSDNode (+3) and a specific value (+2).
+ Size += 5; // Matches a ConstantSDNode (+3) and a specific value (+2).
else if (Child->getComplexPatternInfo(CGP))
Size += getPatternSize(Child, CGP);
else if (isImmAllOnesAllZerosMatch(Child))
@@ -1474,8 +1468,7 @@ static unsigned getPatternSize(const TreePatternNode *P,
/// Compute the complexity metric for the input pattern. This roughly
/// corresponds to the number of nodes that are covered.
-int PatternToMatch::
-getPatternComplexity(const CodeGenDAGPatterns &CGP) const {
+int PatternToMatch::getPatternComplexity(const CodeGenDAGPatterns &CGP) const {
return getPatternSize(getSrcPattern(), CGP) + getAddedComplexity();
}
@@ -1550,18 +1543,17 @@ SDTypeConstraint::SDTypeConstraint(Record *R, const CodeGenHwModes &CGH) {
} else if (R->isSubClassOf("SDTCisVTSmallerThanOp")) {
ConstraintType = SDTCisVTSmallerThanOp;
x.SDTCisVTSmallerThanOp_Info.OtherOperandNum =
- R->getValueAsInt("OtherOperandNum");
+ R->getValueAsInt("OtherOperandNum");
} else if (R->isSubClassOf("SDTCisOpSmallerThanOp")) {
ConstraintType = SDTCisOpSmallerThanOp;
x.SDTCisOpSmallerThanOp_Info.BigOperandNum =
- R->getValueAsInt("BigOperandNum");
+ R->getValueAsInt("BigOperandNum");
} else if (R->isSubClassOf("SDTCisEltOfVec")) {
ConstraintType = SDTCisEltOfVec;
x.SDTCisEltOfVec_Info.OtherOperandNum = R->getValueAsInt("OtherOpNum");
} else if (R->isSubClassOf("SDTCisSubVecOfVec")) {
ConstraintType = SDTCisSubVecOfVec;
- x.SDTCisSubVecOfVec_Info.OtherOperandNum =
- R->getValueAsInt("OtherOpNum");
+ x.SDTCisSubVecOfVec_Info.OtherOperandNum = R->getValueAsInt("OtherOpNum");
} else if (R->isSubClassOf("SDTCVecEltisVT")) {
ConstraintType = SDTCVecEltisVT;
VVT = getValueTypeByHwMode(R->getValueAsDef("VT"), CGH);
@@ -1577,11 +1569,11 @@ SDTypeConstraint::SDTypeConstraint(Record *R, const CodeGenHwModes &CGH) {
} else if (R->isSubClassOf("SDTCisSameNumEltsAs")) {
ConstraintType = SDTCisSameNumEltsAs;
x.SDTCisSameNumEltsAs_Info.OtherOperandNum =
- R->getValueAsInt("OtherOperandNum");
+ R->getValueAsInt("OtherOperandNum");
} else if (R->isSubClassOf("SDTCisSameSizeAs")) {
ConstraintType = SDTCisSameSizeAs;
x.SDTCisSameSizeAs_Info.OtherOperandNum =
- R->getValueAsInt("OtherOperandNum");
+ R->getValueAsInt("OtherOperandNum");
} else {
PrintFatalError(R->getLoc(),
"Unrecognized SDTypeConstraint '" + R->getName() + "'!\n");
@@ -1604,8 +1596,8 @@ static TreePatternNode *getOperandNum(unsigned OpNo, TreePatternNode *N,
if (OpNo >= N->getNumChildren()) {
std::string S;
raw_string_ostream OS(S);
- OS << "Invalid operand number in type constraint "
- << (OpNo+NumResults) << " ";
+ OS << "Invalid operand number in type constraint " << (OpNo + NumResults)
+ << " ";
N->print(OS);
PrintFatalError(S);
}
@@ -1635,7 +1627,7 @@ bool SDTypeConstraint::ApplyTypeConstraint(TreePatternNode *N,
return NodeToApply->UpdateNodeType(ResNo, MVT::iPTR, TP);
case SDTCisInt:
// Require it to be one of the legal integer VTs.
- return TI.EnforceInteger(NodeToApply->getExtType(ResNo));
+ return TI.EnforceInteger(NodeToApply->getExtType(ResNo));
case SDTCisFP:
// Require it to be one of the legal fp VTs.
return TI.EnforceFloatingPoint(NodeToApply->getExtType(ResNo));
@@ -1645,7 +1637,7 @@ bool SDTypeConstraint::ApplyTypeConstraint(TreePatternNode *N,
case SDTCisSameAs: {
unsigned OResNo = 0;
TreePatternNode *OtherNode =
- getOperandNum(x.SDTCisSameAs_Info.OtherOperandNum, N, NodeInfo, OResNo);
+ getOperandNum(x.SDTCisSameAs_Info.OtherOperandNum, N, NodeInfo, OResNo);
return (int)NodeToApply->UpdateNodeType(ResNo,
OtherNode->getExtType(OResNo), TP) |
(int)OtherNode->UpdateNodeType(OResNo,
@@ -1654,10 +1646,10 @@ bool SDTypeConstraint::ApplyTypeConstraint(TreePatternNode *N,
case SDTCisVTSmallerThanOp: {
// The NodeToApply must be a leaf node that is a VT. OtherOperandNum must
// have an integer type that is smaller than the VT.
- if (!NodeToApply->isLeaf() ||
- !isa<DefInit>(NodeToApply->getLeafValue()) ||
- !cast<DefInit>(NodeToApply->getLeafValue())->getDef()
- ->isSubClassOf("ValueType")) {
+ if (!NodeToApply->isLeaf() || !isa<DefInit>(NodeToApply->getLeafValue()) ||
+ !cast<DefInit>(NodeToApply->getLeafValue())
+ ->getDef()
+ ->isSubClassOf("ValueType")) {
TP.error(N->getOperator()->getName() + " expects a VT operand!");
return false;
}
@@ -1667,26 +1659,23 @@ bool SDTypeConstraint::ApplyTypeConstraint(TreePatternNode *N,
TypeSetByHwMode TypeListTmp(VVT);
unsigned OResNo = 0;
- TreePatternNode *OtherNode =
- getOperandNum(x.SDTCisVTSmallerThanOp_Info.OtherOperandNum, N, NodeInfo,
- OResNo);
+ TreePatternNode *OtherNode = getOperandNum(
+ x.SDTCisVTSmallerThanOp_Info.OtherOperandNum, N, NodeInfo, OResNo);
return TI.EnforceSmallerThan(TypeListTmp, OtherNode->getExtType(OResNo),
/*SmallIsVT*/ true);
}
case SDTCisOpSmallerThanOp: {
unsigned BResNo = 0;
- TreePatternNode *BigOperand =
- getOperandNum(x.SDTCisOpSmallerThanOp_Info.BigOperandNum, N, NodeInfo,
- BResNo);
+ TreePatternNode *BigOperand = getOperandNum(
+ x.SDTCisOpSmallerThanOp_Info.BigOperandNum, N, NodeInfo, BResNo);
return TI.EnforceSmallerThan(NodeToApply->getExtType(ResNo),
BigOperand->getExtType(BResNo));
}
case SDTCisEltOfVec: {
unsigned VResNo = 0;
- TreePatternNode *VecOperand =
- getOperandNum(x.SDTCisEltOfVec_Info.OtherOperandNum, N, NodeInfo,
- VResNo);
+ TreePatternNode *VecOperand = getOperandNum(
+ x.SDTCisEltOfVec_Info.OtherOperandNum, N, NodeInfo, VResNo);
// Filter vector types out of VecOperand that don't have the right element
// type.
return TI.EnforceVectorEltTypeIs(VecOperand->getExtType(VResNo),
@@ -1694,9 +1683,8 @@ bool SDTypeConstraint::ApplyTypeConstraint(TreePatternNode *N,
}
case SDTCisSubVecOfVec: {
unsigned VResNo = 0;
- TreePatternNode *BigVecOperand =
- getOperandNum(x.SDTCisSubVecOfVec_Info.OtherOperandNum, N, NodeInfo,
- VResNo);
+ TreePatternNode *BigVecOperand = getOperandNum(
+ x.SDTCisSubVecOfVec_Info.OtherOperandNum, N, NodeInfo, VResNo);
// Filter vector types out of BigVecOperand that don't have the
// right subvector type.
@@ -1708,17 +1696,15 @@ bool SDTypeConstraint::ApplyTypeConstraint(TreePatternNode *N,
}
case SDTCisSameNumEltsAs: {
unsigned OResNo = 0;
- TreePatternNode *OtherNode =
- getOperandNum(x.SDTCisSameNumEltsAs_Info.OtherOperandNum,
- N, NodeInfo, OResNo);
+ TreePatternNode *OtherNode = getOperandNum(
+ x.SDTCisSameNumEltsAs_Info.OtherOperandNum, N, NodeInfo, OResNo);
return TI.EnforceSameNumElts(OtherNode->getExtType(OResNo),
NodeToApply->getExtType(ResNo));
}
case SDTCisSameSizeAs: {
unsigned OResNo = 0;
- TreePatternNode *OtherNode =
- getOperandNum(x.SDTCisSameSizeAs_Info.OtherOperandNum,
- N, NodeInfo, OResNo);
+ TreePatternNode *OtherNode = getOperandNum(
+ x.SDTCisSameSizeAs_Info.OtherOperandNum, N, NodeInfo, OResNo);
return TI.EnforceSameSize(OtherNode->getExtType(OResNo),
NodeToApply->getExtType(ResNo));
}
@@ -1729,8 +1715,7 @@ bool SDTypeConstraint::ApplyTypeConstraint(TreePatternNode *N,
// Update the node type to match an instruction operand or result as specified
// in the ins or outs lists on the instruction definition. Return true if the
// type was actually changed.
-bool TreePatternNode::UpdateNodeTypeFromInst(unsigned ResNo,
- Record *Operand,
+bool TreePatternNode::UpdateNodeTypeFromInst(unsigned ResNo, Record *Operand,
TreePattern &TP) {
// The 'unknown' operand indicates that types should be inferred from the
// context.
@@ -1808,7 +1793,7 @@ bool TreePatternNode::setDefaultMode(unsigned Mode) {
// SDNodeInfo implementation
//
SDNodeInfo::SDNodeInfo(Record *R, const CodeGenHwModes &CGH) : Def(R) {
- EnumName = R->getValueAsString("Opcode");
+ EnumName = R->getValueAsString("Opcode");
SDClassName = R->getValueAsString("SDClass");
Record *TypeProfile = R->getValueAsDef("TypeProfile");
NumResults = TypeProfile->getValueAsInt("NumResults");
@@ -1818,8 +1803,8 @@ SDNodeInfo::SDNodeInfo(Record *R, const CodeGenHwModes &CGH) : Def(R) {
Properties = parseSDPatternOperatorProperties(R);
// Parse the type constraints.
- std::vector<Record*> ConstraintList =
- TypeProfile->getValueAsListOfDefs("Constraints");
+ std::vector<Record *> ConstraintList =
+ TypeProfile->getValueAsListOfDefs("Constraints");
for (Record *R : ConstraintList)
TypeConstraints.emplace_back(R, CGH);
}
@@ -1835,11 +1820,12 @@ MVT::SimpleValueType SDNodeInfo::getKnownType(unsigned ResNo) const {
for (const SDTypeConstraint &Constraint : TypeConstraints) {
// Make sure that this applies to the correct node result.
- if (Constraint.OperandNo >= NumResults) // FIXME: need value #
+ if (Constraint.OperandNo >= NumResults) // FIXME: need value #
continue;
switch (Constraint.ConstraintType) {
- default: break;
+ default:
+ break;
case SDTypeConstraint::SDTCisVT:
if (Constraint.VVT.isSimple())
return Constraint.VVT.getSimple().SimpleTy;
@@ -1856,9 +1842,8 @@ MVT::SimpleValueType SDNodeInfo::getKnownType(unsigned ResNo) const {
//
static unsigned GetNumNodeResults(Record *Operator, CodeGenDAGPatterns &CDP) {
- if (Operator->getName() == "set" ||
- Operator->getName() == "implicit")
- return 0; // All return nothing.
+ if (Operator->getName() == "set" || Operator->getName() == "implicit")
+ return 0; // All return nothing.
if (Operator->isSubClassOf("Intrinsic"))
return CDP.getIntrinsic(Operator).IS.RetTys.size();
@@ -1908,16 +1893,17 @@ static unsigned GetNumNodeResults(Record *Operator, CodeGenDAGPatterns &CDP) {
}
// Add on one implicit def if it has a resolvable type.
- if (InstInfo.HasOneImplicitDefWithKnownVT(CDP.getTargetInfo()) !=MVT::Other)
+ if (InstInfo.HasOneImplicitDefWithKnownVT(CDP.getTargetInfo()) !=
+ MVT::Other)
++NumDefsToAdd;
return NumDefsToAdd;
}
if (Operator->isSubClassOf("SDNodeXForm"))
- return 1; // FIXME: Generalize SDNodeXForm
+ return 1; // FIXME: Generalize SDNodeXForm
if (Operator->isSubClassOf("ValueType"))
- return 1; // A type-cast of one result.
+ return 1; // A type-cast of one result.
if (Operator->isSubClassOf("ComplexPattern"))
return 1;
@@ -1963,9 +1949,7 @@ void TreePatternNode::print(raw_ostream &OS) const {
for (const ScopedName &Name : NamesAsPredicateArg)
OS << ":$pred:" << Name.getScope() << ":" << Name.getIdentifier();
}
-void TreePatternNode::dump() const {
- print(errs());
-}
+void TreePatternNode::dump() const { print(errs()); }
/// isIsomorphicTo - Return true if this node is recursively
/// isomorphic to the specified node. For this comparison, the node's
@@ -1976,7 +1960,8 @@ void TreePatternNode::dump() const {
/// isomorphic if the names match.
bool TreePatternNode::isIsomorphicTo(const TreePatternNode *N,
const MultipleUseVarSet &DepVars) const {
- if (N == this) return true;
+ if (N == this)
+ return true;
if (N->isLeaf() != isLeaf())
return false;
@@ -2035,17 +2020,18 @@ TreePatternNodePtr TreePatternNode::clone() const {
void TreePatternNode::RemoveAllTypes() {
// Reset to unknown type.
std::fill(Types.begin(), Types.end(), TypeSetByHwMode());
- if (isLeaf()) return;
+ if (isLeaf())
+ return;
for (unsigned i = 0, e = getNumChildren(); i != e; ++i)
getChild(i)->RemoveAllTypes();
}
-
/// SubstituteFormalArguments - Replace the formal arguments in this tree
/// with actual values specified by ArgMap.
void TreePatternNode::SubstituteFormalArguments(
std::map<std::string, TreePatternNodePtr> &ArgMap) {
- if (isLeaf()) return;
+ if (isLeaf())
+ return;
for (unsigned i = 0, e = getNumChildren(); i != e; ++i) {
TreePatternNode *Child = getChild(i);
@@ -2053,8 +2039,9 @@ void TreePatternNode::SubstituteFormalArguments(
Init *Val = Child->getLeafValue();
// Note that, when substituting into an output pattern, Val might be an
// UnsetInit.
- if (isa<UnsetInit>(Val) || (isa<DefInit>(Val) &&
- cast<DefInit>(Val)->getDef()->getName() == "node")) {
+ if (isa<UnsetInit>(Val) ||
+ (isa<DefInit>(Val) &&
+ cast<DefInit>(Val)->getDef()->getName() == "node")) {
// We found a use of a formal argument, replace it with its value.
TreePatternNodePtr NewChild = ArgMap[Child->getName()];
assert(NewChild && "Couldn't find formal argument!");
@@ -2069,7 +2056,6 @@ void TreePatternNode::SubstituteFormalArguments(
}
}
-
/// InlinePatternFragments - If this pattern refers to any pattern
/// fragments, return the set of inlined versions (this can be more than
/// one if a PatFrags record has multiple alternatives).
@@ -2205,7 +2191,7 @@ void TreePatternNode::InlinePatternFragments(
for (const TreePredicateCall &Pred : getPredicateCalls())
FragTree->addPredicateCall(Pred);
- // The fragment we inlined could have recursive inlining that is needed. See
+ // The fragment we inlined could have recursive inlining that is needed. See
// if there are any pattern fragments in it and inline them as needed.
FragTree->InlinePatternFragments(TP, OutAlternatives);
}
@@ -2224,8 +2210,7 @@ void TreePatternNode::InlinePatternFragments(
/// GPR:$src operand above.
///
static TypeSetByHwMode getImplicitType(Record *R, unsigned ResNo,
- bool NotRegisters,
- bool Unnamed,
+ bool NotRegisters, bool Unnamed,
TreePattern &TP) {
CodeGenDAGPatterns &CDP = TP.getDAGPatterns();
@@ -2331,11 +2316,10 @@ static TypeSetByHwMode getImplicitType(Record *R, unsigned ResNo,
return TypeSetByHwMode(MVT::Other);
}
-
/// getIntrinsicInfo - If this node corresponds to an intrinsic, return the
/// CodeGenIntrinsic information for it, otherwise return a null pointer.
-const CodeGenIntrinsic *TreePatternNode::
-getIntrinsicInfo(const CodeGenDAGPatterns &CDP) const {
+const CodeGenIntrinsic *
+TreePatternNode::getIntrinsicInfo(const CodeGenDAGPatterns &CDP) const {
if (getOperator() != CDP.get_intrinsic_void_sdnode() &&
getOperator() != CDP.get_intrinsic_w_chain_sdnode() &&
getOperator() != CDP.get_intrinsic_wo_chain_sdnode())
@@ -2406,9 +2390,6 @@ bool TreePatternNode::NodeHasProperty(SDNP Property,
return CGP.getSDNodeInfo(getOperator()).hasProperty(Property);
}
-
-
-
/// TreeHasProperty - Return true if any node in this tree has the specified
/// property.
bool TreePatternNode::TreeHasProperty(SDNP Property,
@@ -2423,8 +2404,8 @@ bool TreePatternNode::TreeHasProperty(SDNP Property,
/// isCommutativeIntrinsic - Return true if the node corresponds to a
/// commutative intrinsic.
-bool
-TreePatternNode::isCommutativeIntrinsic(const CodeGenDAGPatterns &CDP) const {
+bool TreePatternNode::isCommutativeIntrinsic(
+ const CodeGenDAGPatterns &CDP) const {
if (const CodeGenIntrinsic *Int = getIntrinsicInfo(CDP))
return Int->isCommutative;
return false;
@@ -2441,19 +2422,16 @@ static bool isOperandClass(const TreePatternNode *N, StringRef Class) {
return false;
}
-static void emitTooManyOperandsError(TreePattern &TP,
- StringRef InstName,
- unsigned Expected,
- unsigned Actual) {
+static void emitTooManyOperandsError(TreePattern &TP, StringRef InstName,
+ unsigned Expected, unsigned Actual) {
TP.error("Instruction '" + InstName + "' was provided " + Twine(Actual) +
" operands but expected only " + Twine(Expected) + "!");
}
-static void emitTooFewOperandsError(TreePattern &TP,
- StringRef InstName,
+static void emitTooFewOperandsError(TreePattern &TP, StringRef InstName,
unsigned Actual) {
- TP.error("Instruction '" + InstName +
- "' expects more than the provided " + Twine(Actual) + " operands!");
+ TP.error("Instruction '" + InstName + "' expects more than the provided " +
+ Twine(Actual) + " operands!");
}
/// ApplyTypeConstraints - Apply all of the type constraints relevant to
@@ -2469,9 +2447,9 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) {
// If it's a regclass or something else known, include the type.
bool MadeChange = false;
for (unsigned i = 0, e = Types.size(); i != e; ++i)
- MadeChange |= UpdateNodeType(i, getImplicitType(DI->getDef(), i,
- NotRegisters,
- !hasName(), TP), TP);
+ MadeChange |= UpdateNodeType(
+ i, getImplicitType(DI->getDef(), i, NotRegisters, !hasName(), TP),
+ TP);
return MadeChange;
}
@@ -2530,8 +2508,8 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) {
// Apply type info to the intrinsic ID.
MadeChange |= getChild(0)->UpdateNodeType(0, MVT::iPTR, TP);
- for (unsigned i = 0, e = getNumChildren()-1; i != e; ++i) {
- MadeChange |= getChild(i+1)->ApplyTypeConstraints(TP, NotRegisters);
+ for (unsigned i = 0, e = getNumChildren() - 1; i != e; ++i) {
+ MadeChange |= getChild(i + 1)->ApplyTypeConstraints(TP, NotRegisters);
MVT::SimpleValueType OpVT =
getValueType(Int->IS.ParamTys[i]->getValueAsDef("VT"));
@@ -2562,14 +2540,14 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) {
if (getOperator()->isSubClassOf("Instruction")) {
const DAGInstruction &Inst = CDP.getInstruction(getOperator());
CodeGenInstruction &InstInfo =
- CDP.getTargetInfo().getInstruction(getOperator());
+ CDP.getTargetInfo().getInstruction(getOperator());
bool MadeChange = false;
// Apply the result types to the node, these come from the things in the
// (outs) list of the instruction.
- unsigned NumResultsToAdd = std::min(InstInfo.Operands.NumDefs,
- Inst.getNumResults());
+ unsigned NumResultsToAdd =
+ std::min(InstInfo.Operands.NumDefs, Inst.getNumResults());
for (unsigned ResNo = 0; ResNo != NumResultsToAdd; ++ResNo)
MadeChange |= UpdateNodeTypeFromInst(ResNo, Inst.getResult(ResNo), TP);
@@ -2581,7 +2559,7 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) {
// FIXME: Generalize to multiple possible types and multiple possible
// ImplicitDefs.
MVT::SimpleValueType VT =
- InstInfo.HasOneImplicitDefWithKnownVT(CDP.getTargetInfo());
+ InstInfo.HasOneImplicitDefWithKnownVT(CDP.getTargetInfo());
if (VT != MVT::Other)
MadeChange |= UpdateNodeType(ResNo, VT, TP);
@@ -2636,7 +2614,8 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) {
// the pattern was intended to override A or skip it.
unsigned NonOverridableOperands = NumFixedOperands;
while (NonOverridableOperands > NumResults &&
- CDP.operandHasDefault(InstInfo.Operands[NonOverridableOperands-1].Rec))
+ CDP.operandHasDefault(
+ InstInfo.Operands[NonOverridableOperands - 1].Rec))
--NonOverridableOperands;
unsigned ChildNo = 0;
@@ -2659,7 +2638,7 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) {
}
TreePatternNode *Child = getChild(ChildNo++);
- unsigned ChildResNo = 0; // Instructions always use res #0 of their op.
+ unsigned ChildResNo = 0; // Instructions always use res #0 of their op.
// If the operand has sub-operands, they may be provided by distinct
// child patterns, so attempt to match each sub-operand separately.
@@ -2672,8 +2651,7 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) {
if (Child->getNumMIResults(CDP) < NumArgs) {
// Match first sub-operand against the child we already have.
Record *SubRec = cast<DefInit>(MIOpInfo->getArg(0))->getDef();
- MadeChange |=
- Child->UpdateNodeTypeFromInst(ChildResNo, SubRec, TP);
+ MadeChange |= Child->UpdateNodeTypeFromInst(ChildResNo, SubRec, TP);
// And the remaining sub-operands against subsequent children.
for (unsigned Arg = 1; Arg < NumArgs; ++Arg) {
@@ -2686,7 +2664,7 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) {
SubRec = cast<DefInit>(MIOpInfo->getArg(Arg))->getDef();
MadeChange |=
- Child->UpdateNodeTypeFromInst(ChildResNo, SubRec, TP);
+ Child->UpdateNodeTypeFromInst(ChildResNo, SubRec, TP);
}
continue;
}
@@ -2699,8 +2677,8 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) {
}
if (!InstInfo.Operands.isVariadic && ChildNo != getNumChildren()) {
- emitTooManyOperandsError(TP, getOperator()->getName(),
- ChildNo, getNumChildren());
+ emitTooManyOperandsError(TP, getOperator()->getName(), ChildNo,
+ getNumChildren());
return false;
}
@@ -2759,7 +2737,6 @@ static bool OnlyOnRHSOfCommutative(TreePatternNode *N) {
return false;
}
-
/// canPatternMatch - If it is impossible for this pattern to match on this
/// target, fill in Reason and return false. Otherwise, return true. This is
/// used as a sanity check for .td files (to prevent people from writing stuff
@@ -2767,7 +2744,8 @@ static bool OnlyOnRHSOfCommutative(TreePatternNode *N) {
/// generating stuff that is useless.
bool TreePatternNode::canPatternMatch(std::string &Reason,
const CodeGenDAGPatterns &CDP) {
- if (isLeaf()) return true;
+ if (isLeaf())
+ return true;
for (unsigned i = 0, e = getNumChildren(); i != e; ++i)
if (!getChild(i)->canPatternMatch(Reason, CDP))
@@ -2790,11 +2768,12 @@ bool TreePatternNode::canPatternMatch(std::string &Reason,
if (NodeInfo.hasProperty(SDNPCommutative) || isCommIntrinsic) {
// Scan all of the operands of the node and make sure that only the last one
// is a constant node, unless the RHS also is.
- if (!OnlyOnRHSOfCommutative(getChild(getNumChildren()-1))) {
+ if (!OnlyOnRHSOfCommutative(getChild(getNumChildren() - 1))) {
unsigned Skip = isCommIntrinsic ? 1 : 0; // First operand is intrinsic id.
- for (unsigned i = Skip, e = getNumChildren()-1; i != e; ++i)
+ for (unsigned i = Skip, e = getNumChildren() - 1; i != e; ++i)
if (OnlyOnRHSOfCommutative(getChild(i))) {
- Reason="Immediate value must be on the RHS of commutative operators!";
+ Reason =
+ "Immediate value must be on the RHS of commutative operators!";
return false;
}
}
@@ -2808,17 +2787,17 @@ bool TreePatternNode::canPatternMatch(std::string &Reason,
//
TreePattern::TreePattern(Record *TheRec, ListInit *RawPat, bool isInput,
- CodeGenDAGPatterns &cdp) : TheRecord(TheRec), CDP(cdp),
- isInputPattern(isInput), HasError(false),
- Infer(*this) {
+ CodeGenDAGPatterns &cdp)
+ : TheRecord(TheRec), CDP(cdp), isInputPattern(isInput), HasError(false),
+ Infer(*this) {
for (Init *I : RawPat->getValues())
Trees.push_back(ParseTreePattern(I, ""));
}
TreePattern::TreePattern(Record *TheRec, DagInit *Pat, bool isInput,
- CodeGenDAGPatterns &cdp) : TheRecord(TheRec), CDP(cdp),
- isInputPattern(isInput), HasError(false),
- Infer(*this) {
+ CodeGenDAGPatterns &cdp)
+ : TheRecord(TheRec), CDP(cdp), isInputPattern(isInput), HasError(false),
+ Infer(*this) {
Trees.push_back(ParseTreePattern(Pat, ""));
}
@@ -2861,9 +2840,9 @@ TreePatternNodePtr TreePattern::ParseTreePattern(Init *TheInit,
/// (foo GPR, imm) -> (foo GPR, (imm))
if (R->isSubClassOf("SDNode") || R->isSubClassOf("PatFrags"))
return ParseTreePattern(
- DagInit::get(DI, nullptr,
- std::vector<std::pair<Init*, StringInit*> >()),
- OpName);
+ DagInit::get(DI, nullptr,
+ std::vector<std::pair<Init *, StringInit *>>()),
+ OpName);
// Input argument?
TreePatternNodePtr Res = makeIntrusiveRefCnt<TreePatternNode>(DI, 1);
@@ -2943,8 +2922,7 @@ TreePatternNodePtr TreePattern::ParseTreePattern(Init *TheInit,
!Operator->isSubClassOf("SDNodeXForm") &&
!Operator->isSubClassOf("Intrinsic") &&
!Operator->isSubClassOf("ComplexPattern") &&
- Operator->getName() != "set" &&
- Operator->getName() != "implicit")
+ Operator->getName() != "set" && Operator->getName() != "implicit")
error("Unrecognized node '" + Operator->getName() + "'!");
// Check to see if this is something that is illegal in an input pattern.
@@ -2956,20 +2934,16 @@ TreePatternNodePtr TreePattern::ParseTreePattern(Init *TheInit,
if (Operator->isSubClassOf("Intrinsic"))
error("Cannot use '" + Operator->getName() + "' in an output pattern!");
- if (Operator->isSubClassOf("SDNode") &&
- Operator->getName() != "imm" &&
- Operator->getName() != "timm" &&
- Operator->getName() != "fpimm" &&
+ if (Operator->isSubClassOf("SDNode") && Operator->getName() != "imm" &&
+ Operator->getName() != "timm" && Operator->getName() != "fpimm" &&
Operator->getName() != "tglobaltlsaddr" &&
Operator->getName() != "tconstpool" &&
Operator->getName() != "tjumptable" &&
Operator->getName() != "tframeindex" &&
Operator->getName() != "texternalsym" &&
Operator->getName() != "tblockaddress" &&
- Operator->getName() != "tglobaladdr" &&
- Operator->getName() != "bb" &&
- Operator->getName() != "vt" &&
- Operator->getName() != "mcsym")
+ Operator->getName() != "tglobaladdr" && Operator->getName() != "bb" &&
+ Operator->getName() != "vt" && Operator->getName() != "mcsym")
error("Cannot use '" + Operator->getName() + "' in an output pattern!");
}
@@ -2979,8 +2953,8 @@ TreePatternNodePtr TreePattern::ParseTreePattern(Init *TheInit,
for (unsigned i = 0, e = Dag->getNumArgs(); i != e; ++i)
Children.push_back(ParseTreePattern(Dag->getArg(i), Dag->getArgNameStr(i)));
- // Get the actual number of results before Operator is converted to an intrinsic
- // node (which is hard-coded to have either zero or one result).
+ // Get the actual number of results before Operator is converted to an
+ // intrinsic node (which is hard-coded to have either zero or one result).
unsigned NumResults = GetNumNodeResults(Operator, CDP);
// If the operator is an intrinsic, then this is just syntactic sugar for
@@ -2988,7 +2962,7 @@ TreePatternNodePtr TreePattern::ParseTreePattern(Init *TheInit,
// convert the intrinsic name to a number.
if (Operator->isSubClassOf("Intrinsic")) {
const CodeGenIntrinsic &Int = getDAGPatterns().getIntrinsic(Operator);
- unsigned IID = getDAGPatterns().getIntrinsicID(Operator)+1;
+ unsigned IID = getDAGPatterns().getIntrinsicID(Operator) + 1;
// If this intrinsic returns void, it must have side-effects and thus a
// chain.
@@ -3072,13 +3046,11 @@ static bool SimplifyTree(TreePatternNodePtr &N) {
return MadeChange;
}
-
-
/// InferAllTypes - Infer/propagate as many types throughout the expression
/// patterns as possible. Return true if all types are inferred, false
/// otherwise. Flags an error if a type contradiction is found.
-bool TreePattern::
-InferAllTypes(const StringMap<SmallVector<TreePatternNode*,1> > *InNamedTypes) {
+bool TreePattern::InferAllTypes(
+ const StringMap<SmallVector<TreePatternNode *, 1>> *InNamedTypes) {
if (NamedNodes.empty())
ComputeNamedNodes();
@@ -3092,7 +3064,7 @@ InferAllTypes(const StringMap<SmallVector<TreePatternNode*,1> > *InNamedTypes) {
// If there are constraints on our named nodes, apply them.
for (auto &Entry : NamedNodes) {
- SmallVectorImpl<TreePatternNode*> &Nodes = Entry.second;
+ SmallVectorImpl<TreePatternNode *> &Nodes = Entry.second;
// If we have input named node types, propagate their types to the named
// values here.
@@ -3103,8 +3075,8 @@ InferAllTypes(const StringMap<SmallVector<TreePatternNode*,1> > *InNamedTypes) {
return true;
}
- const SmallVectorImpl<TreePatternNode*> &InNodes =
- InNamedTypes->find(Entry.getKey())->second;
+ const SmallVectorImpl<TreePatternNode *> &InNodes =
+ InNamedTypes->find(Entry.getKey())->second;
// The input types should be fully resolved by now.
for (TreePatternNode *Node : Nodes) {
@@ -3120,19 +3092,18 @@ InferAllTypes(const StringMap<SmallVector<TreePatternNode*,1> > *InNamedTypes) {
continue;
}
- assert(Node->getNumTypes() == 1 &&
- InNodes[0]->getNumTypes() == 1 &&
+ assert(Node->getNumTypes() == 1 && InNodes[0]->getNumTypes() == 1 &&
"FIXME: cannot name multiple result nodes yet");
- MadeChange |= Node->UpdateNodeType(0, InNodes[0]->getExtType(0),
- *this);
+ MadeChange |=
+ Node->UpdateNodeType(0, InNodes[0]->getExtType(0), *this);
}
}
// If there are multiple nodes with the same name, they must all have the
// same type.
if (Entry.second.size() > 1) {
- for (unsigned i = 0, e = Nodes.size()-1; i != e; ++i) {
- TreePatternNode *N1 = Nodes[i], *N2 = Nodes[i+1];
+ for (unsigned i = 0, e = Nodes.size() - 1; i != e; ++i) {
+ TreePatternNode *N1 = Nodes[i], *N2 = Nodes[i + 1];
assert(N1->getNumTypes() == 1 && N2->getNumTypes() == 1 &&
"FIXME: cannot name multiple result nodes yet");
@@ -3190,7 +3161,7 @@ CodeGenDAGPatterns::CodeGenDAGPatterns(RecordKeeper &R,
ParsePatternFragments();
ParseDefaultOperands();
ParseInstructions();
- ParsePatternFragments(/*OutFrags*/true);
+ ParsePatternFragments(/*OutFrags*/ true);
ParsePatterns();
// Generate variants. For example, commutative patterns can match
@@ -3221,7 +3192,7 @@ Record *CodeGenDAGPatterns::getSDNodeNamed(StringRef Name) const {
// Parse all of the SDNode definitions for the target, populating SDNodes.
void CodeGenDAGPatterns::ParseNodeInfo() {
- std::vector<Record*> Nodes = Records.getAllDerivedDefinitions("SDNode");
+ std::vector<Record *> Nodes = Records.getAllDerivedDefinitions("SDNode");
const CodeGenHwModes &CGH = getTargetInfo().getHwModes();
while (!Nodes.empty()) {
@@ -3231,15 +3202,16 @@ void CodeGenDAGPatterns::ParseNodeInfo() {
}
// Get the builtin intrinsic nodes.
- intrinsic_void_sdnode = getSDNodeNamed("intrinsic_void");
- intrinsic_w_chain_sdnode = getSDNodeNamed("intrinsic_w_chain");
+ intrinsic_void_sdnode = getSDNodeNamed("intrinsic_void");
+ intrinsic_w_chain_sdnode = getSDNodeNamed("intrinsic_w_chain");
intrinsic_wo_chain_sdnode = getSDNodeNamed("intrinsic_wo_chain");
}
/// ParseNodeTransforms - Parse all SDNodeXForm instances into the SDNodeXForms
/// map, and emit them to the file as functions.
void CodeGenDAGPatterns::ParseNodeTransforms() {
- std::vector<Record*> Xforms = Records.getAllDerivedDefinitions("SDNodeXForm");
+ std::vector<Record *> Xforms =
+ Records.getAllDerivedDefinitions("SDNodeXForm");
while (!Xforms.empty()) {
Record *XFormNode = Xforms.back();
Record *SDNode = XFormNode->getValueAsDef("Opcode");
@@ -3252,21 +3224,22 @@ void CodeGenDAGPatterns::ParseNodeTransforms() {
}
void CodeGenDAGPatterns::ParseComplexPatterns() {
- std::vector<Record*> AMs = Records.getAllDerivedDefinitions("ComplexPattern");
+ std::vector<Record *> AMs =
+ Records.getAllDerivedDefinitions("ComplexPattern");
while (!AMs.empty()) {
ComplexPatterns.insert(std::make_pair(AMs.back(), AMs.back()));
AMs.pop_back();
}
}
-
/// ParsePatternFragments - Parse all of the PatFrag definitions in the .td
/// file, building up the PatternFragments map. After we've collected them all,
/// inline fragments together as necessary, so that there are no references left
/// inside a pattern fragment to a pattern fragment.
///
void CodeGenDAGPatterns::ParsePatternFragments(bool OutFrags) {
- std::vector<Record*> Fragments = Records.getAllDerivedDefinitions("PatFrags");
+ std::vector<Record *> Fragments =
+ Records.getAllDerivedDefinitions("PatFrags");
// First step, parse all of the fragments.
for (Record *Frag : Fragments) {
@@ -3274,10 +3247,9 @@ void CodeGenDAGPatterns::ParsePatternFragments(bool OutFrags) {
continue;
ListInit *LI = Frag->getValueAsListInit("Fragments");
- TreePattern *P =
- (PatternFragments[Frag] = std::make_unique<TreePattern>(
- Frag, LI, !Frag->isSubClassOf("OutPatFrag"),
- *this)).get();
+ TreePattern *P = (PatternFragments[Frag] = std::make_unique<TreePattern>(
+ Frag, LI, !Frag->isSubClassOf("OutPatFrag"), *this))
+ .get();
// Validate the argument list, converting it to set, to discard duplicates.
std::vector<std::string> &Args = P->getArgList();
@@ -3294,10 +3266,9 @@ void CodeGenDAGPatterns::ParsePatternFragments(bool OutFrags) {
DefInit *OpsOp = dyn_cast<DefInit>(OpsList->getOperator());
// Special cases: ops == outs == ins. Different names are used to
// improve readability.
- if (!OpsOp ||
- (OpsOp->getDef()->getName() != "ops" &&
- OpsOp->getDef()->getName() != "outs" &&
- OpsOp->getDef()->getName() != "ins"))
+ if (!OpsOp || (OpsOp->getDef()->getName() != "ops" &&
+ OpsOp->getDef()->getName() != "outs" &&
+ OpsOp->getDef()->getName() != "ins"))
P->error("Operands list should start with '(ops ... '!");
// Copy over the arguments.
@@ -3323,7 +3294,7 @@ void CodeGenDAGPatterns::ParsePatternFragments(bool OutFrags) {
// If there is a node transformation corresponding to this, keep track of
// it.
Record *Transform = Frag->getValueAsDef("OperandTransform");
- if (!getSDNodeTransform(Transform).second.empty()) // not noop xform?
+ if (!getSDNodeTransform(Transform).second.empty()) // not noop xform?
for (const auto &T : P->getTrees())
T->setTransformFn(Transform);
}
@@ -3354,7 +3325,7 @@ void CodeGenDAGPatterns::ParsePatternFragments(bool OutFrags) {
}
void CodeGenDAGPatterns::ParseDefaultOperands() {
- std::vector<Record*> DefaultOps;
+ std::vector<Record *> DefaultOps;
DefaultOps = Records.getAllDerivedDefinitions("OperandWithDefaultOps");
// Find some SDNode.
@@ -3366,10 +3337,10 @@ void CodeGenDAGPatterns::ParseDefaultOperands() {
// Clone the DefaultInfo dag node, changing the operator from 'ops' to
// SomeSDnode so that we can parse this.
- std::vector<std::pair<Init*, StringInit*> > Ops;
+ std::vector<std::pair<Init *, StringInit *>> Ops;
for (unsigned op = 0, e = DefaultInfo->getNumArgs(); op != e; ++op)
- Ops.push_back(std::make_pair(DefaultInfo->getArg(op),
- DefaultInfo->getArgName(op)));
+ Ops.push_back(
+ std::make_pair(DefaultInfo->getArg(op), DefaultInfo->getArgName(op)));
DagInit *DI = DagInit::get(SomeSDNode, nullptr, Ops);
// Create a TreePattern to parse this.
@@ -3520,7 +3491,7 @@ void CodeGenDAGPatterns::FindPatternInputsAndOutputs(
I.error("Cannot specify a transform function on a set node!");
// Check the set destinations.
- unsigned NumDests = Pat->getNumChildren()-1;
+ unsigned NumDests = Pat->getNumChildren() - 1;
for (unsigned i = 0; i != NumDests; ++i) {
TreePatternNodePtr Dest = Pat->getChildShared(i);
// For set destinations we also must resolve fragments here.
@@ -3565,6 +3536,7 @@ void CodeGenDAGPatterns::FindPatternInputsAndOutputs(
class InstAnalyzer {
const CodeGenDAGPatterns &CDP;
+
public:
bool hasSideEffects;
bool mayStore;
@@ -3574,8 +3546,8 @@ class InstAnalyzer {
bool hasChain;
InstAnalyzer(const CodeGenDAGPatterns &cdp)
- : CDP(cdp), hasSideEffects(false), mayStore(false), mayLoad(false),
- isBitcast(false), isVariadic(false), hasChain(false) {}
+ : CDP(cdp), hasSideEffects(false), mayStore(false), mayLoad(false),
+ isBitcast(false), isVariadic(false), hasChain(false) {}
void Analyze(const PatternToMatch &Pat) {
const TreePatternNode *N = Pat.getSrcPattern();
@@ -3611,9 +3583,12 @@ class InstAnalyzer {
// Handle ComplexPattern leaves.
if (LeafRec->isSubClassOf("ComplexPattern")) {
const ComplexPattern &CP = CDP.getComplexPattern(LeafRec);
- if (CP.hasProperty(SDNPMayStore)) mayStore = true;
- if (CP.hasProperty(SDNPMayLoad)) mayLoad = true;
- if (CP.hasProperty(SDNPSideEffect)) hasSideEffects = true;
+ if (CP.hasProperty(SDNPMayStore))
+ mayStore = true;
+ if (CP.hasProperty(SDNPMayLoad))
+ mayLoad = true;
+ if (CP.hasProperty(SDNPSideEffect))
+ hasSideEffects = true;
}
}
return;
@@ -3624,11 +3599,16 @@ class InstAnalyzer {
AnalyzeNode(N->getChild(i));
// Notice properties of the node.
- if (N->NodeHasProperty(SDNPMayStore, CDP)) mayStore = true;
- if (N->NodeHasProperty(SDNPMayLoad, CDP)) mayLoad = true;
- if (N->NodeHasProperty(SDNPSideEffect, CDP)) hasSideEffects = true;
- if (N->NodeHasProperty(SDNPVariadic, CDP)) isVariadic = true;
- if (N->NodeHasProperty(SDNPHasChain, CDP)) hasChain = true;
+ if (N->NodeHasProperty(SDNPMayStore, CDP))
+ mayStore = true;
+ if (N->NodeHasProperty(SDNPMayLoad, CDP))
+ mayLoad = true;
+ if (N->NodeHasProperty(SDNPSideEffect, CDP))
+ hasSideEffects = true;
+ if (N->NodeHasProperty(SDNPVariadic, CDP))
+ isVariadic = true;
+ if (N->NodeHasProperty(SDNPHasChain, CDP))
+ hasChain = true;
if (const CodeGenIntrinsic *IntInfo = N->getIntrinsicInfo(CDP)) {
ModRefInfo MR = IntInfo->ME.getModRef();
@@ -3645,17 +3625,15 @@ class InstAnalyzer {
hasSideEffects = true;
}
}
-
};
static bool InferFromPattern(CodeGenInstruction &InstInfo,
- const InstAnalyzer &PatInfo,
- Record *PatDef) {
+ const InstAnalyzer &PatInfo, Record *PatDef) {
bool Error = false;
// Remember where InstInfo got its flags.
if (InstInfo.hasUndefFlags())
- InstInfo.InferredFrom = PatDef;
+ InstInfo.InferredFrom = PatDef;
// Check explicitly set flags for consistency.
if (InstInfo.hasSideEffects != PatInfo.hasSideEffects &&
@@ -3666,14 +3644,14 @@ static bool InferFromPattern(CodeGenInstruction &InstInfo,
if (!InstInfo.hasSideEffects) {
Error = true;
PrintError(PatDef->getLoc(), "Pattern doesn't match hasSideEffects = " +
- Twine(InstInfo.hasSideEffects));
+ Twine(InstInfo.hasSideEffects));
}
}
if (InstInfo.mayStore != PatInfo.mayStore && !InstInfo.mayStore_Unset) {
Error = true;
- PrintError(PatDef->getLoc(), "Pattern doesn't match mayStore = " +
- Twine(InstInfo.mayStore));
+ PrintError(PatDef->getLoc(),
+ "Pattern doesn't match mayStore = " + Twine(InstInfo.mayStore));
}
if (InstInfo.mayLoad != PatInfo.mayLoad && !InstInfo.mayLoad_Unset) {
@@ -3681,8 +3659,8 @@ static bool InferFromPattern(CodeGenInstruction &InstInfo,
// Some targets translate immediates to loads.
if (!InstInfo.mayLoad) {
Error = true;
- PrintError(PatDef->getLoc(), "Pattern doesn't match mayLoad = " +
- Twine(InstInfo.mayLoad));
+ PrintError(PatDef->getLoc(),
+ "Pattern doesn't match mayLoad = " + Twine(InstInfo.mayLoad));
}
}
@@ -3712,11 +3690,13 @@ static bool InferFromPattern(CodeGenInstruction &InstInfo,
/// null_frag operator.
static bool hasNullFragReference(DagInit *DI) {
DefInit *OpDef = dyn_cast<DefInit>(DI->getOperator());
- if (!OpDef) return false;
+ if (!OpDef)
+ return false;
Record *Operator = OpDef->getDef();
// If this is the null fragment, return true.
- if (Operator->getName() == "null_frag") return true;
+ if (Operator->getName() == "null_frag")
+ return true;
// If any of the arguments reference the null fragment, return true.
for (unsigned i = 0, e = DI->getNumArgs(); i != e; ++i) {
if (auto Arg = dyn_cast<DefInit>(DI->getArg(i)))
@@ -3743,8 +3723,8 @@ static bool hasNullFragReference(ListInit *LI) {
}
/// Get all the instructions in a tree.
-static void
-getInstructionsInTree(TreePatternNode *Tree, SmallVectorImpl<Record*> &Instrs) {
+static void getInstructionsInTree(TreePatternNode *Tree,
+ SmallVectorImpl<Record *> &Instrs) {
if (Tree->isLeaf())
return;
if (Tree->getOperator()->isSubClassOf("Instruction"))
@@ -3755,8 +3735,7 @@ getInstructionsInTree(TreePatternNode *Tree, SmallVectorImpl<Record*> &Instrs) {
/// Check the class of a pattern leaf node against the instruction operand it
/// represents.
-static bool checkOperandClass(CGIOperandList::OperandInfo &OI,
- Record *Leaf) {
+static bool checkOperandClass(CGIOperandList::OperandInfo &OI, Record *Leaf) {
if (OI.Rec == Leaf)
return true;
@@ -3772,8 +3751,9 @@ static bool checkOperandClass(CGIOperandList::OperandInfo &OI,
return false;
}
-void CodeGenDAGPatterns::parseInstructionPattern(
- CodeGenInstruction &CGI, ListInit *Pat, DAGInstMap &DAGInsts) {
+void CodeGenDAGPatterns::parseInstructionPattern(CodeGenInstruction &CGI,
+ ListInit *Pat,
+ DAGInstMap &DAGInsts) {
assert(!DAGInsts.count(CGI.TheDef) && "Instruction already parsed!");
@@ -3789,7 +3769,7 @@ void CodeGenDAGPatterns::parseInstructionPattern(
MapVector<std::string, TreePatternNodePtr, std::map<std::string, unsigned>>
InstResults;
- std::vector<Record*> InstImpResults;
+ std::vector<Record *> InstImpResults;
// Verify that the top-level forms in the instruction are of void type, and
// fill in the InstResults map.
@@ -3805,8 +3785,8 @@ void CodeGenDAGPatterns::parseInstructionPattern(
Pat->getExtType(k).writeToStream(OS);
}
I.error("Top-level forms in instruction pattern should have"
- " void types, has types " +
- OS.str());
+ " void types, has types " +
+ OS.str());
}
// Find inputs and outputs, and verify the structure of the uses/defs.
@@ -3823,7 +3803,7 @@ void CodeGenDAGPatterns::parseInstructionPattern(
assert(I.getArgList().empty() && "Args list should still be empty here!");
// Check that all of the results occur first in the list.
- std::vector<Record*> Results;
+ std::vector<Record *> Results;
std::vector<unsigned> ResultIndices;
SmallVector<TreePatternNodePtr, 2> ResNodes;
for (unsigned i = 0; i != NumResults; ++i) {
@@ -3850,8 +3830,9 @@ void CodeGenDAGPatterns::parseInstructionPattern(
Record *R = cast<DefInit>(RNode->getLeafValue())->getDef();
ResNodes.push_back(std::move(RNode));
if (!R)
- I.error("Operand $" + OpName + " should be a set destination: all "
- "outputs must occur before inputs in operand list!");
+ I.error("Operand $" + OpName +
+ " should be a set destination: all "
+ "outputs must occur before inputs in operand list!");
if (!checkOperandClass(CGI.Operands[i], R))
I.error("Operand $" + OpName + " class mismatch!");
@@ -3868,7 +3849,7 @@ void CodeGenDAGPatterns::parseInstructionPattern(
// Loop over the inputs next.
std::vector<TreePatternNodePtr> ResultNodeOperands;
- std::vector<Record*> Operands;
+ std::vector<Record *> Operands;
for (unsigned i = NumResults, e = CGI.Operands.size(); i != e; ++i) {
CGIOperandList::OperandInfo &Op = CGI.Operands[i];
const std::string &OpName = Op.Name;
@@ -3885,16 +3866,17 @@ void CodeGenDAGPatterns::parseInstructionPattern(
continue;
}
I.error("Operand $" + OpName +
- " does not appear in the instruction pattern");
+ " does not appear in the instruction pattern");
}
TreePatternNodePtr InVal = InstInputs[OpName];
- InstInputs.erase(OpName); // It occurred, remove from map.
+ InstInputs.erase(OpName); // It occurred, remove from map.
if (InVal->isLeaf() && isa<DefInit>(InVal->getLeafValue())) {
Record *InRec = cast<DefInit>(InVal->getLeafValue())->getDef();
if (!checkOperandClass(Op, InRec))
- I.error("Operand $" + OpName + "'s register class disagrees"
- " between the operand and pattern");
+ I.error("Operand $" + OpName +
+ "'s register class disagrees"
+ " between the operand and pattern");
}
Operands.push_back(Op.Rec);
@@ -3910,7 +3892,7 @@ void CodeGenDAGPatterns::parseInstructionPattern(
std::vector<TreePatternNodePtr> Children;
Children.push_back(OpNode);
OpNode = makeIntrusiveRefCnt<TreePatternNode>(Xform, std::move(Children),
- OpNode->getNumTypes());
+ OpNode->getNumTypes());
}
ResultNodeOperands.push_back(std::move(OpNode));
@@ -3935,8 +3917,8 @@ void CodeGenDAGPatterns::parseInstructionPattern(
TreePatternNodePtr Pattern = I.getTree(0);
TreePatternNodePtr SrcPattern;
if (Pattern->getOperator()->getName() == "set") {
- SrcPattern = Pattern->getChild(Pattern->getNumChildren()-1)->clone();
- } else{
+ SrcPattern = Pattern->getChild(Pattern->getNumChildren() - 1)->clone();
+ } else {
// Not a set (store or something?)
SrcPattern = Pattern;
}
@@ -3954,7 +3936,8 @@ void CodeGenDAGPatterns::parseInstructionPattern(
/// any fragments involved. This populates the Instructions list with fully
/// resolved instructions.
void CodeGenDAGPatterns::ParseInstructions() {
- std::vector<Record*> Instrs = Records.getAllDerivedDefinitions("Instruction");
+ std::vector<Record *> Instrs =
+ Records.getAllDerivedDefinitions("Instruction");
for (Record *Instr : Instrs) {
ListInit *LI = nullptr;
@@ -3969,8 +3952,8 @@ void CodeGenDAGPatterns::ParseInstructions() {
// is from a multiclass expansion w/ a SDPatternOperator passed in as
// null_frag.
if (!LI || LI->empty() || hasNullFragReference(LI)) {
- std::vector<Record*> Results;
- std::vector<Record*> Operands;
+ std::vector<Record *> Results;
+ std::vector<Record *> Operands;
CodeGenInstruction &InstInfo = Target.getInstruction(Instr);
@@ -3980,14 +3963,15 @@ void CodeGenDAGPatterns::ParseInstructions() {
// The rest are inputs.
for (unsigned j = InstInfo.Operands.NumDefs,
- e = InstInfo.Operands.size(); j < e; ++j)
+ e = InstInfo.Operands.size();
+ j < e; ++j)
Operands.push_back(InstInfo.Operands[j].Rec);
}
// Create and insert the instruction.
Instructions.try_emplace(Instr, std::move(Results), std::move(Operands),
std::vector<Record *>());
- continue; // no pattern.
+ continue; // no pattern.
}
CodeGenInstruction &CGI = Target.getInstruction(Instr);
@@ -4036,19 +4020,18 @@ void CodeGenDAGPatterns::AddPatternToMatch(TreePattern *Pattern,
std::string Reason;
if (!PTM.getSrcPattern()->canPatternMatch(Reason, *this)) {
PrintWarning(Pattern->getRecord()->getLoc(),
- Twine("Pattern can never match: ") + Reason);
+ Twine("Pattern can never match: ") + Reason);
return;
}
// If the source pattern's root is a complex pattern, that complex pattern
// must specify the nodes it can potentially match.
if (const ComplexPattern *CP =
- PTM.getSrcPattern()->getComplexPatternInfo(*this))
+ PTM.getSrcPattern()->getComplexPatternInfo(*this))
if (CP->getRootNodes().empty())
Pattern->error("ComplexPattern at root must specify list of opcodes it"
" could match");
-
// Find all of the named values in the input and output, ensure they have the
// same type.
std::map<std::string, NameRecord> SrcNames, DstNames;
@@ -4074,8 +4057,8 @@ void CodeGenDAGPatterns::AddPatternToMatch(TreePattern *Pattern,
}
void CodeGenDAGPatterns::InferInstructionFlags() {
- ArrayRef<const CodeGenInstruction*> Instructions =
- Target.getInstructionsByEnumValue();
+ ArrayRef<const CodeGenInstruction *> Instructions =
+ Target.getInstructionsByEnumValue();
unsigned Errors = 0;
@@ -4085,7 +4068,7 @@ void CodeGenDAGPatterns::InferInstructionFlags() {
for (const PatternToMatch &PTM : ptms()) {
// We can only infer from single-instruction patterns, otherwise we won't
// know which instruction should get the flags.
- SmallVector<Record*, 8> PatInstrs;
+ SmallVector<Record *, 8> PatInstrs;
getInstructionsInTree(PTM.getDstPattern(), PatInstrs);
if (PatInstrs.size() != 1)
continue;
@@ -4109,7 +4092,7 @@ void CodeGenDAGPatterns::InferInstructionFlags() {
if (Target.guessInstructionProperties()) {
for (unsigned i = 0, e = Instructions.size(); i != e; ++i) {
CodeGenInstruction *InstInfo =
- const_cast<CodeGenInstruction *>(Instructions[i]);
+ const_cast<CodeGenInstruction *>(Instructions[i]);
if (InstInfo->InferredFrom)
continue;
// The mayLoad and mayStore flags default to false.
@@ -4123,7 +4106,7 @@ void CodeGenDAGPatterns::InferInstructionFlags() {
// Complain about any flags that are still undefined.
for (unsigned i = 0, e = Instructions.size(); i != e; ++i) {
CodeGenInstruction *InstInfo =
- const_cast<CodeGenInstruction *>(Instructions[i]);
+ const_cast<CodeGenInstruction *>(Instructions[i]);
if (InstInfo->InferredFrom)
continue;
if (InstInfo->hasSideEffects_Unset)
@@ -4138,12 +4121,11 @@ void CodeGenDAGPatterns::InferInstructionFlags() {
}
}
-
/// Verify instruction flags against pattern node properties.
void CodeGenDAGPatterns::VerifyInstructionFlags() {
unsigned Errors = 0;
for (const PatternToMatch &PTM : ptms()) {
- SmallVector<Record*, 8> Instrs;
+ SmallVector<Record *, 8> Instrs;
getInstructionsInTree(PTM.getDstPattern(), Instrs);
if (Instrs.empty())
continue;
@@ -4186,16 +4168,16 @@ void CodeGenDAGPatterns::VerifyInstructionFlags() {
++Errors;
for (const std::string &Msg : Msgs)
- PrintError(PTM.getSrcRecord()->getLoc(), Twine(Msg) + " on the " +
- (Instrs.size() == 1 ?
- "instruction" : "output instructions"));
+ PrintError(
+ PTM.getSrcRecord()->getLoc(),
+ Twine(Msg) + " on the " +
+ (Instrs.size() == 1 ? "instruction" : "output instructions"));
// Provide the location of the relevant instruction definitions.
for (const Record *Instr : Instrs) {
if (Instr != PTM.getSrcRecord())
PrintError(Instr->getLoc(), "defined here");
const CodeGenInstruction &InstInfo = Target.getInstruction(Instr);
- if (InstInfo.InferredFrom &&
- InstInfo.InferredFrom != InstInfo.TheDef &&
+ if (InstInfo.InferredFrom && InstInfo.InferredFrom != InstInfo.TheDef &&
InstInfo.InferredFrom != PTM.getSrcRecord())
PrintError(InstInfo.InferredFrom->getLoc(), "inferred from pattern");
}
@@ -4237,11 +4219,11 @@ static bool ForceArbitraryInstResultType(TreePatternNode *N, TreePattern &TP) {
// Promote xform function to be an explicit node wherever set.
static TreePatternNodePtr PromoteXForms(TreePatternNodePtr N) {
if (Record *Xform = N->getTransformFn()) {
- N->setTransformFn(nullptr);
- std::vector<TreePatternNodePtr> Children;
- Children.push_back(PromoteXForms(N));
- return makeIntrusiveRefCnt<TreePatternNode>(Xform, std::move(Children),
- N->getNumTypes());
+ N->setTransformFn(nullptr);
+ std::vector<TreePatternNodePtr> Children;
+ Children.push_back(PromoteXForms(N));
+ return makeIntrusiveRefCnt<TreePatternNode>(Xform, std::move(Children),
+ N->getNumTypes());
}
if (!N->isLeaf())
@@ -4252,9 +4234,9 @@ static TreePatternNodePtr PromoteXForms(TreePatternNodePtr N) {
return N;
}
-void CodeGenDAGPatterns::ParseOnePattern(Record *TheDef,
- TreePattern &Pattern, TreePattern &Result,
- const std::vector<Record *> &InstImpResults) {
+void CodeGenDAGPatterns::ParseOnePattern(
+ Record *TheDef, TreePattern &Pattern, TreePattern &Result,
+ const std::vector<Record *> &InstImpResults) {
// Inline pattern fragments and expand multiple alternatives.
Pattern.InlinePatternFragments();
@@ -4274,8 +4256,7 @@ void CodeGenDAGPatterns::ParseOnePattern(Record *TheDef,
// Infer as many types as possible. If we cannot infer all of them, we
// can never do anything with this pattern: report it to the user.
- InferredAllResultTypes =
- Result.InferAllTypes(&Pattern.getNamedNodesMap());
+ InferredAllResultTypes = Result.InferAllTypes(&Pattern.getNamedNodesMap());
IterateInference = false;
@@ -4286,11 +4267,11 @@ void CodeGenDAGPatterns::ParseOnePattern(Record *TheDef,
for (const auto &T : Pattern.getTrees())
for (unsigned i = 0, e = std::min(Result.getOnlyTree()->getNumTypes(),
T->getNumTypes());
- i != e; ++i) {
- IterateInference |= T->UpdateNodeType(
- i, Result.getOnlyTree()->getExtType(i), Result);
- IterateInference |= Result.getOnlyTree()->UpdateNodeType(
- i, T->getExtType(i), Result);
+ i != e; ++i) {
+ IterateInference |=
+ T->UpdateNodeType(i, Result.getOnlyTree()->getExtType(i), Result);
+ IterateInference |=
+ Result.getOnlyTree()->UpdateNodeType(i, T->getExtType(i), Result);
}
// If our iteration has converged and the input pattern's types are fully
@@ -4302,8 +4283,7 @@ void CodeGenDAGPatterns::ParseOnePattern(Record *TheDef,
//
// In any case, to handle this, we just go through and disambiguate some
// arbitrary types to the result pattern's nodes.
- if (!IterateInference && InferredAllPatternTypes &&
- !InferredAllResultTypes)
+ if (!IterateInference && InferredAllPatternTypes && !InferredAllResultTypes)
IterateInference =
ForceArbitraryInstResultType(Result.getTree(0).get(), Result);
} while (IterateInference);
@@ -4357,7 +4337,7 @@ void CodeGenDAGPatterns::ParseOnePattern(Record *TheDef,
}
void CodeGenDAGPatterns::ParsePatterns() {
- std::vector<Record*> Patterns = Records.getAllDerivedDefinitions("Pattern");
+ std::vector<Record *> Patterns = Records.getAllDerivedDefinitions("Pattern");
for (Record *CurPattern : Patterns) {
DagInit *Tree = CurPattern->getValueAsDag("PatternToMatch");
@@ -4369,7 +4349,8 @@ void CodeGenDAGPatterns::ParsePatterns() {
TreePattern Pattern(CurPattern, Tree, true, *this);
ListInit *LI = CurPattern->getValueAsListInit("ResultInstrs");
- if (LI->empty()) continue; // no pattern.
+ if (LI->empty())
+ continue; // no pattern.
// Parse the instruction.
TreePattern Result(CurPattern, LI, false, *this);
@@ -4382,7 +4363,7 @@ void CodeGenDAGPatterns::ParsePatterns() {
std::map<std::string, TreePatternNodePtr> InstInputs;
MapVector<std::string, TreePatternNodePtr, std::map<std::string, unsigned>>
InstResults;
- std::vector<Record*> InstImpResults;
+ std::vector<Record *> InstImpResults;
for (unsigned j = 0, ee = Pattern.getNumTrees(); j != ee; ++j)
FindPatternInputsAndOutputs(Pattern, Pattern.getTree(j), InstInputs,
InstResults, InstImpResults);
@@ -4512,7 +4493,6 @@ static void DumpDepVars(MultipleUseVarSet &DepVars) {
}
#endif
-
/// CombineChildVariants - Given a bunch of permutations of each child of the
/// 'operator' node, put them together in all possible ways.
static void CombineChildVariants(
@@ -4598,7 +4578,8 @@ static void CombineChildVariants(TreePatternNodePtr Orig,
static void
GatherChildrenOfAssociativeOpcode(TreePatternNodePtr N,
std::vector<TreePatternNodePtr> &Children) {
- assert(N->getNumChildren()==2 &&"Associative but doesn't have 2 children!");
+ assert(N->getNumChildren() == 2 &&
+ "Associative but doesn't have 2 children!");
Record *Operator = N->getOperator();
// Only permit raw nodes.
@@ -4725,7 +4706,6 @@ static void GenerateVariantsOf(TreePatternNodePtr N,
}
}
-
// GenerateVariants - Generate variants. For example, commutative patterns can
// match multiple ways. Add them to PatternsToMatch as well.
void CodeGenDAGPatterns::GenerateVariants() {
@@ -4782,7 +4762,8 @@ void CodeGenDAGPatterns::GenerateVariants() {
}
}
// If we already have it, ignore the variant.
- if (AlreadyExists) continue;
+ if (AlreadyExists)
+ continue;
// Otherwise, add it to the list of patterns we have.
PatternsToMatch.emplace_back(
diff --git a/llvm/utils/TableGen/CodeGenDAGPatterns.h b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
similarity index 89%
rename from llvm/utils/TableGen/CodeGenDAGPatterns.h
rename to llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
index 2611fe06f55ca5..cb1a1e2867b046 100644
--- a/llvm/utils/TableGen/CodeGenDAGPatterns.h
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.h
@@ -14,9 +14,9 @@
#ifndef LLVM_UTILS_TABLEGEN_CODEGENDAGPATTERNS_H
#define LLVM_UTILS_TABLEGEN_CODEGENDAGPATTERNS_H
-#include "CodeGenIntrinsics.h"
+#include "Basic/CodeGenIntrinsics.h"
+#include "Basic/SDNodeProperties.h"
#include "CodeGenTarget.h"
-#include "SDNodeProperties.h"
#include "llvm/ADT/IntrusiveRefCntPtr.h"
#include "llvm/ADT/MapVector.h"
#include "llvm/ADT/PointerUnion.h"
@@ -56,17 +56,15 @@ struct MachineValueTypeSet {
static_assert(std::is_same<std::underlying_type_t<MVT::SimpleValueType>,
uint8_t>::value,
"Change uint8_t here to the SimpleValueType's type");
- static unsigned constexpr Capacity = std::numeric_limits<uint8_t>::max()+1;
+ static unsigned constexpr Capacity = std::numeric_limits<uint8_t>::max() + 1;
using WordType = uint64_t;
- static unsigned constexpr WordWidth = CHAR_BIT*sizeof(WordType);
- static unsigned constexpr NumWords = Capacity/WordWidth;
- static_assert(NumWords*WordWidth == Capacity,
+ static unsigned constexpr WordWidth = CHAR_BIT * sizeof(WordType);
+ static unsigned constexpr NumWords = Capacity / WordWidth;
+ static_assert(NumWords * WordWidth == Capacity,
"Capacity should be a multiple of WordWidth");
LLVM_ATTRIBUTE_ALWAYS_INLINE
- MachineValueTypeSet() {
- clear();
- }
+ MachineValueTypeSet() { clear(); }
LLVM_ATTRIBUTE_ALWAYS_INLINE
unsigned size() const {
@@ -76,9 +74,7 @@ struct MachineValueTypeSet {
return Count;
}
LLVM_ATTRIBUTE_ALWAYS_INLINE
- void clear() {
- std::memset(Words.data(), 0, NumWords*sizeof(WordType));
- }
+ void clear() { std::memset(Words.data(), 0, NumWords * sizeof(WordType)); }
LLVM_ATTRIBUTE_ALWAYS_INLINE
bool empty() const {
for (WordType W : Words)
@@ -90,7 +86,7 @@ struct MachineValueTypeSet {
unsigned count(MVT T) const {
return (Words[T.SimpleTy / WordWidth] >> (T.SimpleTy % WordWidth)) & 1;
}
- std::pair<MachineValueTypeSet&,bool> insert(MVT T) {
+ std::pair<MachineValueTypeSet &, bool> insert(MVT T) {
bool V = count(T.SimpleTy);
Words[T.SimpleTy / WordWidth] |= WordType(1) << (T.SimpleTy % WordWidth);
return {*this, V};
@@ -113,8 +109,8 @@ struct MachineValueTypeSet {
using iterator_category = std::forward_iterator_tag;
using value_type = MVT;
using difference_type = ptrdiff_t;
- using pointer = const MVT*;
- using reference = const MVT&;
+ using pointer = const MVT *;
+ using reference = const MVT &;
LLVM_ATTRIBUTE_ALWAYS_INLINE
MVT operator*() const {
@@ -128,7 +124,7 @@ struct MachineValueTypeSet {
LLVM_ATTRIBUTE_ALWAYS_INLINE
const_iterator &operator++() {
assert(Pos != Capacity);
- Pos = find_from_pos(Pos+1);
+ Pos = find_from_pos(Pos + 1);
return *this;
}
@@ -137,9 +133,7 @@ struct MachineValueTypeSet {
return Set == It.Set && Pos == It.Pos;
}
LLVM_ATTRIBUTE_ALWAYS_INLINE
- bool operator!=(const const_iterator &It) const {
- return !operator==(It);
- }
+ bool operator!=(const const_iterator &It) const { return !operator==(It); }
private:
unsigned find_from_pos(unsigned P) const {
@@ -151,7 +145,7 @@ struct MachineValueTypeSet {
// the trailing bits need to be masked off to use findFirstSet.
if (SkipBits != 0) {
WordType W = Set->Words[SkipWords];
- W &= maskLeadingOnes<WordType>(WordWidth-SkipBits);
+ W &= maskLeadingOnes<WordType>(WordWidth - SkipBits);
if (W != 0)
return Count + llvm::countr_zero(W);
Count += WordWidth;
@@ -174,20 +168,18 @@ struct MachineValueTypeSet {
LLVM_ATTRIBUTE_ALWAYS_INLINE
const_iterator begin() const { return const_iterator(this, false); }
LLVM_ATTRIBUTE_ALWAYS_INLINE
- const_iterator end() const { return const_iterator(this, true); }
+ const_iterator end() const { return const_iterator(this, true); }
LLVM_ATTRIBUTE_ALWAYS_INLINE
bool operator==(const MachineValueTypeSet &S) const {
return Words == S.Words;
}
LLVM_ATTRIBUTE_ALWAYS_INLINE
- bool operator!=(const MachineValueTypeSet &S) const {
- return !operator==(S);
- }
+ bool operator!=(const MachineValueTypeSet &S) const { return !operator==(S); }
private:
friend struct const_iterator;
- std::array<WordType,NumWords> Words;
+ std::array<WordType, NumWords> Words;
};
raw_ostream &operator<<(raw_ostream &OS, const MachineValueTypeSet &T);
@@ -200,14 +192,12 @@ struct TypeSetByHwMode : public InfoByHwMode<MachineValueTypeSet> {
TypeSetByHwMode(const TypeSetByHwMode &VTS) = default;
TypeSetByHwMode &operator=(const TypeSetByHwMode &) = default;
TypeSetByHwMode(MVT::SimpleValueType VT)
- : TypeSetByHwMode(ValueTypeByHwMode(VT)) {}
+ : TypeSetByHwMode(ValueTypeByHwMode(VT)) {}
TypeSetByHwMode(ValueTypeByHwMode VT)
- : TypeSetByHwMode(ArrayRef<ValueTypeByHwMode>(&VT, 1)) {}
+ : TypeSetByHwMode(ArrayRef<ValueTypeByHwMode>(&VT, 1)) {}
TypeSetByHwMode(ArrayRef<ValueTypeByHwMode> VTList);
- SetType &getOrCreate(unsigned Mode) {
- return Map[Mode];
- }
+ SetType &getOrCreate(unsigned Mode) { return Map[Mode]; }
bool isValueTypeByHwMode(bool AllowEmpty) const;
ValueTypeByHwMode getValueTypeByHwMode() const;
@@ -225,9 +215,7 @@ struct TypeSetByHwMode : public InfoByHwMode<MachineValueTypeSet> {
bool isPossible() const;
- bool isPointer() const {
- return getValueTypeByHwMode().isPointer();
- }
+ bool isPointer() const { return getValueTypeByHwMode().isPointer(); }
unsigned getPtrAddrSpace() const {
assert(isPointer());
@@ -313,8 +301,7 @@ struct TypeInfer {
/// Ensure that for each type T in \p Sub, T is a vector type, and there
/// exists a type U in \p Vec such that U is a vector type with the same
/// element type as T and at least as many elements as T.
- bool EnforceVectorSubVectorTypeIs(TypeSetByHwMode &Vec,
- TypeSetByHwMode &Sub);
+ bool EnforceVectorSubVectorTypeIs(TypeSetByHwMode &Vec, TypeSetByHwMode &Sub);
/// 1. Ensure that \p V has a scalar type iff \p W has a scalar type.
/// 2. Ensure that for each vector type T in \p V, there exists a vector
/// type U in \p W, such that T and U have the same number of elements.
@@ -346,15 +333,13 @@ struct TypeInfer {
SuppressValidation(TypeInfer &TI) : Infer(TI), SavedValidate(TI.Validate) {
Infer.Validate = false;
}
- ~SuppressValidation() {
- Infer.Validate = SavedValidate;
- }
+ ~SuppressValidation() { Infer.Validate = SavedValidate; }
TypeInfer &Infer;
bool SavedValidate;
};
TreePattern &TP;
- bool Validate = true; // Indicate whether to validate types.
+ bool Validate = true; // Indicate whether to validate types.
private:
const TypeSetByHwMode &getLegalTypes() const;
@@ -372,14 +357,24 @@ typedef StringSet<> MultipleUseVarSet;
struct SDTypeConstraint {
SDTypeConstraint(Record *R, const CodeGenHwModes &CGH);
- unsigned OperandNo; // The operand # this constraint applies to.
+ unsigned OperandNo; // The operand # this constraint applies to.
enum {
- SDTCisVT, SDTCisPtrTy, SDTCisInt, SDTCisFP, SDTCisVec, SDTCisSameAs,
- SDTCisVTSmallerThanOp, SDTCisOpSmallerThanOp, SDTCisEltOfVec,
- SDTCisSubVecOfVec, SDTCVecEltisVT, SDTCisSameNumEltsAs, SDTCisSameSizeAs
+ SDTCisVT,
+ SDTCisPtrTy,
+ SDTCisInt,
+ SDTCisFP,
+ SDTCisVec,
+ SDTCisSameAs,
+ SDTCisVTSmallerThanOp,
+ SDTCisOpSmallerThanOp,
+ SDTCisEltOfVec,
+ SDTCisSubVecOfVec,
+ SDTCVecEltisVT,
+ SDTCisSameNumEltsAs,
+ SDTCisSameSizeAs
} ConstraintType;
- union { // The discriminated union.
+ union { // The discriminated union.
struct {
unsigned OtherOperandNum;
} SDTCisSameAs_Info;
@@ -422,6 +417,7 @@ struct SDTypeConstraint {
class ScopedName {
unsigned Scope;
std::string Identifier;
+
public:
ScopedName(unsigned Scope, StringRef Identifier)
: Scope(Scope), Identifier(std::string(Identifier)) {
@@ -447,6 +443,7 @@ class SDNodeInfo {
unsigned NumResults;
int NumOperands;
std::vector<SDTypeConstraint> TypeConstraints;
+
public:
// Parse the specified record.
SDNodeInfo(Record *R, const CodeGenHwModes &CGH);
@@ -487,11 +484,11 @@ class TreePredicateFn {
/// PatFragRec - This is the TreePattern for the PatFrag that we
/// originally came from.
TreePattern *PatFragRec;
+
public:
/// TreePredicateFn constructor. Here 'N' is a subclass of PatFrag.
TreePredicateFn(TreePattern *N);
-
TreePattern *getOrigPatFragRecord() const { return PatFragRec; }
/// isAlwaysTrue - Return true if this is a noop predicate.
@@ -582,7 +579,8 @@ class TreePredicateFn {
bool isAtomicOrderingWeakerThanRelease() const;
/// If non-null, indicates that this predicate is a predefined memory VT
- /// predicate for a load/store and returns the ValueType record for the memory VT.
+ /// predicate for a load/store and returns the ValueType record for the memory
+ /// VT.
Record *getMemoryVT() const;
/// If non-null, indicates that this predicate is a predefined memory VT
/// predicate (checking only the scalar type) for load/store and returns the
@@ -615,14 +613,12 @@ struct TreePredicateCall {
unsigned Scope;
TreePredicateCall(const TreePredicateFn &Fn, unsigned Scope)
- : Fn(Fn), Scope(Scope) {}
+ : Fn(Fn), Scope(Scope) {}
bool operator==(const TreePredicateCall &o) const {
return Fn == o.Fn && Scope == o.Scope;
}
- bool operator!=(const TreePredicateCall &o) const {
- return !(*this == o);
- }
+ bool operator!=(const TreePredicateCall &o) const { return !(*this == o); }
};
class TreePatternNode : public RefCountedBase<TreePatternNode> {
@@ -681,7 +677,7 @@ class TreePatternNode : public RefCountedBase<TreePatternNode> {
const std::vector<ScopedName> &getNamesAsPredicateArg() const {
return NamesAsPredicateArg;
}
- void setNamesAsPredicateArg(const std::vector<ScopedName>& Names) {
+ void setNamesAsPredicateArg(const std::vector<ScopedName> &Names) {
NamesAsPredicateArg = Names;
}
void addNameAsPredicateArg(const ScopedName &N) {
@@ -733,9 +729,7 @@ class TreePatternNode : public RefCountedBase<TreePatternNode> {
const TreePatternNodePtr &getChildShared(unsigned N) const {
return Children[N];
}
- TreePatternNodePtr &getChildSharedPtr(unsigned N) {
- return Children[N];
- }
+ TreePatternNodePtr &getChildSharedPtr(unsigned N) { return Children[N]; }
void setChild(unsigned i, TreePatternNodePtr N) { Children[i] = N; }
/// hasChild - Return true if N is any of our children.
@@ -762,7 +756,8 @@ class TreePatternNode : public RefCountedBase<TreePatternNode> {
}
void addPredicateCall(const TreePredicateCall &Call) {
assert(!Call.Fn.isAlwaysTrue() && "Empty predicate string!");
- assert(!is_contained(PredicateCalls, Call) && "predicate applied recursively");
+ assert(!is_contained(PredicateCalls, Call) &&
+ "predicate applied recursively");
PredicateCalls.push_back(Call);
}
void addPredicateCall(const TreePredicateFn &Fn, unsigned Scope) {
@@ -805,8 +800,7 @@ class TreePatternNode : public RefCountedBase<TreePatternNode> {
void print(raw_ostream &OS) const;
void dump() const;
-public: // Higher level manipulation routines.
-
+public: // Higher level manipulation routines.
/// clone - Return a new copy of this tree.
///
TreePatternNodePtr clone() const;
@@ -845,8 +839,7 @@ class TreePatternNode : public RefCountedBase<TreePatternNode> {
TreePattern &TP);
bool UpdateNodeType(unsigned ResNo, MVT::SimpleValueType InTy,
TreePattern &TP);
- bool UpdateNodeType(unsigned ResNo, ValueTypeByHwMode InTy,
- TreePattern &TP);
+ bool UpdateNodeType(unsigned ResNo, ValueTypeByHwMode InTy, TreePattern &TP);
// Update node type with types inferred from an instruction operand or result
// def from the ins/outs lists.
@@ -910,7 +903,6 @@ class TreePattern {
TypeInfer Infer;
public:
-
/// TreePattern constructor - Parse the specified DagInits into the
/// current record.
TreePattern(Record *TheRec, ListInit *RawPat, bool isInput,
@@ -971,12 +963,8 @@ class TreePattern {
/// error - If this is the first error in the current resolution step,
/// print it and set the error flag. Otherwise, continue silently.
void error(const Twine &Msg);
- bool hasError() const {
- return HasError;
- }
- void resetError() {
- HasError = false;
- }
+ bool hasError() const { return HasError; }
+ void resetError() { HasError = false; }
TypeInfer &getInfer() { return Infer; }
@@ -989,7 +977,6 @@ class TreePattern {
void ComputeNamedNodes(TreePatternNode *N);
};
-
inline bool TreePatternNode::UpdateNodeType(unsigned ResNo,
const TypeSetByHwMode &InTy,
TreePattern &TP) {
@@ -1014,7 +1001,6 @@ inline bool TreePatternNode::UpdateNodeType(unsigned ResNo,
return TP.getInfer().MergeInTypeInfo(Types[ResNo], VTS);
}
-
/// DAGDefaultOperand - One of these is created for each OperandWithDefaultOps
/// that has a set ExecuteAlways / DefaultOps field.
struct DAGDefaultOperand {
@@ -1022,9 +1008,9 @@ struct DAGDefaultOperand {
};
class DAGInstruction {
- std::vector<Record*> Results;
- std::vector<Record*> Operands;
- std::vector<Record*> ImpResults;
+ std::vector<Record *> Results;
+ std::vector<Record *> Operands;
+ std::vector<Record *> ImpResults;
TreePatternNodePtr SrcPattern;
TreePatternNodePtr ResultPattern;
@@ -1041,7 +1027,7 @@ class DAGInstruction {
unsigned getNumResults() const { return Results.size(); }
unsigned getNumOperands() const { return Operands.size(); }
unsigned getNumImpResults() const { return ImpResults.size(); }
- const std::vector<Record*>& getImpResults() const { return ImpResults; }
+ const std::vector<Record *> &getImpResults() const { return ImpResults; }
Record *getResult(unsigned RN) const {
assert(RN < Results.size());
@@ -1065,34 +1051,33 @@ class DAGInstruction {
/// PatternToMatch - Used by CodeGenDAGPatterns to keep tab of patterns
/// processed to produce isel.
class PatternToMatch {
- Record *SrcRecord; // Originating Record for the pattern.
- ListInit *Predicates; // Top level predicate conditions to match.
- TreePatternNodePtr SrcPattern; // Source pattern to match.
- TreePatternNodePtr DstPattern; // Resulting pattern.
- std::vector<Record*> Dstregs; // Physical register defs being matched.
- std::string HwModeFeatures;
- int AddedComplexity; // Add to matching pattern complexity.
- unsigned ID; // Unique ID for the record.
+ Record *SrcRecord; // Originating Record for the pattern.
+ ListInit *Predicates; // Top level predicate conditions to match.
+ TreePatternNodePtr SrcPattern; // Source pattern to match.
+ TreePatternNodePtr DstPattern; // Resulting pattern.
+ std::vector<Record *> Dstregs; // Physical register defs being matched.
+ std::string HwModeFeatures;
+ int AddedComplexity; // Add to matching pattern complexity.
+ unsigned ID; // Unique ID for the record.
public:
PatternToMatch(Record *srcrecord, ListInit *preds, TreePatternNodePtr src,
TreePatternNodePtr dst, std::vector<Record *> dstregs,
- int complexity, unsigned uid,
- const Twine &hwmodefeatures = "")
+ int complexity, unsigned uid, const Twine &hwmodefeatures = "")
: SrcRecord(srcrecord), Predicates(preds), SrcPattern(src),
DstPattern(dst), Dstregs(std::move(dstregs)),
HwModeFeatures(hwmodefeatures.str()), AddedComplexity(complexity),
ID(uid) {}
- Record *getSrcRecord() const { return SrcRecord; }
- ListInit *getPredicates() const { return Predicates; }
+ Record *getSrcRecord() const { return SrcRecord; }
+ ListInit *getPredicates() const { return Predicates; }
TreePatternNode *getSrcPattern() const { return SrcPattern.get(); }
TreePatternNodePtr getSrcPatternShared() const { return SrcPattern; }
TreePatternNode *getDstPattern() const { return DstPattern.get(); }
TreePatternNodePtr getDstPatternShared() const { return DstPattern; }
- const std::vector<Record*> &getDstRegs() const { return Dstregs; }
- StringRef getHwModeFeatures() const { return HwModeFeatures; }
- int getAddedComplexity() const { return AddedComplexity; }
+ const std::vector<Record *> &getDstRegs() const { return Dstregs; }
+ StringRef getHwModeFeatures() const { return HwModeFeatures; }
+ int getAddedComplexity() const { return AddedComplexity; }
unsigned getID() const { return ID; }
std::string getPredicateCheck() const;
@@ -1108,14 +1093,14 @@ class CodeGenDAGPatterns {
CodeGenTarget Target;
CodeGenIntrinsicTable Intrinsics;
- std::map<Record*, SDNodeInfo, LessRecordByID> SDNodes;
- std::map<Record*, std::pair<Record*, std::string>, LessRecordByID>
+ std::map<Record *, SDNodeInfo, LessRecordByID> SDNodes;
+ std::map<Record *, std::pair<Record *, std::string>, LessRecordByID>
SDNodeXForms;
- std::map<Record*, ComplexPattern, LessRecordByID> ComplexPatterns;
+ std::map<Record *, ComplexPattern, LessRecordByID> ComplexPatterns;
std::map<Record *, std::unique_ptr<TreePattern>, LessRecordByID>
PatternFragments;
- std::map<Record*, DAGDefaultOperand, LessRecordByID> DefaultOperands;
- std::map<Record*, DAGInstruction, LessRecordByID> Instructions;
+ std::map<Record *, DAGDefaultOperand, LessRecordByID> DefaultOperands;
+ std::map<Record *, DAGInstruction, LessRecordByID> Instructions;
// Specific SDNode definitions:
Record *intrinsic_void_sdnode;
@@ -1128,7 +1113,7 @@ class CodeGenDAGPatterns {
TypeSetByHwMode LegalVTS;
- using PatternRewriterFn = std::function<void (TreePattern *)>;
+ using PatternRewriterFn = std::function<void(TreePattern *)>;
PatternRewriterFn PatternRewriter;
unsigned NumScopes = 0;
@@ -1150,7 +1135,7 @@ class CodeGenDAGPatterns {
}
// Node transformation lookups.
- typedef std::pair<Record*, std::string> NodeXForm;
+ typedef std::pair<Record *, std::string> NodeXForm;
const NodeXForm &getSDNodeTransform(Record *R) const {
auto F = SDNodeXForms.find(R);
assert(F != SDNodeXForms.end() && "Invalid transform!");
@@ -1165,25 +1150,27 @@ class CodeGenDAGPatterns {
const CodeGenIntrinsic &getIntrinsic(Record *R) const {
for (unsigned i = 0, e = Intrinsics.size(); i != e; ++i)
- if (Intrinsics[i].TheDef == R) return Intrinsics[i];
+ if (Intrinsics[i].TheDef == R)
+ return Intrinsics[i];
llvm_unreachable("Unknown intrinsic!");
}
const CodeGenIntrinsic &getIntrinsicInfo(unsigned IID) const {
- if (IID-1 < Intrinsics.size())
- return Intrinsics[IID-1];
+ if (IID - 1 < Intrinsics.size())
+ return Intrinsics[IID - 1];
llvm_unreachable("Bad intrinsic ID!");
}
unsigned getIntrinsicID(Record *R) const {
for (unsigned i = 0, e = Intrinsics.size(); i != e; ++i)
- if (Intrinsics[i].TheDef == R) return i;
+ if (Intrinsics[i].TheDef == R)
+ return i;
llvm_unreachable("Unknown intrinsic!");
}
const DAGDefaultOperand &getDefaultOperand(Record *R) const {
auto F = DefaultOperands.find(R);
- assert(F != DefaultOperands.end() &&"Isn't an analyzed default operand!");
+ assert(F != DefaultOperands.end() && "Isn't an analyzed default operand!");
return F->second;
}
@@ -1213,10 +1200,9 @@ class CodeGenDAGPatterns {
iterator_range<ptm_iterator> ptms() const { return PatternsToMatch; }
/// Parse the Pattern for an instruction, and insert the result in DAGInsts.
- typedef std::map<Record*, DAGInstruction, LessRecordByID> DAGInstMap;
- void parseInstructionPattern(
- CodeGenInstruction &CGI, ListInit *Pattern,
- DAGInstMap &DAGInsts);
+ typedef std::map<Record *, DAGInstruction, LessRecordByID> DAGInstMap;
+ void parseInstructionPattern(CodeGenInstruction &CGI, ListInit *Pattern,
+ DAGInstMap &DAGInsts);
const DAGInstruction &getInstruction(Record *R) const {
auto F = Instructions.find(R);
@@ -1224,9 +1210,7 @@ class CodeGenDAGPatterns {
return F->second;
}
- Record *get_intrinsic_void_sdnode() const {
- return intrinsic_void_sdnode;
- }
+ Record *get_intrinsic_void_sdnode() const { return intrinsic_void_sdnode; }
Record *get_intrinsic_w_chain_sdnode() const {
return intrinsic_w_chain_sdnode;
}
@@ -1238,7 +1222,7 @@ class CodeGenDAGPatterns {
bool operandHasDefault(Record *Op) const {
return Op->isSubClassOf("OperandWithDefaultOps") &&
- !getDefaultOperand(Op).DefaultOps.empty();
+ !getDefaultOperand(Op).DefaultOps.empty();
}
private:
@@ -1254,8 +1238,8 @@ class CodeGenDAGPatterns {
void GenerateVariants();
void VerifyInstructionFlags();
- void ParseOnePattern(Record *TheDef,
- TreePattern &Pattern, TreePattern &Result,
+ void ParseOnePattern(Record *TheDef, TreePattern &Pattern,
+ TreePattern &Result,
const std::vector<Record *> &InstImpResults);
void AddPatternToMatch(TreePattern *Pattern, PatternToMatch &&PTM);
void FindPatternInputsAndOutputs(
@@ -1266,14 +1250,13 @@ class CodeGenDAGPatterns {
std::vector<Record *> &InstImpResults);
};
-
inline bool SDNodeInfo::ApplyTypeConstraints(TreePatternNode *N,
TreePattern &TP) const {
- bool MadeChange = false;
- for (unsigned i = 0, e = TypeConstraints.size(); i != e; ++i)
- MadeChange |= TypeConstraints[i].ApplyTypeConstraint(N, *this, TP);
- return MadeChange;
- }
+ bool MadeChange = false;
+ for (unsigned i = 0, e = TypeConstraints.size(); i != e; ++i)
+ MadeChange |= TypeConstraints[i].ApplyTypeConstraint(N, *this, TP);
+ return MadeChange;
+}
} // end namespace llvm
diff --git a/llvm/utils/TableGen/CodeGenHwModes.cpp b/llvm/utils/TableGen/Common/CodeGenHwModes.cpp
similarity index 89%
rename from llvm/utils/TableGen/CodeGenHwModes.cpp
rename to llvm/utils/TableGen/Common/CodeGenHwModes.cpp
index 2171507f4c63f6..7c08c7516054ec 100644
--- a/llvm/utils/TableGen/CodeGenHwModes.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenHwModes.cpp
@@ -37,17 +37,17 @@ HwMode::HwMode(Record *R) {
}
LLVM_DUMP_METHOD
-void HwMode::dump() const {
- dbgs() << Name << ": " << Features << '\n';
-}
+void HwMode::dump() const { dbgs() << Name << ": " << Features << '\n'; }
HwModeSelect::HwModeSelect(Record *R, CodeGenHwModes &CGH) {
- std::vector<Record*> Modes = R->getValueAsListOfDefs("Modes");
- std::vector<Record*> Objects = R->getValueAsListOfDefs("Objects");
+ std::vector<Record *> Modes = R->getValueAsListOfDefs("Modes");
+ std::vector<Record *> Objects = R->getValueAsListOfDefs("Objects");
if (Modes.size() != Objects.size()) {
- PrintError(R->getLoc(), "in record " + R->getName() +
- " derived from HwModeSelect: the lists Modes and Objects should "
- "have the same size");
+ PrintError(
+ R->getLoc(),
+ "in record " + R->getName() +
+ " derived from HwModeSelect: the lists Modes and Objects should "
+ "have the same size");
report_fatal_error("error in target description.");
}
for (unsigned i = 0, e = Modes.size(); i != e; ++i) {
diff --git a/llvm/utils/TableGen/Common/CodeGenHwModes.h b/llvm/utils/TableGen/Common/CodeGenHwModes.h
new file mode 100644
index 00000000000000..9a5b7a8c2c1c9d
--- /dev/null
+++ b/llvm/utils/TableGen/Common/CodeGenHwModes.h
@@ -0,0 +1,67 @@
+//===--- CodeGenHwModes.h ---------------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+// Classes to parse and store HW mode information for instruction selection.
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_UTILS_TABLEGEN_CODEGENHWMODES_H
+#define LLVM_UTILS_TABLEGEN_CODEGENHWMODES_H
+
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/StringRef.h"
+#include <cassert>
+#include <map>
+#include <string>
+#include <utility>
+#include <vector>
+
+// HwModeId -> list of predicates (definition)
+
+namespace llvm {
+class Record;
+class RecordKeeper;
+
+struct CodeGenHwModes;
+
+struct HwMode {
+ HwMode(Record *R);
+ StringRef Name;
+ std::string Features;
+ std::string Predicates;
+ void dump() const;
+};
+
+struct HwModeSelect {
+ HwModeSelect(Record *R, CodeGenHwModes &CGH);
+ typedef std::pair<unsigned, Record *> PairType;
+ std::vector<PairType> Items;
+ void dump() const;
+};
+
+struct CodeGenHwModes {
+ enum : unsigned { DefaultMode = 0 };
+ static StringRef DefaultModeName;
+
+ CodeGenHwModes(RecordKeeper &R);
+ unsigned getHwModeId(Record *R) const;
+ const HwMode &getMode(unsigned Id) const {
+ assert(Id != 0 && "Mode id of 0 is reserved for the default mode");
+ return Modes[Id - 1];
+ }
+ const HwModeSelect &getHwModeSelect(Record *R) const;
+ unsigned getNumModeIds() const { return Modes.size() + 1; }
+ void dump() const;
+
+private:
+ RecordKeeper &Records;
+ DenseMap<Record *, unsigned> ModeIds; // HwMode Record -> HwModeId
+ std::vector<HwMode> Modes;
+ std::map<Record *, HwModeSelect> ModeSelects;
+};
+} // namespace llvm
+
+#endif // LLVM_UTILS_TABLEGEN_CODEGENHWMODES_H
diff --git a/llvm/utils/TableGen/CodeGenInstAlias.cpp b/llvm/utils/TableGen/Common/CodeGenInstAlias.cpp
similarity index 100%
rename from llvm/utils/TableGen/CodeGenInstAlias.cpp
rename to llvm/utils/TableGen/Common/CodeGenInstAlias.cpp
diff --git a/llvm/utils/TableGen/CodeGenInstAlias.h b/llvm/utils/TableGen/Common/CodeGenInstAlias.h
similarity index 100%
rename from llvm/utils/TableGen/CodeGenInstAlias.h
rename to llvm/utils/TableGen/Common/CodeGenInstAlias.h
diff --git a/llvm/utils/TableGen/CodeGenInstruction.cpp b/llvm/utils/TableGen/Common/CodeGenInstruction.cpp
similarity index 83%
rename from llvm/utils/TableGen/CodeGenInstruction.cpp
rename to llvm/utils/TableGen/Common/CodeGenInstruction.cpp
index 5cd89417c002b3..a569194ef23cbc 100644
--- a/llvm/utils/TableGen/CodeGenInstruction.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenInstruction.cpp
@@ -55,15 +55,15 @@ CGIOperandList::CGIOperandList(Record *R) : TheDef(R) {
unsigned e = InDI->getNumArgs() + OutDI->getNumArgs();
OperandList.reserve(e);
bool VariadicOuts = false;
- for (unsigned i = 0; i != e; ++i){
+ for (unsigned i = 0; i != e; ++i) {
Init *ArgInit;
StringRef ArgName;
if (i < NumDefs) {
ArgInit = OutDI->getArg(i);
ArgName = OutDI->getArgNameStr(i);
} else {
- ArgInit = InDI->getArg(i-NumDefs);
- ArgName = InDI->getArgNameStr(i-NumDefs);
+ ArgInit = InDI->getArg(i - NumDefs);
+ ArgName = InDI->getArgNameStr(i - NumDefs);
}
DagInit *SubArgDag = dyn_cast<DagInit>(ArgInit);
@@ -192,7 +192,6 @@ CGIOperandList::CGIOperandList(Record *R) : TheDef(R) {
--NumDefs;
}
-
/// getOperandNamed - Return the index of the operand with the specified
/// non-empty name. If the instruction does not have an operand with the
/// specified name, abort.
@@ -230,7 +229,7 @@ bool CGIOperandList::hasSubOperandAlias(
return false;
}
-std::pair<unsigned,unsigned>
+std::pair<unsigned, unsigned>
CGIOperandList::ParseOperandName(StringRef Op, bool AllowWholeOp) {
if (!Op.starts_with("$"))
PrintFatalError(TheDef->getLoc(),
@@ -242,7 +241,7 @@ CGIOperandList::ParseOperandName(StringRef Op, bool AllowWholeOp) {
// Check to see if this is $foo.bar.
StringRef::size_type DotIdx = OpName.find_first_of('.');
if (DotIdx != StringRef::npos) {
- SubOpName = OpName.substr(DotIdx+1);
+ SubOpName = OpName.substr(DotIdx + 1);
if (SubOpName.empty())
PrintFatalError(TheDef->getLoc(),
TheDef->getName() +
@@ -266,7 +265,7 @@ CGIOperandList::ParseOperandName(StringRef Op, bool AllowWholeOp) {
OpIdx = getOperandNamed(OpName);
- if (SubOpName.empty()) { // If no suboperand name was specified:
+ if (SubOpName.empty()) { // If no suboperand name was specified:
// If one was needed, throw.
if (OperandList[OpIdx].MINumOperands > 1 && !AllowWholeOp &&
SubOpName.empty())
@@ -299,82 +298,80 @@ CGIOperandList::ParseOperandName(StringRef Op, bool AllowWholeOp) {
return std::make_pair(0U, 0U);
}
-static void ParseConstraint(StringRef CStr, CGIOperandList &Ops,
- Record *Rec) {
+static void ParseConstraint(StringRef CStr, CGIOperandList &Ops, Record *Rec) {
// EARLY_CLOBBER: @early $reg
StringRef::size_type wpos = CStr.find_first_of(" \t");
StringRef::size_type start = CStr.find_first_not_of(" \t");
StringRef Tok = CStr.substr(start, wpos - start);
if (Tok == "@earlyclobber") {
- StringRef Name = CStr.substr(wpos+1);
+ StringRef Name = CStr.substr(wpos + 1);
wpos = Name.find_first_not_of(" \t");
if (wpos == StringRef::npos)
- PrintFatalError(
- Rec->getLoc(), "Illegal format for @earlyclobber constraint in '" +
- Rec->getName() + "': '" + CStr + "'");
+ PrintFatalError(Rec->getLoc(),
+ "Illegal format for @earlyclobber constraint in '" +
+ Rec->getName() + "': '" + CStr + "'");
Name = Name.substr(wpos);
- std::pair<unsigned,unsigned> Op = Ops.ParseOperandName(Name, false);
+ std::pair<unsigned, unsigned> Op = Ops.ParseOperandName(Name, false);
// Build the string for the operand
if (!Ops[Op.first].Constraints[Op.second].isNone())
- PrintFatalError(
- Rec->getLoc(), "Operand '" + Name + "' of '" + Rec->getName() +
- "' cannot have multiple constraints!");
+ PrintFatalError(Rec->getLoc(), "Operand '" + Name + "' of '" +
+ Rec->getName() +
+ "' cannot have multiple constraints!");
Ops[Op.first].Constraints[Op.second] =
- CGIOperandList::ConstraintInfo::getEarlyClobber();
+ CGIOperandList::ConstraintInfo::getEarlyClobber();
return;
}
// Only other constraint is "TIED_TO" for now.
StringRef::size_type pos = CStr.find_first_of('=');
if (pos == StringRef::npos)
- PrintFatalError(
- Rec->getLoc(), "Unrecognized constraint '" + CStr +
- "' in '" + Rec->getName() + "'");
+ PrintFatalError(Rec->getLoc(), "Unrecognized constraint '" + CStr +
+ "' in '" + Rec->getName() + "'");
start = CStr.find_first_not_of(" \t");
// TIED_TO: $src1 = $dst
wpos = CStr.find_first_of(" \t", start);
if (wpos == StringRef::npos || wpos > pos)
- PrintFatalError(
- Rec->getLoc(), "Illegal format for tied-to constraint in '" +
- Rec->getName() + "': '" + CStr + "'");
+ PrintFatalError(Rec->getLoc(),
+ "Illegal format for tied-to constraint in '" +
+ Rec->getName() + "': '" + CStr + "'");
StringRef LHSOpName = CStr.substr(start, wpos - start);
- std::pair<unsigned,unsigned> LHSOp = Ops.ParseOperandName(LHSOpName, false);
+ std::pair<unsigned, unsigned> LHSOp = Ops.ParseOperandName(LHSOpName, false);
wpos = CStr.find_first_not_of(" \t", pos + 1);
if (wpos == StringRef::npos)
- PrintFatalError(
- Rec->getLoc(), "Illegal format for tied-to constraint: '" + CStr + "'");
+ PrintFatalError(Rec->getLoc(),
+ "Illegal format for tied-to constraint: '" + CStr + "'");
StringRef RHSOpName = CStr.substr(wpos);
- std::pair<unsigned,unsigned> RHSOp = Ops.ParseOperandName(RHSOpName, false);
+ std::pair<unsigned, unsigned> RHSOp = Ops.ParseOperandName(RHSOpName, false);
// Sort the operands into order, which should put the output one
// first. But keep the original order, for use in diagnostics.
bool FirstIsDest = (LHSOp < RHSOp);
- std::pair<unsigned,unsigned> DestOp = (FirstIsDest ? LHSOp : RHSOp);
+ std::pair<unsigned, unsigned> DestOp = (FirstIsDest ? LHSOp : RHSOp);
StringRef DestOpName = (FirstIsDest ? LHSOpName : RHSOpName);
- std::pair<unsigned,unsigned> SrcOp = (FirstIsDest ? RHSOp : LHSOp);
+ std::pair<unsigned, unsigned> SrcOp = (FirstIsDest ? RHSOp : LHSOp);
StringRef SrcOpName = (FirstIsDest ? RHSOpName : LHSOpName);
// Ensure one operand is a def and the other is a use.
if (DestOp.first >= Ops.NumDefs)
- PrintFatalError(
- Rec->getLoc(), "Input operands '" + LHSOpName + "' and '" + RHSOpName +
- "' of '" + Rec->getName() + "' cannot be tied!");
+ PrintFatalError(Rec->getLoc(), "Input operands '" + LHSOpName + "' and '" +
+ RHSOpName + "' of '" + Rec->getName() +
+ "' cannot be tied!");
if (SrcOp.first < Ops.NumDefs)
- PrintFatalError(
- Rec->getLoc(), "Output operands '" + LHSOpName + "' and '" + RHSOpName +
- "' of '" + Rec->getName() + "' cannot be tied!");
+ PrintFatalError(Rec->getLoc(), "Output operands '" + LHSOpName + "' and '" +
+ RHSOpName + "' of '" + Rec->getName() +
+ "' cannot be tied!");
// The constraint has to go on the operand with higher index, i.e.
// the source one. Check there isn't another constraint there
// already.
if (!Ops[SrcOp.first].Constraints[SrcOp.second].isNone())
- PrintFatalError(
- Rec->getLoc(), "Operand '" + SrcOpName + "' of '" + Rec->getName() +
- "' cannot have multiple constraints!");
+ PrintFatalError(Rec->getLoc(), "Operand '" + SrcOpName + "' of '" +
+ Rec->getName() +
+ "' cannot have multiple constraints!");
unsigned DestFlatOpNo = Ops.getFlattenedOperandNumber(DestOp);
auto NewConstraint = CGIOperandList::ConstraintInfo::getTied(DestFlatOpNo);
@@ -384,16 +381,17 @@ static void ParseConstraint(StringRef CStr, CGIOperandList &Ops,
for (const CGIOperandList::OperandInfo &Op : Ops) {
for (unsigned i = 0; i < Op.MINumOperands; i++)
if (Op.Constraints[i] == NewConstraint)
- PrintFatalError(
- Rec->getLoc(), "Operand '" + DestOpName + "' of '" + Rec->getName() +
- "' cannot have multiple operands tied to it!");
+ PrintFatalError(Rec->getLoc(),
+ "Operand '" + DestOpName + "' of '" + Rec->getName() +
+ "' cannot have multiple operands tied to it!");
}
Ops[SrcOp.first].Constraints[SrcOp.second] = NewConstraint;
}
static void ParseConstraints(StringRef CStr, CGIOperandList &Ops, Record *Rec) {
- if (CStr.empty()) return;
+ if (CStr.empty())
+ return;
StringRef delims(",");
StringRef::size_type bidx, eidx;
@@ -413,15 +411,15 @@ void CGIOperandList::ProcessDisableEncoding(StringRef DisableEncoding) {
while (true) {
StringRef OpName;
std::tie(OpName, DisableEncoding) = getToken(DisableEncoding, " ,\t");
- if (OpName.empty()) break;
+ if (OpName.empty())
+ break;
// Figure out which operand this is.
- std::pair<unsigned,unsigned> Op = ParseOperandName(OpName, false);
+ std::pair<unsigned, unsigned> Op = ParseOperandName(OpName, false);
// Mark the operand as not-to-be encoded.
OperandList[Op.first].DoNotEncode[Op.second] = true;
}
-
}
//===----------------------------------------------------------------------===//
@@ -429,27 +427,27 @@ void CGIOperandList::ProcessDisableEncoding(StringRef DisableEncoding) {
//===----------------------------------------------------------------------===//
CodeGenInstruction::CodeGenInstruction(Record *R)
- : TheDef(R), Operands(R), InferredFrom(nullptr) {
+ : TheDef(R), Operands(R), InferredFrom(nullptr) {
Namespace = R->getValueAsString("Namespace");
AsmString = std::string(R->getValueAsString("AsmString"));
isPreISelOpcode = R->getValueAsBit("isPreISelOpcode");
- isReturn = R->getValueAsBit("isReturn");
+ isReturn = R->getValueAsBit("isReturn");
isEHScopeReturn = R->getValueAsBit("isEHScopeReturn");
- isBranch = R->getValueAsBit("isBranch");
+ isBranch = R->getValueAsBit("isBranch");
isIndirectBranch = R->getValueAsBit("isIndirectBranch");
- isCompare = R->getValueAsBit("isCompare");
- isMoveImm = R->getValueAsBit("isMoveImm");
- isMoveReg = R->getValueAsBit("isMoveReg");
- isBitcast = R->getValueAsBit("isBitcast");
- isSelect = R->getValueAsBit("isSelect");
- isBarrier = R->getValueAsBit("isBarrier");
- isCall = R->getValueAsBit("isCall");
- isAdd = R->getValueAsBit("isAdd");
- isTrap = R->getValueAsBit("isTrap");
+ isCompare = R->getValueAsBit("isCompare");
+ isMoveImm = R->getValueAsBit("isMoveImm");
+ isMoveReg = R->getValueAsBit("isMoveReg");
+ isBitcast = R->getValueAsBit("isBitcast");
+ isSelect = R->getValueAsBit("isSelect");
+ isBarrier = R->getValueAsBit("isBarrier");
+ isCall = R->getValueAsBit("isCall");
+ isAdd = R->getValueAsBit("isAdd");
+ isTrap = R->getValueAsBit("isTrap");
canFoldAsLoad = R->getValueAsBit("canFoldAsLoad");
- isPredicable = !R->getValueAsBit("isUnpredicable") && (
- Operands.isPredicable || R->getValueAsBit("isPredicable"));
+ isPredicable = !R->getValueAsBit("isUnpredicable") &&
+ (Operands.isPredicable || R->getValueAsBit("isPredicable"));
isConvertibleToThreeAddress = R->getValueAsBit("isConvertibleToThreeAddress");
isCommutable = R->getValueAsBit("isCommutable");
isTerminator = R->getValueAsBit("isTerminator");
@@ -457,7 +455,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R)
hasDelaySlot = R->getValueAsBit("hasDelaySlot");
usesCustomInserter = R->getValueAsBit("usesCustomInserter");
hasPostISelHook = R->getValueAsBit("hasPostISelHook");
- hasCtrlDep = R->getValueAsBit("hasCtrlDep");
+ hasCtrlDep = R->getValueAsBit("hasCtrlDep");
isNotDuplicable = R->getValueAsBit("isNotDuplicable");
isRegSequence = R->getValueAsBit("isRegSequence");
isExtractSubreg = R->getValueAsBit("isExtractSubreg");
@@ -469,9 +467,9 @@ CodeGenInstruction::CodeGenInstruction(Record *R)
isAuthenticated = R->getValueAsBit("isAuthenticated");
bool Unset;
- mayLoad = R->getValueAsBitOrUnset("mayLoad", Unset);
+ mayLoad = R->getValueAsBitOrUnset("mayLoad", Unset);
mayLoad_Unset = Unset;
- mayStore = R->getValueAsBitOrUnset("mayStore", Unset);
+ mayStore = R->getValueAsBitOrUnset("mayStore", Unset);
mayStore_Unset = Unset;
mayRaiseFPException = R->getValueAsBit("mayRaiseFPException");
hasSideEffects = R->getValueAsBitOrUnset("hasSideEffects", Unset);
@@ -494,8 +492,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R)
ParseConstraints(R->getValueAsString("Constraints"), Operands, R);
// Parse the DisableEncoding field.
- Operands.ProcessDisableEncoding(
- R->getValueAsString("DisableEncoding"));
+ Operands.ProcessDisableEncoding(R->getValueAsString("DisableEncoding"));
// First check for a ComplexDeprecationPredicate.
if (R->getValue("ComplexDeprecationPredicate")) {
@@ -516,25 +513,25 @@ CodeGenInstruction::CodeGenInstruction(Record *R)
/// HasOneImplicitDefWithKnownVT - If the instruction has at least one
/// implicit def and it has a known VT, return the VT, otherwise return
/// MVT::Other.
-MVT::SimpleValueType CodeGenInstruction::
-HasOneImplicitDefWithKnownVT(const CodeGenTarget &TargetInfo) const {
- if (ImplicitDefs.empty()) return MVT::Other;
+MVT::SimpleValueType CodeGenInstruction::HasOneImplicitDefWithKnownVT(
+ const CodeGenTarget &TargetInfo) const {
+ if (ImplicitDefs.empty())
+ return MVT::Other;
// Check to see if the first implicit def has a resolvable type.
Record *FirstImplicitDef = ImplicitDefs[0];
assert(FirstImplicitDef->isSubClassOf("Register"));
const std::vector<ValueTypeByHwMode> &RegVTs =
- TargetInfo.getRegisterVTs(FirstImplicitDef);
+ TargetInfo.getRegisterVTs(FirstImplicitDef);
if (RegVTs.size() == 1 && RegVTs[0].isSimple())
return RegVTs[0].getSimple().SimpleTy;
return MVT::Other;
}
-
/// FlattenAsmStringVariants - Flatten the specified AsmString to only
/// include text from the specified variant, returning the new string.
-std::string CodeGenInstruction::
-FlattenAsmStringVariants(StringRef Cur, unsigned Variant) {
+std::string CodeGenInstruction::FlattenAsmStringVariants(StringRef Cur,
+ unsigned Variant) {
std::string Res;
for (;;) {
@@ -542,8 +539,8 @@ FlattenAsmStringVariants(StringRef Cur, unsigned Variant) {
size_t VariantsStart = 0;
for (size_t e = Cur.size(); VariantsStart != e; ++VariantsStart)
if (Cur[VariantsStart] == '{' &&
- (VariantsStart == 0 || (Cur[VariantsStart-1] != '$' &&
- Cur[VariantsStart-1] != '\\')))
+ (VariantsStart == 0 ||
+ (Cur[VariantsStart - 1] != '$' && Cur[VariantsStart - 1] != '\\')))
break;
// Add the prefix to the result.
@@ -557,7 +554,7 @@ FlattenAsmStringVariants(StringRef Cur, unsigned Variant) {
size_t VariantsEnd = VariantsStart;
unsigned NestedBraces = 1;
for (size_t e = Cur.size(); VariantsEnd != e; ++VariantsEnd) {
- if (Cur[VariantsEnd] == '}' && Cur[VariantsEnd-1] != '\\') {
+ if (Cur[VariantsEnd] == '}' && Cur[VariantsEnd - 1] != '\\') {
if (--NestedBraces == 0)
break;
} else if (Cur[VariantsEnd] == '{')
diff --git a/llvm/utils/TableGen/Common/CodeGenInstruction.h b/llvm/utils/TableGen/Common/CodeGenInstruction.h
new file mode 100644
index 00000000000000..8d6c7313243435
--- /dev/null
+++ b/llvm/utils/TableGen/Common/CodeGenInstruction.h
@@ -0,0 +1,339 @@
+//===- CodeGenInstruction.h - Instruction Class Wrapper ---------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines a wrapper class for the 'Instruction' TableGen class.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_UTILS_TABLEGEN_CODEGENINSTRUCTION_H
+#define LLVM_UTILS_TABLEGEN_CODEGENINSTRUCTION_H
+
+#include "llvm/ADT/BitVector.h"
+#include "llvm/ADT/StringMap.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/CodeGenTypes/MachineValueType.h"
+#include <cassert>
+#include <string>
+#include <utility>
+#include <vector>
+
+namespace llvm {
+class Record;
+class DagInit;
+class CodeGenTarget;
+
+class CGIOperandList {
+public:
+ class ConstraintInfo {
+ enum { None, EarlyClobber, Tied } Kind = None;
+ unsigned OtherTiedOperand = 0;
+
+ public:
+ ConstraintInfo() = default;
+
+ static ConstraintInfo getEarlyClobber() {
+ ConstraintInfo I;
+ I.Kind = EarlyClobber;
+ I.OtherTiedOperand = 0;
+ return I;
+ }
+
+ static ConstraintInfo getTied(unsigned Op) {
+ ConstraintInfo I;
+ I.Kind = Tied;
+ I.OtherTiedOperand = Op;
+ return I;
+ }
+
+ bool isNone() const { return Kind == None; }
+ bool isEarlyClobber() const { return Kind == EarlyClobber; }
+ bool isTied() const { return Kind == Tied; }
+
+ unsigned getTiedOperand() const {
+ assert(isTied());
+ return OtherTiedOperand;
+ }
+
+ bool operator==(const ConstraintInfo &RHS) const {
+ if (Kind != RHS.Kind)
+ return false;
+ if (Kind == Tied && OtherTiedOperand != RHS.OtherTiedOperand)
+ return false;
+ return true;
+ }
+ bool operator!=(const ConstraintInfo &RHS) const { return !(*this == RHS); }
+ };
+
+ /// OperandInfo - The information we keep track of for each operand in the
+ /// operand list for a tablegen instruction.
+ struct OperandInfo {
+ /// Rec - The definition this operand is declared as.
+ ///
+ Record *Rec;
+
+ /// Name - If this operand was assigned a symbolic name, this is it,
+ /// otherwise, it's empty.
+ std::string Name;
+
+ /// The names of sub-operands, if given, otherwise empty.
+ std::vector<std::string> SubOpNames;
+
+ /// PrinterMethodName - The method used to print operands of this type in
+ /// the asmprinter.
+ std::string PrinterMethodName;
+
+ /// The method used to get the machine operand value for binary
+ /// encoding, per sub-operand. If empty, uses "getMachineOpValue".
+ std::vector<std::string> EncoderMethodNames;
+
+ /// OperandType - A value from MCOI::OperandType representing the type of
+ /// the operand.
+ std::string OperandType;
+
+ /// MIOperandNo - Currently (this is meant to be phased out), some logical
+ /// operands correspond to multiple MachineInstr operands. In the X86
+ /// target for example, one address operand is represented as 4
+ /// MachineOperands. Because of this, the operand number in the
+ /// OperandList may not match the MachineInstr operand num. Until it
+ /// does, this contains the MI operand index of this operand.
+ unsigned MIOperandNo;
+ unsigned MINumOperands; // The number of operands.
+
+ /// DoNotEncode - Bools are set to true in this vector for each operand in
+ /// the DisableEncoding list. These should not be emitted by the code
+ /// emitter.
+ BitVector DoNotEncode;
+
+ /// MIOperandInfo - Default MI operand type. Note an operand may be made
+ /// up of multiple MI operands.
+ DagInit *MIOperandInfo;
+
+ /// Constraint info for this operand. This operand can have pieces, so we
+ /// track constraint info for each.
+ std::vector<ConstraintInfo> Constraints;
+
+ OperandInfo(Record *R, const std::string &N, const std::string &PMN,
+ const std::string &OT, unsigned MION, unsigned MINO,
+ DagInit *MIOI)
+ : Rec(R), Name(N), SubOpNames(MINO), PrinterMethodName(PMN),
+ EncoderMethodNames(MINO), OperandType(OT), MIOperandNo(MION),
+ MINumOperands(MINO), DoNotEncode(MINO), MIOperandInfo(MIOI),
+ Constraints(MINO) {}
+
+ /// getTiedOperand - If this operand is tied to another one, return the
+ /// other operand number. Otherwise, return -1.
+ int getTiedRegister() const {
+ for (unsigned j = 0, e = Constraints.size(); j != e; ++j) {
+ const CGIOperandList::ConstraintInfo &CI = Constraints[j];
+ if (CI.isTied())
+ return CI.getTiedOperand();
+ }
+ return -1;
+ }
+ };
+
+ CGIOperandList(Record *D);
+
+ Record *TheDef; // The actual record containing this OperandList.
+
+ /// NumDefs - Number of def operands declared, this is the number of
+ /// elements in the instruction's (outs) list.
+ ///
+ unsigned NumDefs;
+
+ /// OperandList - The list of declared operands, along with their declared
+ /// type (which is a record).
+ std::vector<OperandInfo> OperandList;
+
+ /// SubOpAliases - List of alias names for suboperands.
+ StringMap<std::pair<unsigned, unsigned>> SubOpAliases;
+
+ // Information gleaned from the operand list.
+ bool isPredicable;
+ bool hasOptionalDef;
+ bool isVariadic;
+
+ // Provide transparent accessors to the operand list.
+ bool empty() const { return OperandList.empty(); }
+ unsigned size() const { return OperandList.size(); }
+ const OperandInfo &operator[](unsigned i) const { return OperandList[i]; }
+ OperandInfo &operator[](unsigned i) { return OperandList[i]; }
+ OperandInfo &back() { return OperandList.back(); }
+ const OperandInfo &back() const { return OperandList.back(); }
+
+ typedef std::vector<OperandInfo>::iterator iterator;
+ typedef std::vector<OperandInfo>::const_iterator const_iterator;
+ iterator begin() { return OperandList.begin(); }
+ const_iterator begin() const { return OperandList.begin(); }
+ iterator end() { return OperandList.end(); }
+ const_iterator end() const { return OperandList.end(); }
+
+ /// getOperandNamed - Return the index of the operand with the specified
+ /// non-empty name. If the instruction does not have an operand with the
+ /// specified name, abort.
+ unsigned getOperandNamed(StringRef Name) const;
+
+ /// hasOperandNamed - Query whether the instruction has an operand of the
+ /// given name. If so, return true and set OpIdx to the index of the
+ /// operand. Otherwise, return false.
+ bool hasOperandNamed(StringRef Name, unsigned &OpIdx) const;
+
+ bool hasSubOperandAlias(StringRef Name,
+ std::pair<unsigned, unsigned> &SubOp) const;
+
+ /// ParseOperandName - Parse an operand name like "$foo" or "$foo.bar",
+ /// where $foo is a whole operand and $foo.bar refers to a suboperand.
+ /// This aborts if the name is invalid. If AllowWholeOp is true, references
+ /// to operands with suboperands are allowed, otherwise not.
+ std::pair<unsigned, unsigned> ParseOperandName(StringRef Op,
+ bool AllowWholeOp = true);
+
+ /// getFlattenedOperandNumber - Flatten a operand/suboperand pair into a
+ /// flat machineinstr operand #.
+ unsigned getFlattenedOperandNumber(std::pair<unsigned, unsigned> Op) const {
+ return OperandList[Op.first].MIOperandNo + Op.second;
+ }
+
+ /// getSubOperandNumber - Unflatten a operand number into an
+ /// operand/suboperand pair.
+ std::pair<unsigned, unsigned> getSubOperandNumber(unsigned Op) const {
+ for (unsigned i = 0;; ++i) {
+ assert(i < OperandList.size() && "Invalid flat operand #");
+ if (OperandList[i].MIOperandNo + OperandList[i].MINumOperands > Op)
+ return std::make_pair(i, Op - OperandList[i].MIOperandNo);
+ }
+ }
+
+ /// isFlatOperandNotEmitted - Return true if the specified flat operand #
+ /// should not be emitted with the code emitter.
+ bool isFlatOperandNotEmitted(unsigned FlatOpNo) const {
+ std::pair<unsigned, unsigned> Op = getSubOperandNumber(FlatOpNo);
+ if (OperandList[Op.first].DoNotEncode.size() > Op.second)
+ return OperandList[Op.first].DoNotEncode[Op.second];
+ return false;
+ }
+
+ void ProcessDisableEncoding(StringRef Value);
+};
+
+class CodeGenInstruction {
+public:
+ Record *TheDef; // The actual record defining this instruction.
+ StringRef Namespace; // The namespace the instruction is in.
+
+ /// AsmString - The format string used to emit a .s file for the
+ /// instruction.
+ std::string AsmString;
+
+ /// Operands - This is information about the (ins) and (outs) list specified
+ /// to the instruction.
+ CGIOperandList Operands;
+
+ /// ImplicitDefs/ImplicitUses - These are lists of registers that are
+ /// implicitly defined and used by the instruction.
+ std::vector<Record *> ImplicitDefs, ImplicitUses;
+
+ // Various boolean values we track for the instruction.
+ bool isPreISelOpcode : 1;
+ bool isReturn : 1;
+ bool isEHScopeReturn : 1;
+ bool isBranch : 1;
+ bool isIndirectBranch : 1;
+ bool isCompare : 1;
+ bool isMoveImm : 1;
+ bool isMoveReg : 1;
+ bool isBitcast : 1;
+ bool isSelect : 1;
+ bool isBarrier : 1;
+ bool isCall : 1;
+ bool isAdd : 1;
+ bool isTrap : 1;
+ bool canFoldAsLoad : 1;
+ bool mayLoad : 1;
+ bool mayLoad_Unset : 1;
+ bool mayStore : 1;
+ bool mayStore_Unset : 1;
+ bool mayRaiseFPException : 1;
+ bool isPredicable : 1;
+ bool isConvertibleToThreeAddress : 1;
+ bool isCommutable : 1;
+ bool isTerminator : 1;
+ bool isReMaterializable : 1;
+ bool hasDelaySlot : 1;
+ bool usesCustomInserter : 1;
+ bool hasPostISelHook : 1;
+ bool hasCtrlDep : 1;
+ bool isNotDuplicable : 1;
+ bool hasSideEffects : 1;
+ bool hasSideEffects_Unset : 1;
+ bool isAsCheapAsAMove : 1;
+ bool hasExtraSrcRegAllocReq : 1;
+ bool hasExtraDefRegAllocReq : 1;
+ bool isCodeGenOnly : 1;
+ bool isPseudo : 1;
+ bool isMeta : 1;
+ bool isRegSequence : 1;
+ bool isExtractSubreg : 1;
+ bool isInsertSubreg : 1;
+ bool isConvergent : 1;
+ bool hasNoSchedulingInfo : 1;
+ bool FastISelShouldIgnore : 1;
+ bool hasChain : 1;
+ bool hasChain_Inferred : 1;
+ bool variadicOpsAreDefs : 1;
+ bool isAuthenticated : 1;
+
+ std::string DeprecatedReason;
+ bool HasComplexDeprecationPredicate;
+
+ /// Are there any undefined flags?
+ bool hasUndefFlags() const {
+ return mayLoad_Unset || mayStore_Unset || hasSideEffects_Unset;
+ }
+
+ // The record used to infer instruction flags, or NULL if no flag values
+ // have been inferred.
+ Record *InferredFrom;
+
+ CodeGenInstruction(Record *R);
+
+ /// HasOneImplicitDefWithKnownVT - If the instruction has at least one
+ /// implicit def and it has a known VT, return the VT, otherwise return
+ /// MVT::Other.
+ MVT::SimpleValueType
+ HasOneImplicitDefWithKnownVT(const CodeGenTarget &TargetInfo) const;
+
+ /// FlattenAsmStringVariants - Flatten the specified AsmString to only
+ /// include text from the specified variant, returning the new string.
+ static std::string FlattenAsmStringVariants(StringRef AsmString,
+ unsigned Variant);
+
+ // Is the specified operand in a generic instruction implicitly a pointer.
+ // This can be used on intructions that use typeN or ptypeN to identify
+ // operands that should be considered as pointers even though SelectionDAG
+ // didn't make a distinction between integer and pointers.
+ bool isInOperandAPointer(unsigned i) const {
+ return isOperandImpl("InOperandList", i, "IsPointer");
+ }
+
+ bool isOutOperandAPointer(unsigned i) const {
+ return isOperandImpl("OutOperandList", i, "IsPointer");
+ }
+
+ /// Check if the operand is required to be an immediate.
+ bool isInOperandImmArg(unsigned i) const {
+ return isOperandImpl("InOperandList", i, "IsImmediate");
+ }
+
+private:
+ bool isOperandImpl(StringRef OpListName, unsigned i,
+ StringRef PropertyName) const;
+};
+} // namespace llvm
+
+#endif
diff --git a/llvm/utils/TableGen/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
similarity index 92%
rename from llvm/utils/TableGen/CodeGenRegisters.cpp
rename to llvm/utils/TableGen/Common/CodeGenRegisters.cpp
index d1abdb74ea4a98..4b8954059d5587 100644
--- a/llvm/utils/TableGen/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -48,7 +48,7 @@ using namespace llvm;
//===----------------------------------------------------------------------===//
CodeGenSubRegIndex::CodeGenSubRegIndex(Record *R, unsigned Enum)
- : TheDef(R), EnumValue(Enum), AllSuperRegsCovered(true), Artificial(true) {
+ : TheDef(R), EnumValue(Enum), AllSuperRegsCovered(true), Artificial(true) {
Name = std::string(R->getName());
if (R->getValue("Namespace"))
Namespace = std::string(R->getValueAsString("Namespace"));
@@ -74,7 +74,7 @@ void CodeGenSubRegIndex::updateComponents(CodeGenRegBank &RegBank) {
if (!TheDef)
return;
- std::vector<Record*> Comps = TheDef->getValueAsListOfDefs("ComposedOf");
+ std::vector<Record *> Comps = TheDef->getValueAsListOfDefs("ComposedOf");
if (!Comps.empty()) {
if (Comps.size() != 2)
PrintFatalError(TheDef->getLoc(),
@@ -86,13 +86,13 @@ void CodeGenSubRegIndex::updateComponents(CodeGenRegBank &RegBank) {
PrintFatalError(TheDef->getLoc(), "Ambiguous ComposedOf entries");
}
- std::vector<Record*> Parts =
- TheDef->getValueAsListOfDefs("CoveringSubRegIndices");
+ std::vector<Record *> Parts =
+ TheDef->getValueAsListOfDefs("CoveringSubRegIndices");
if (!Parts.empty()) {
if (Parts.size() < 2)
PrintFatalError(TheDef->getLoc(),
"CoveredBySubRegs must have two or more entries");
- SmallVector<CodeGenSubRegIndex*, 8> IdxParts;
+ SmallVector<CodeGenSubRegIndex *, 8> IdxParts;
for (Record *Part : Parts)
IdxParts.push_back(RegBank.getSubRegIdx(Part));
setConcatenationOf(IdxParts);
@@ -117,17 +117,19 @@ LaneBitmask CodeGenSubRegIndex::computeLaneMask() const {
}
void CodeGenSubRegIndex::setConcatenationOf(
- ArrayRef<CodeGenSubRegIndex*> Parts) {
+ ArrayRef<CodeGenSubRegIndex *> Parts) {
if (ConcatenationOf.empty())
ConcatenationOf.assign(Parts.begin(), Parts.end());
else
- assert(std::equal(Parts.begin(), Parts.end(),
- ConcatenationOf.begin()) && "parts consistent");
+ assert(std::equal(Parts.begin(), Parts.end(), ConcatenationOf.begin()) &&
+ "parts consistent");
}
void CodeGenSubRegIndex::computeConcatTransitiveClosure() {
- for (SmallVectorImpl<CodeGenSubRegIndex*>::iterator
- I = ConcatenationOf.begin(); I != ConcatenationOf.end(); /*empty*/) {
+ for (SmallVectorImpl<CodeGenSubRegIndex *>::iterator I =
+ ConcatenationOf.begin();
+ I != ConcatenationOf.end();
+ /*empty*/) {
CodeGenSubRegIndex *SubIdx = *I;
SubIdx->computeConcatTransitiveClosure();
#ifndef NDEBUG
@@ -160,8 +162,8 @@ CodeGenRegister::CodeGenRegister(Record *R, unsigned Enum)
}
void CodeGenRegister::buildObjectGraph(CodeGenRegBank &RegBank) {
- std::vector<Record*> SRIs = TheDef->getValueAsListOfDefs("SubRegIndices");
- std::vector<Record*> SRs = TheDef->getValueAsListOfDefs("SubRegs");
+ std::vector<Record *> SRIs = TheDef->getValueAsListOfDefs("SubRegIndices");
+ std::vector<Record *> SRs = TheDef->getValueAsListOfDefs("SubRegs");
if (SRIs.size() != SRs.size())
PrintFatalError(TheDef->getLoc(),
@@ -182,7 +184,7 @@ void CodeGenRegister::buildObjectGraph(CodeGenRegBank &RegBank) {
// Add ad hoc alias links. This is a symmetric relationship between two
// registers, so build a symmetric graph by adding links in both ends.
- std::vector<Record*> Aliases = TheDef->getValueAsListOfDefs("Aliases");
+ std::vector<Record *> Aliases = TheDef->getValueAsListOfDefs("Aliases");
for (Record *Alias : Aliases) {
CodeGenRegister *Reg = RegBank.getReg(Alias);
ExplicitAliases.push_back(Reg);
@@ -204,8 +206,8 @@ class RegUnitIterator {
static CodeGenRegister::RegUnitList Sentinel;
public:
- RegUnitIterator(const CodeGenRegister::Vec &Regs):
- RegI(Regs.begin()), RegE(Regs.end()) {
+ RegUnitIterator(const CodeGenRegister::Vec &Regs)
+ : RegI(Regs.begin()), RegE(Regs.end()) {
if (RegI == RegE) {
UnitI = Sentinel.end();
@@ -219,9 +221,15 @@ class RegUnitIterator {
bool isValid() const { return UnitI != UnitE; }
- unsigned operator* () const { assert(isValid()); return *UnitI; }
+ unsigned operator*() const {
+ assert(isValid());
+ return *UnitI;
+ }
- const CodeGenRegister *getReg() const { assert(isValid()); return *RegI; }
+ const CodeGenRegister *getReg() const {
+ assert(isValid());
+ return *RegI;
+ }
/// Preincrement. Move to the next unit.
void operator++() {
@@ -280,14 +288,15 @@ CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {
Idx->Artificial = false;
if (!SubRegs.insert(std::make_pair(Idx, SR)).second)
PrintFatalError(TheDef->getLoc(), "SubRegIndex " + Idx->getName() +
- " appears twice in Register " + getName());
+ " appears twice in Register " +
+ getName());
// Map explicit sub-registers first, so the names take precedence.
// The inherited sub-registers are mapped below.
SubReg2Idx.insert(std::make_pair(SR, Idx));
}
// Keep track of inherited subregs and how they can be reached.
- SmallPtrSet<CodeGenRegister*, 8> Orphans;
+ SmallPtrSet<CodeGenRegister *, 8> Orphans;
// Clone inherited subregs and place duplicate entries in Orphans.
// Here the order is important - earlier subregs take precedence.
@@ -305,7 +314,7 @@ CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {
// If dsub_2 has ComposedOf = [qsub_1, dsub_0], and this register has a
// qsub_1 subreg, add a dsub_2 subreg. Keep growing Indices and process
// expanded subreg indices recursively.
- SmallVector<CodeGenSubRegIndex*, 8> Indices = ExplicitSubRegIndices;
+ SmallVector<CodeGenSubRegIndex *, 8> Indices = ExplicitSubRegIndices;
for (unsigned i = 0; i != Indices.size(); ++i) {
CodeGenSubRegIndex *Idx = Indices[i];
const CodeGenSubRegIndex::CompMap &Comps = Idx->getComposites();
@@ -350,7 +359,8 @@ CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {
const SubRegMap &Map = SR->computeSubRegs(RegBank);
for (const auto &SubReg : Map)
if (Orphans.erase(SubReg.second))
- SubRegs[RegBank.getCompositeSubRegIndex(Idx, SubReg.first)] = SubReg.second;
+ SubRegs[RegBank.getCompositeSubRegIndex(Idx, SubReg.first)] =
+ SubReg.second;
}
// Compute the inverse SubReg -> Idx map.
@@ -360,7 +370,7 @@ CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {
if (TheDef)
Loc = TheDef->getLoc();
PrintFatalError(Loc, "Register " + getName() +
- " has itself as a sub-register");
+ " has itself as a sub-register");
}
// Compute AllSuperRegsCovered.
@@ -368,17 +378,18 @@ CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {
SubReg.first->AllSuperRegsCovered = false;
// Ensure that every sub-register has a unique name.
- DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*>::iterator Ins =
- SubReg2Idx.insert(std::make_pair(SubReg.second, SubReg.first)).first;
+ DenseMap<const CodeGenRegister *, CodeGenSubRegIndex *>::iterator Ins =
+ SubReg2Idx.insert(std::make_pair(SubReg.second, SubReg.first)).first;
if (Ins->second == SubReg.first)
continue;
// Trouble: Two different names for SubReg.second.
ArrayRef<SMLoc> Loc;
if (TheDef)
Loc = TheDef->getLoc();
- PrintFatalError(Loc, "Sub-register can't have two names: " +
- SubReg.second->getName() + " available as " +
- SubReg.first->getName() + " and " + Ins->second->getName());
+ PrintFatalError(
+ Loc, "Sub-register can't have two names: " + SubReg.second->getName() +
+ " available as " + SubReg.first->getName() + " and " +
+ Ins->second->getName());
}
// Derive possible names for sub-register concatenations from any explicit
@@ -392,7 +403,7 @@ CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {
continue;
// SR is composed of multiple sub-regs. Find their names in this register.
- SmallVector<CodeGenSubRegIndex*, 8> Parts;
+ SmallVector<CodeGenSubRegIndex *, 8> Parts;
for (unsigned j = 0, e = SR->ExplicitSubRegs.size(); j != e; ++j) {
CodeGenSubRegIndex &I = *SR->ExplicitSubRegIndices[j];
if (!I.Artificial)
@@ -464,8 +475,8 @@ CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) {
void CodeGenRegister::computeSecondarySubRegs(CodeGenRegBank &RegBank) {
SmallVector<SubRegMap::value_type, 8> NewSubRegs;
- std::queue<std::pair<CodeGenSubRegIndex*,CodeGenRegister*>> SubRegQueue;
- for (std::pair<CodeGenSubRegIndex*,CodeGenRegister*> P : SubRegs)
+ std::queue<std::pair<CodeGenSubRegIndex *, CodeGenRegister *>> SubRegQueue;
+ for (std::pair<CodeGenSubRegIndex *, CodeGenRegister *> P : SubRegs)
SubRegQueue.push(P);
// Look at the leading super-registers of each sub-register. Those are the
@@ -479,7 +490,7 @@ void CodeGenRegister::computeSecondarySubRegs(CodeGenRegBank &RegBank) {
const CodeGenRegister::SuperRegList &Leads = SubReg->LeadingSuperRegs;
for (unsigned i = 0, e = Leads.size(); i != e; ++i) {
- CodeGenRegister *Cand = const_cast<CodeGenRegister*>(Leads[i]);
+ CodeGenRegister *Cand = const_cast<CodeGenRegister *>(Leads[i]);
// Already got this sub-register?
if (Cand == this || getSubRegIndex(Cand))
continue;
@@ -488,7 +499,7 @@ void CodeGenRegister::computeSecondarySubRegs(CodeGenRegBank &RegBank) {
"Super-register has no sub-registers");
if (Cand->ExplicitSubRegs.size() == 1)
continue;
- SmallVector<CodeGenSubRegIndex*, 8> Parts;
+ SmallVector<CodeGenSubRegIndex *, 8> Parts;
// We know that the first component is (SubRegIdx,SubReg). However we
// may still need to split it into smaller subregister parts.
assert(Cand->ExplicitSubRegs[0] == SubReg && "LeadingSuperRegs correct");
@@ -513,7 +524,7 @@ void CodeGenRegister::computeSecondarySubRegs(CodeGenRegBank &RegBank) {
// Each part of Cand is a sub-register of this. Make the full Cand also
// a sub-register with a concatenated sub-register index.
CodeGenSubRegIndex *Concat = RegBank.getConcatSubRegIndex(Parts);
- std::pair<CodeGenSubRegIndex*,CodeGenRegister*> NewSubReg =
+ std::pair<CodeGenSubRegIndex *, CodeGenRegister *> NewSubReg =
std::make_pair(Concat, Cand);
if (!SubRegs.insert(NewSubReg).second)
@@ -570,9 +581,8 @@ void CodeGenRegister::computeSuperRegs(CodeGenRegBank &RegBank) {
TopoSig = RegBank.getTopoSig(Id);
}
-void
-CodeGenRegister::addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet,
- CodeGenRegBank &RegBank) const {
+void CodeGenRegister::addSubRegsPreOrder(
+ SetVector<const CodeGenRegister *> &OSet, CodeGenRegBank &RegBank) const {
assert(SubRegsComplete && "Must precompute sub-registers");
for (unsigned i = 0, e = ExplicitSubRegs.size(); i != e; ++i) {
CodeGenRegister *SR = ExplicitSubRegs[i];
@@ -611,7 +621,7 @@ struct TupleExpander : SetTheory::Expander {
: SynthDefs(SynthDefs) {}
void expand(SetTheory &ST, Record *Def, SetTheory::RecSet &Elts) override {
- std::vector<Record*> Indices = Def->getValueAsListOfDefs("SubRegIndices");
+ std::vector<Record *> Indices = Def->getValueAsListOfDefs("SubRegIndices");
unsigned Dim = Indices.size();
ListInit *SubRegs = Def->getValueAsListInit("SubRegs");
if (Dim != SubRegs->size())
@@ -635,17 +645,18 @@ struct TupleExpander : SetTheory::Expander {
Record *RegisterCl = Def->getRecords().getClass("Register");
RecTy *RegisterRecTy = RecordRecTy::get(RegisterCl);
std::vector<StringRef> RegNames =
- Def->getValueAsListOfStrings("RegAsmNames");
+ Def->getValueAsListOfStrings("RegAsmNames");
// Zip them up.
RecordKeeper &RK = Def->getRecords();
for (unsigned n = 0; n != Length; ++n) {
std::string Name;
Record *Proto = Lists[0][n];
- std::vector<Init*> Tuple;
+ std::vector<Init *> Tuple;
for (unsigned i = 0; i != Dim; ++i) {
Record *Reg = Lists[i][n];
- if (i) Name += '_';
+ if (i)
+ Name += '_';
Name += Reg->getName();
Tuple.push_back(DefInit::get(Reg));
}
@@ -660,7 +671,7 @@ struct TupleExpander : SetTheory::Expander {
if (RegNames.size() <= n)
PrintFatalError(Def->getLoc(),
"Register tuple definition missing name for '" +
- Name + "'.");
+ Name + "'.");
AsmName = StringInit::get(RK, RegNames[n]);
}
@@ -703,15 +714,13 @@ struct TupleExpander : SetTheory::Expander {
RV.setValue(BitInit::get(RK, true));
// Copy fields from the RegisterTuples def.
- if (Field == "SubRegIndices" ||
- Field == "CompositeIndices") {
+ if (Field == "SubRegIndices" || Field == "CompositeIndices") {
NewReg->addValue(*Def->getValue(Field));
continue;
}
// Some fields get their default uninitialized value.
- if (Field == "DwarfNumbers" ||
- Field == "DwarfAlias" ||
+ if (Field == "DwarfNumbers" || Field == "DwarfAlias" ||
Field == "Aliases") {
if (const RecordVal *DefRV = RegisterCl->getValue(Field))
NewReg->addValue(*DefRV);
@@ -740,7 +749,7 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
: TheDef(R), Name(std::string(R->getName())),
TopoSigs(RegBank.getNumTopoSigs()), EnumValue(-1), TSFlags(0) {
GeneratePressureSet = R->getValueAsBit("GeneratePressureSet");
- std::vector<Record*> TypeList = R->getValueAsListOfDefs("RegTypes");
+ std::vector<Record *> TypeList = R->getValueAsListOfDefs("RegTypes");
if (TypeList.empty())
PrintFatalError(R->getLoc(), "RegTypes list must not be empty!");
for (unsigned i = 0, e = TypeList.size(); i != e; ++i) {
@@ -779,7 +788,7 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
Order.pop_back();
if (!contains(Reg))
PrintFatalError(R->getLoc(), " AltOrder register " + Reg->getName() +
- " is not a class member");
+ " is not a class member");
}
}
@@ -793,8 +802,8 @@ CodeGenRegisterClass::CodeGenRegisterClass(CodeGenRegBank &RegBank, Record *R)
"Impossible to determine register size");
if (!RSI.hasDefault()) {
RegSizeInfo RI;
- RI.RegSize = RI.SpillSize = Size ? Size
- : VTs[0].getSimple().getSizeInBits();
+ RI.RegSize = RI.SpillSize =
+ Size ? Size : VTs[0].getSimple().getSizeInBits();
RI.SpillAlignment = R->getValueAsInt("Alignment");
RSI.insertRegSizeForMode(DefaultMode, RI);
}
@@ -890,7 +899,7 @@ bool CodeGenRegisterClass::contains(const CodeGenRegister *Reg) const {
deref<std::less<>>());
}
-unsigned CodeGenRegisterClass::getWeight(const CodeGenRegBank& RegBank) const {
+unsigned CodeGenRegisterClass::getWeight(const CodeGenRegBank &RegBank) const {
if (TheDef && !TheDef->isValueUnset("Weight"))
return TheDef->getValueAsInt("Weight");
@@ -902,19 +911,19 @@ unsigned CodeGenRegisterClass::getWeight(const CodeGenRegBank& RegBank) const {
namespace llvm {
- raw_ostream &operator<<(raw_ostream &OS, const CodeGenRegisterClass::Key &K) {
- OS << "{ " << K.RSI;
- for (const auto R : *K.Members)
- OS << ", " << R->getName();
- return OS << " }";
- }
+raw_ostream &operator<<(raw_ostream &OS, const CodeGenRegisterClass::Key &K) {
+ OS << "{ " << K.RSI;
+ for (const auto R : *K.Members)
+ OS << ", " << R->getName();
+ return OS << " }";
+}
} // end namespace llvm
// This is a simple lexicographical order that can be used to search for sets.
// It is not the same as the topological order provided by TopoOrderRC.
-bool CodeGenRegisterClass::Key::
-operator<(const CodeGenRegisterClass::Key &B) const {
+bool CodeGenRegisterClass::Key::operator<(
+ const CodeGenRegisterClass::Key &B) const {
assert(Members && B.Members);
return std::tie(*Members, RSI) < std::tie(*B.Members, B.RSI);
}
@@ -1066,7 +1075,7 @@ CodeGenRegisterClass::getMatchingSubClassWithSubRegs(
// Find all the subreg classes and order them by size too.
std::vector<std::pair<CodeGenRegisterClass *, BitVector>> SuperRegClasses;
- for (auto &RC: RegClasses) {
+ for (auto &RC : RegClasses) {
BitVector SuperRegClassesBV(RegClasses.size());
RC.getSuperRegClasses(SubIdx, SuperRegClassesBV);
if (SuperRegClassesBV.any())
@@ -1129,8 +1138,8 @@ void CodeGenRegisterClass::getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
}
// Populate a unique sorted list of units from a register set.
-void CodeGenRegisterClass::buildRegUnitSet(const CodeGenRegBank &RegBank,
- std::vector<unsigned> &RegUnits) const {
+void CodeGenRegisterClass::buildRegUnitSet(
+ const CodeGenRegBank &RegBank, std::vector<unsigned> &RegUnits) const {
std::vector<unsigned> TmpUnits;
for (RegUnitIterator UnitI(Members); UnitI.isValid(); ++UnitI) {
const RegUnit &RU = RegBank.getRegUnit(*UnitI);
@@ -1158,7 +1167,8 @@ CodeGenRegisterCategory::CodeGenRegisterCategory(CodeGenRegBank &RegBank,
//===----------------------------------------------------------------------===//
CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records,
- const CodeGenHwModes &Modes) : CGH(Modes) {
+ const CodeGenHwModes &Modes)
+ : CGH(Modes) {
// Configure register Sets to understand register classes and tuples.
Sets.addFieldExpander("RegisterClass", "MemberList");
Sets.addFieldExpander("CalleeSavedRegs", "SaveList");
@@ -1167,7 +1177,7 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records,
// Read in the user-defined (named) sub-register indices.
// More indices will be synthesized later.
- std::vector<Record*> SRIs = Records.getAllDerivedDefinitions("SubRegIndex");
+ std::vector<Record *> SRIs = Records.getAllDerivedDefinitions("SubRegIndex");
llvm::sort(SRIs, LessRecord());
for (unsigned i = 0, e = SRIs.size(); i != e; ++i)
getSubRegIdx(SRIs[i]);
@@ -1238,8 +1248,9 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records,
SRI.computeConcatTransitiveClosure();
if (!SRI.ConcatenationOf.empty())
ConcatIdx.insert(std::make_pair(
- SmallVector<CodeGenSubRegIndex*,8>(SRI.ConcatenationOf.begin(),
- SRI.ConcatenationOf.end()), &SRI));
+ SmallVector<CodeGenSubRegIndex *, 8>(SRI.ConcatenationOf.begin(),
+ SRI.ConcatenationOf.end()),
+ &SRI));
}
// Infer even more sub-registers by combining leading super-registers.
@@ -1269,7 +1280,7 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records,
NumNativeRegUnits = RegUnits.size();
// Read in register class definitions.
- std::vector<Record*> RCs = Records.getAllDerivedDefinitions("RegisterClass");
+ std::vector<Record *> RCs = Records.getAllDerivedDefinitions("RegisterClass");
if (RCs.empty())
PrintFatalError("No 'RegisterClass' subclasses defined!");
@@ -1299,8 +1310,8 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records,
}
// Create a synthetic CodeGenSubRegIndex without a corresponding Record.
-CodeGenSubRegIndex*
-CodeGenRegBank::createSubRegIndex(StringRef Name, StringRef Namespace) {
+CodeGenSubRegIndex *CodeGenRegBank::createSubRegIndex(StringRef Name,
+ StringRef Namespace) {
SubRegIndices.emplace_back(Name, Namespace, SubRegIndices.size() + 1);
return &SubRegIndices.back();
}
@@ -1315,7 +1326,7 @@ CodeGenSubRegIndex *CodeGenRegBank::getSubRegIdx(Record *Def) {
}
const CodeGenSubRegIndex *
-CodeGenRegBank::findSubRegIdx(const Record* Def) const {
+CodeGenRegBank::findSubRegIdx(const Record *Def) const {
return Def2SubRegIdx.lookup(Def);
}
@@ -1339,7 +1350,7 @@ void CodeGenRegBank::addToMaps(CodeGenRegisterClass *RC) {
}
// Create a synthetic sub-class if it is missing.
-CodeGenRegisterClass*
+CodeGenRegisterClass *
CodeGenRegBank::getOrCreateSubClass(const CodeGenRegisterClass *RC,
const CodeGenRegister::Vec *Members,
StringRef Name) {
@@ -1362,7 +1373,7 @@ CodeGenRegisterClass *CodeGenRegBank::getRegClass(const Record *Def) const {
PrintFatalError(Def->getLoc(), "Not a known RegisterClass!");
}
-CodeGenSubRegIndex*
+CodeGenSubRegIndex *
CodeGenRegBank::getCompositeSubRegIndex(CodeGenSubRegIndex *A,
CodeGenSubRegIndex *B) {
// Look for an existing entry.
@@ -1377,8 +1388,8 @@ CodeGenRegBank::getCompositeSubRegIndex(CodeGenSubRegIndex *A,
return Comp;
}
-CodeGenSubRegIndex *CodeGenRegBank::
-getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8> &Parts) {
+CodeGenSubRegIndex *CodeGenRegBank::getConcatSubRegIndex(
+ const SmallVector<CodeGenSubRegIndex *, 8> &Parts) {
assert(Parts.size() > 1 && "Need two parts to concatenate");
#ifndef NDEBUG
for (CodeGenSubRegIndex *Idx : Parts) {
@@ -1419,26 +1430,26 @@ getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8> &Parts) {
}
void CodeGenRegBank::computeComposites() {
- using RegMap = std::map<const CodeGenRegister*, const CodeGenRegister*>;
+ using RegMap = std::map<const CodeGenRegister *, const CodeGenRegister *>;
// Subreg -> { Reg->Reg }, where the right-hand side is the mapping from
// register to (sub)register associated with the action of the left-hand
// side subregister.
- std::map<const CodeGenSubRegIndex*, RegMap> SubRegAction;
+ std::map<const CodeGenSubRegIndex *, RegMap> SubRegAction;
for (const CodeGenRegister &R : Registers) {
const CodeGenRegister::SubRegMap &SM = R.getSubRegs();
- for (std::pair<const CodeGenSubRegIndex*, const CodeGenRegister*> P : SM)
+ for (std::pair<const CodeGenSubRegIndex *, const CodeGenRegister *> P : SM)
SubRegAction[P.first].insert({&R, P.second});
}
// Calculate the composition of two subregisters as compositions of their
// associated actions.
- auto compose = [&SubRegAction] (const CodeGenSubRegIndex *Sub1,
- const CodeGenSubRegIndex *Sub2) {
+ auto compose = [&SubRegAction](const CodeGenSubRegIndex *Sub1,
+ const CodeGenSubRegIndex *Sub2) {
RegMap C;
const RegMap &Img1 = SubRegAction.at(Sub1);
const RegMap &Img2 = SubRegAction.at(Sub2);
- for (std::pair<const CodeGenRegister*, const CodeGenRegister*> P : Img1) {
+ for (std::pair<const CodeGenRegister *, const CodeGenRegister *> P : Img1) {
auto F = Img2.find(P.second);
if (F != Img2.end())
C.insert({P.first, F->second});
@@ -1447,13 +1458,13 @@ void CodeGenRegBank::computeComposites() {
};
// Check if the two maps agree on the intersection of their domains.
- auto agree = [] (const RegMap &Map1, const RegMap &Map2) {
+ auto agree = [](const RegMap &Map1, const RegMap &Map2) {
// Technically speaking, an empty map agrees with any other map, but
// this could flag false positives. We're interested in non-vacuous
// agreements.
if (Map1.empty() || Map2.empty())
return false;
- for (std::pair<const CodeGenRegister*, const CodeGenRegister*> P : Map1) {
+ for (std::pair<const CodeGenRegister *, const CodeGenRegister *> P : Map1) {
auto F = Map2.find(P.first);
if (F == Map2.end() || P.second != F->second)
return false;
@@ -1461,9 +1472,9 @@ void CodeGenRegBank::computeComposites() {
return true;
};
- using CompositePair = std::pair<const CodeGenSubRegIndex*,
- const CodeGenSubRegIndex*>;
- SmallSet<CompositePair,4> UserDefined;
+ using CompositePair =
+ std::pair<const CodeGenSubRegIndex *, const CodeGenSubRegIndex *>;
+ SmallSet<CompositePair, 4> UserDefined;
for (const CodeGenSubRegIndex &Idx : SubRegIndices)
for (auto P : Idx.getComposites())
UserDefined.insert(std::make_pair(&Idx, P.first));
@@ -1528,8 +1539,8 @@ void CodeGenRegBank::computeSubRegLaneMasks() {
if (Idx.getComposites().empty()) {
if (Bit > LaneBitmask::BitWidth) {
PrintFatalError(
- Twine("Ran out of lanemask bits to represent subregister ")
- + Idx.getName());
+ Twine("Ran out of lanemask bits to represent subregister ") +
+ Idx.getName());
}
Idx.LaneMask = LaneBitmask::getLane(Bit);
++Bit;
@@ -1556,7 +1567,7 @@ void CodeGenRegBank::computeSubRegLaneMasks() {
unsigned DstBit = Idx.LaneMask.getHighestLane();
assert(Idx.LaneMask == LaneBitmask::getLane(DstBit) &&
"Must be a leaf subregister");
- MaskRolPair MaskRol = { LaneBitmask::getLane(0), (uint8_t)DstBit };
+ MaskRolPair MaskRol = {LaneBitmask::getLane(0), (uint8_t)DstBit};
LaneTransforms.push_back(MaskRol);
} else {
// Go through all leaf subregisters and find the ones that compose with
@@ -1571,7 +1582,7 @@ void CodeGenRegBank::computeSubRegLaneMasks() {
// Replicate the behaviour from the lane mask generation loop above.
unsigned SrcBit = NextBit;
LaneBitmask SrcMask = LaneBitmask::getLane(SrcBit);
- if (NextBit < LaneBitmask::BitWidth-1)
+ if (NextBit < LaneBitmask::BitWidth - 1)
++NextBit;
assert(Idx2.LaneMask == SrcMask);
@@ -1586,8 +1597,8 @@ void CodeGenRegBank::computeSubRegLaneMasks() {
// Create Mask+Rotate operation and merge with existing ops if possible.
unsigned DstBit = Composite->LaneMask.getHighestLane();
int Shift = DstBit - SrcBit;
- uint8_t RotateLeft = Shift >= 0 ? (uint8_t)Shift
- : LaneBitmask::BitWidth + Shift;
+ uint8_t RotateLeft =
+ Shift >= 0 ? (uint8_t)Shift : LaneBitmask::BitWidth + Shift;
for (auto &I : LaneTransforms) {
if (I.RotateLeft == RotateLeft) {
I.Mask |= SrcMask;
@@ -1595,7 +1606,7 @@ void CodeGenRegBank::computeSubRegLaneMasks() {
}
}
if (SrcMask.any()) {
- MaskRolPair MaskRol = { SrcMask, RotateLeft };
+ MaskRolPair MaskRol = {SrcMask, RotateLeft};
LaneTransforms.push_back(MaskRol);
}
}
@@ -1611,7 +1622,7 @@ void CodeGenRegBank::computeSubRegLaneMasks() {
// in a sequence with 0 entries we can just pick any other. Choose
// Mask 0xffffffff with Rotation 0.
if (LaneTransforms.size() == 0) {
- MaskRolPair P = { LaneBitmask::getAll(), 0 };
+ MaskRolPair P = {LaneBitmask::getAll(), 0};
LaneTransforms.push_back(P);
}
}
@@ -1679,7 +1690,7 @@ struct UberRegSet {
//
// UberRegSets[0] is a special non-allocatable set.
static void computeUberSets(std::vector<UberRegSet> &UberSets,
- std::vector<UberRegSet*> &RegSets,
+ std::vector<UberRegSet *> &RegSets,
CodeGenRegBank &RegBank) {
const auto &Registers = RegBank.getRegisters();
@@ -1742,7 +1753,8 @@ static void computeUberWeights(std::vector<UberRegSet> &UberSets,
CodeGenRegBank &RegBank) {
// Skip the first unallocatable set.
for (std::vector<UberRegSet>::iterator I = std::next(UberSets.begin()),
- E = UberSets.end(); I != E; ++I) {
+ E = UberSets.end();
+ I != E; ++I) {
// Initialize all unit weights in this set, and remember the max units/reg.
const CodeGenRegister *Reg = nullptr;
@@ -1797,7 +1809,7 @@ static void computeUberWeights(std::vector<UberRegSet> &UberSets,
// - induces recomputation of UberWeights.
static bool normalizeWeight(CodeGenRegister *Reg,
std::vector<UberRegSet> &UberSets,
- std::vector<UberRegSet*> &RegSets,
+ std::vector<UberRegSet *> &RegSets,
BitVector &NormalRegs,
CodeGenRegister::RegUnitList &NormalUnits,
CodeGenRegBank &RegBank) {
@@ -1830,15 +1842,14 @@ static bool normalizeWeight(CodeGenRegister *Reg,
// for this register, has not been used to normalize a subregister's set,
// and has not already been used to singularly determine this UberRegSet.
unsigned AdjustUnit = *Reg->getRegUnits().begin();
- if (Reg->getRegUnits().count() != 1
- || hasRegUnit(NormalUnits, AdjustUnit)
- || hasRegUnit(UberSet->SingularDeterminants, AdjustUnit)) {
+ if (Reg->getRegUnits().count() != 1 ||
+ hasRegUnit(NormalUnits, AdjustUnit) ||
+ hasRegUnit(UberSet->SingularDeterminants, AdjustUnit)) {
// We don't have an adjustable unit, so adopt a new one.
AdjustUnit = RegBank.newRegUnit(UberSet->Weight - RegWeight);
Reg->adoptRegUnit(AdjustUnit);
// Adopting a unit does not immediately require recomputing set weights.
- }
- else {
+ } else {
// Adjust the existing single unit.
if (!RegBank.getRegUnit(AdjustUnit).Artificial)
RegBank.increaseRegUnitWeight(AdjustUnit, UberSet->Weight - RegWeight);
@@ -1860,7 +1871,7 @@ static bool normalizeWeight(CodeGenRegister *Reg,
// where each register's weight is defined as sum of its units' weights.
void CodeGenRegBank::computeRegUnitWeights() {
std::vector<UberRegSet> UberSets;
- std::vector<UberRegSet*> RegSets(Registers.size());
+ std::vector<UberRegSet *> RegSets(Registers.size());
computeUberSets(UberSets, RegSets, *this);
// UberSets and RegSets are now immutable.
@@ -1871,7 +1882,7 @@ void CodeGenRegBank::computeRegUnitWeights() {
unsigned NumIters = 0;
for (bool Changed = true; Changed; ++NumIters) {
assert(NumIters <= NumNativeRegUnits && "Runaway register unit weights");
- (void) NumIters;
+ (void)NumIters;
Changed = false;
for (auto &Reg : Registers) {
CodeGenRegister::RegUnitList NormalUnits;
@@ -1887,9 +1898,9 @@ void CodeGenRegBank::computeRegUnitWeights() {
static std::vector<RegUnitSet>::const_iterator
findRegUnitSet(const std::vector<RegUnitSet> &UniqueSets,
const RegUnitSet &Set) {
- std::vector<RegUnitSet>::const_iterator
- I = UniqueSets.begin(), E = UniqueSets.end();
- for(;I != E; ++I) {
+ std::vector<RegUnitSet>::const_iterator I = UniqueSets.begin(),
+ E = UniqueSets.end();
+ for (; I != E; ++I) {
if (I->Units == Set.Units)
break;
}
@@ -1899,8 +1910,8 @@ findRegUnitSet(const std::vector<RegUnitSet> &UniqueSets,
// Return true if the RUSubSet is a subset of RUSuperSet.
static bool isRegUnitSubSet(const std::vector<unsigned> &RUSubSet,
const std::vector<unsigned> &RUSuperSet) {
- return std::includes(RUSuperSet.begin(), RUSuperSet.end(),
- RUSubSet.begin(), RUSubSet.end());
+ return std::includes(RUSuperSet.begin(), RUSuperSet.end(), RUSubSet.begin(),
+ RUSubSet.end());
}
/// Iteratively prune unit sets. Prune subsets that are close to the superset,
@@ -1925,8 +1936,8 @@ void CodeGenRegBank::pruneUnitSets() {
// Form an equivalence class of UnitSets with no significant difference.
std::vector<unsigned> SuperSetIDs;
- for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size();
- SubIdx != EndIdx; ++SubIdx) {
+ for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size(); SubIdx != EndIdx;
+ ++SubIdx) {
const RegUnitSet &SubSet = RegUnitSets[SubIdx];
unsigned SuperIdx = 0;
for (; SuperIdx != EndIdx; ++SuperIdx) {
@@ -1935,10 +1946,10 @@ void CodeGenRegBank::pruneUnitSets() {
unsigned UnitWeight = RegUnits[SubSet.Units[0]].Weight;
const RegUnitSet &SuperSet = RegUnitSets[SuperIdx];
- if (isRegUnitSubSet(SubSet.Units, SuperSet.Units)
- && (SubSet.Units.size() + 3 > SuperSet.Units.size())
- && UnitWeight == RegUnits[SuperSet.Units[0]].Weight
- && UnitWeight == RegUnits[SuperSet.Units.back()].Weight) {
+ if (isRegUnitSubSet(SubSet.Units, SuperSet.Units) &&
+ (SubSet.Units.size() + 3 > SuperSet.Units.size()) &&
+ UnitWeight == RegUnits[SuperSet.Units[0]].Weight &&
+ UnitWeight == RegUnits[SuperSet.Units.back()].Weight) {
LLVM_DEBUG(dbgs() << "UnitSet " << SubIdx << " subsumed by " << SuperIdx
<< "\n");
// We can pick any of the set names for the merged set. Go for the
@@ -1988,7 +1999,7 @@ void CodeGenRegBank::computeRegUnitSets() {
// Find an existing RegUnitSet.
std::vector<RegUnitSet>::const_iterator SetI =
- findRegUnitSet(RegUnitSets, RegUnitSets.back());
+ findRegUnitSet(RegUnitSets, RegUnitSets.back());
if (SetI != std::prev(RegUnitSets.end()))
RegUnitSets.pop_back();
}
@@ -2023,10 +2034,10 @@ void CodeGenRegBank::computeRegUnitSets() {
// In theory, this is combinatorial. In practice, it needs to be bounded
// by a small number of sets for regpressure to be efficient.
// If the assert is hit, we need to implement pruning.
- assert(Idx < (2*NumRegUnitSubSets) && "runaway unit set inference");
+ assert(Idx < (2 * NumRegUnitSubSets) && "runaway unit set inference");
// Compare new sets with all original classes.
- for (unsigned SearchIdx = (Idx >= NumRegUnitSubSets) ? 0 : Idx+1;
+ for (unsigned SearchIdx = (Idx >= NumRegUnitSubSets) ? 0 : Idx + 1;
SearchIdx != EndIdx; ++SearchIdx) {
std::set<unsigned> Intersection;
std::set_intersection(RegUnitSets[Idx].Units.begin(),
@@ -2040,7 +2051,7 @@ void CodeGenRegBank::computeRegUnitSets() {
// Speculatively grow the RegUnitSets to hold the new set.
RegUnitSets.resize(RegUnitSets.size() + 1);
RegUnitSets.back().Name =
- RegUnitSets[Idx].Name + "_with_" + RegUnitSets[SearchIdx].Name;
+ RegUnitSets[Idx].Name + "_with_" + RegUnitSets[SearchIdx].Name;
std::set_union(RegUnitSets[Idx].Units.begin(),
RegUnitSets[Idx].Units.end(),
@@ -2051,7 +2062,7 @@ void CodeGenRegBank::computeRegUnitSets() {
// Find an existing RegUnitSet, or add the union to the unique sets.
std::vector<RegUnitSet>::const_iterator SetI =
- findRegUnitSet(RegUnitSets, RegUnitSets.back());
+ findRegUnitSet(RegUnitSets, RegUnitSets.back());
if (SetI != std::prev(RegUnitSets.end()))
RegUnitSets.pop_back();
else {
@@ -2098,8 +2109,8 @@ void CodeGenRegBank::computeRegUnitSets() {
dbgs() << "\n UnitSetIDs:");
// Find all supersets.
- for (unsigned USIdx = 0, USEnd = RegUnitSets.size();
- USIdx != USEnd; ++USIdx) {
+ for (unsigned USIdx = 0, USEnd = RegUnitSets.size(); USIdx != USEnd;
+ ++USIdx) {
if (isRegUnitSubSet(RCRegUnits, RegUnitSets[USIdx].Units)) {
LLVM_DEBUG(dbgs() << " " << USIdx);
RegClassUnitSets[RCIdx].push_back(USIdx);
@@ -2114,8 +2125,8 @@ void CodeGenRegBank::computeRegUnitSets() {
// contain the unit. Normally, this matches an existing list of UnitSets for a
// register class. If not, we create a new entry in RegClassUnitSets as a
// "fake" register class.
- for (unsigned UnitIdx = 0, UnitEnd = NumNativeRegUnits;
- UnitIdx < UnitEnd; ++UnitIdx) {
+ for (unsigned UnitIdx = 0, UnitEnd = NumNativeRegUnits; UnitIdx < UnitEnd;
+ ++UnitIdx) {
std::vector<unsigned> RUSets;
for (unsigned i = 0, e = RegUnitSets.size(); i != e; ++i) {
RegUnitSet &RUSet = RegUnitSets[i];
@@ -2124,8 +2135,8 @@ void CodeGenRegBank::computeRegUnitSets() {
RUSets.push_back(i);
}
unsigned RCUnitSetsIdx = 0;
- for (unsigned e = RegClassUnitSets.size();
- RCUnitSetsIdx != e; ++RCUnitSetsIdx) {
+ for (unsigned e = RegClassUnitSets.size(); RCUnitSetsIdx != e;
+ ++RCUnitSetsIdx) {
if (RegClassUnitSets[RCUnitSetsIdx] == RUSets) {
break;
}
@@ -2301,9 +2312,8 @@ void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) {
continue;
}
// This is a real subset. See if we have a matching class.
- CodeGenRegisterClass *SubRC =
- getOrCreateSubClass(RC, &I->second,
- RC->getName() + "_with_" + I->first->getName());
+ CodeGenRegisterClass *SubRC = getOrCreateSubClass(
+ RC, &I->second, RC->getName() + "_with_" + I->first->getName());
RC->setSubClassWithSubReg(&SubIdx, SubRC);
}
}
@@ -2315,8 +2325,9 @@ void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) {
// has a maximal result for any SubIdx and any X >= FirstSubRegRC.
//
-void CodeGenRegBank::inferMatchingSuperRegClass(CodeGenRegisterClass *RC,
- std::list<CodeGenRegisterClass>::iterator FirstSubRegRC) {
+void CodeGenRegBank::inferMatchingSuperRegClass(
+ CodeGenRegisterClass *RC,
+ std::list<CodeGenRegisterClass>::iterator FirstSubRegRC) {
DenseMap<const CodeGenRegister *, std::vector<const CodeGenRegister *>>
SubToSuperRegs;
BitVector TopoSigs(getNumTopoSigs());
@@ -2374,9 +2385,9 @@ void CodeGenRegBank::inferMatchingSuperRegClass(CodeGenRegisterClass *RC,
// Only a subset of RC maps into SubRC. Make sure it is represented by a
// class.
- getOrCreateSubClass(RC, &SubSetVec, RC->getName() + "_with_" +
- SubIdx.getName() + "_in_" +
- SubRC.getName());
+ getOrCreateSubClass(RC, &SubSetVec,
+ RC->getName() + "_with_" + SubIdx.getName() + "_in_" +
+ SubRC.getName());
}
}
}
@@ -2431,8 +2442,7 @@ void CodeGenRegBank::computeInferredRegisterClasses() {
/// return null. If the register is in multiple classes, and the classes have a
/// superset-subset relationship and the same set of types, return the
/// superclass. Otherwise return null.
-const CodeGenRegisterClass*
-CodeGenRegBank::getRegClassForRegister(Record *R) {
+const CodeGenRegisterClass *CodeGenRegBank::getRegClassForRegister(Record *R) {
const CodeGenRegister *Reg = getReg(R);
const CodeGenRegisterClass *FoundRC = nullptr;
for (const auto &RC : getRegClasses()) {
@@ -2477,8 +2487,8 @@ CodeGenRegBank::getMinimalPhysRegClass(Record *RegRecord,
const CodeGenRegister *Reg = getReg(RegRecord);
const CodeGenRegisterClass *BestRC = nullptr;
for (const auto &RC : getRegClasses()) {
- if ((!VT || RC.hasType(*VT)) &&
- RC.contains(Reg) && (!BestRC || BestRC->hasSubClass(&RC)))
+ if ((!VT || RC.hasType(*VT)) && RC.contains(Reg) &&
+ (!BestRC || BestRC->hasSubClass(&RC)))
BestRC = &RC;
}
@@ -2486,8 +2496,8 @@ CodeGenRegBank::getMinimalPhysRegClass(Record *RegRecord,
return BestRC;
}
-BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record*> Regs) {
- SetVector<const CodeGenRegister*> Set;
+BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record *> Regs) {
+ SetVector<const CodeGenRegister *> Set;
// First add Regs with all sub-registers.
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.h b/llvm/utils/TableGen/Common/CodeGenRegisters.h
new file mode 100644
index 00000000000000..cfc6d87c4ce3a9
--- /dev/null
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.h
@@ -0,0 +1,842 @@
+//===- CodeGenRegisters.h - Register and RegisterClass Info -----*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines structures to encapsulate information gleaned from the
+// target register and register class definitions.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H
+#define LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H
+
+#include "CodeGenHwModes.h"
+#include "InfoByHwMode.h"
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/BitVector.h"
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SetVector.h"
+#include "llvm/ADT/SmallPtrSet.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/SparseBitVector.h"
+#include "llvm/ADT/StringMap.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/MC/LaneBitmask.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/TableGen/Record.h"
+#include "llvm/TableGen/SetTheory.h"
+#include <cassert>
+#include <cstdint>
+#include <deque>
+#include <functional>
+#include <list>
+#include <map>
+#include <memory>
+#include <optional>
+#include <string>
+#include <utility>
+#include <vector>
+
+namespace llvm {
+
+class CodeGenRegBank;
+
+/// Used to encode a step in a register lane mask transformation.
+/// Mask the bits specified in Mask, then rotate them Rol bits to the left
+/// assuming a wraparound at 32bits.
+struct MaskRolPair {
+ LaneBitmask Mask;
+ uint8_t RotateLeft;
+
+ bool operator==(const MaskRolPair Other) const {
+ return Mask == Other.Mask && RotateLeft == Other.RotateLeft;
+ }
+ bool operator!=(const MaskRolPair Other) const {
+ return Mask != Other.Mask || RotateLeft != Other.RotateLeft;
+ }
+};
+
+/// CodeGenSubRegIndex - Represents a sub-register index.
+class CodeGenSubRegIndex {
+ Record *const TheDef;
+ std::string Name;
+ std::string Namespace;
+
+public:
+ uint16_t Size;
+ uint16_t Offset;
+ const unsigned EnumValue;
+ mutable LaneBitmask LaneMask;
+ mutable SmallVector<MaskRolPair, 1> CompositionLaneMaskTransform;
+
+ /// A list of subregister indexes concatenated resulting in this
+ /// subregister index. This is the reverse of CodeGenRegBank::ConcatIdx.
+ SmallVector<CodeGenSubRegIndex *, 4> ConcatenationOf;
+
+ // Are all super-registers containing this SubRegIndex covered by their
+ // sub-registers?
+ bool AllSuperRegsCovered;
+ // A subregister index is "artificial" if every subregister obtained
+ // from applying this index is artificial. Artificial subregister
+ // indexes are not used to create new register classes.
+ bool Artificial;
+
+ CodeGenSubRegIndex(Record *R, unsigned Enum);
+ CodeGenSubRegIndex(StringRef N, StringRef Nspace, unsigned Enum);
+ CodeGenSubRegIndex(CodeGenSubRegIndex &) = delete;
+
+ const std::string &getName() const { return Name; }
+ const std::string &getNamespace() const { return Namespace; }
+ std::string getQualifiedName() const;
+
+ // Map of composite subreg indices.
+ typedef std::map<CodeGenSubRegIndex *, CodeGenSubRegIndex *,
+ deref<std::less<>>>
+ CompMap;
+
+ // Returns the subreg index that results from composing this with Idx.
+ // Returns NULL if this and Idx don't compose.
+ CodeGenSubRegIndex *compose(CodeGenSubRegIndex *Idx) const {
+ CompMap::const_iterator I = Composed.find(Idx);
+ return I == Composed.end() ? nullptr : I->second;
+ }
+
+ // Add a composite subreg index: this+A = B.
+ // Return a conflicting composite, or NULL
+ CodeGenSubRegIndex *addComposite(CodeGenSubRegIndex *A,
+ CodeGenSubRegIndex *B) {
+ assert(A && B);
+ std::pair<CompMap::iterator, bool> Ins =
+ Composed.insert(std::make_pair(A, B));
+ // Synthetic subreg indices that aren't contiguous (for instance ARM
+ // register tuples) don't have a bit range, so it's OK to let
+ // B->Offset == -1. For the other cases, accumulate the offset and set
+ // the size here. Only do so if there is no offset yet though.
+ if ((Offset != (uint16_t)-1 && A->Offset != (uint16_t)-1) &&
+ (B->Offset == (uint16_t)-1)) {
+ B->Offset = Offset + A->Offset;
+ B->Size = A->Size;
+ }
+ return (Ins.second || Ins.first->second == B) ? nullptr : Ins.first->second;
+ }
+
+ // Update the composite maps of components specified in 'ComposedOf'.
+ void updateComponents(CodeGenRegBank &);
+
+ // Return the map of composites.
+ const CompMap &getComposites() const { return Composed; }
+
+ // Compute LaneMask from Composed. Return LaneMask.
+ LaneBitmask computeLaneMask() const;
+
+ void setConcatenationOf(ArrayRef<CodeGenSubRegIndex *> Parts);
+
+ /// Replaces subregister indexes in the `ConcatenationOf` list with
+ /// list of subregisters they are composed of (if any). Do this recursively.
+ void computeConcatTransitiveClosure();
+
+ bool operator<(const CodeGenSubRegIndex &RHS) const {
+ return this->EnumValue < RHS.EnumValue;
+ }
+
+private:
+ CompMap Composed;
+};
+
+/// CodeGenRegister - Represents a register definition.
+class CodeGenRegister {
+public:
+ Record *TheDef;
+ unsigned EnumValue;
+ std::vector<int64_t> CostPerUse;
+ bool CoveredBySubRegs = true;
+ bool HasDisjunctSubRegs = false;
+ bool Artificial = true;
+ bool Constant = false;
+
+ // Map SubRegIndex -> Register.
+ typedef std::map<CodeGenSubRegIndex *, CodeGenRegister *, deref<std::less<>>>
+ SubRegMap;
+
+ CodeGenRegister(Record *R, unsigned Enum);
+
+ StringRef getName() const;
+
+ // Extract more information from TheDef. This is used to build an object
+ // graph after all CodeGenRegister objects have been created.
+ void buildObjectGraph(CodeGenRegBank &);
+
+ // Lazily compute a map of all sub-registers.
+ // This includes unique entries for all sub-sub-registers.
+ const SubRegMap &computeSubRegs(CodeGenRegBank &);
+
+ // Compute extra sub-registers by combining the existing sub-registers.
+ void computeSecondarySubRegs(CodeGenRegBank &);
+
+ // Add this as a super-register to all sub-registers after the sub-register
+ // graph has been built.
+ void computeSuperRegs(CodeGenRegBank &);
+
+ const SubRegMap &getSubRegs() const {
+ assert(SubRegsComplete && "Must precompute sub-registers");
+ return SubRegs;
+ }
+
+ // Add sub-registers to OSet following a pre-order defined by the .td file.
+ void addSubRegsPreOrder(SetVector<const CodeGenRegister *> &OSet,
+ CodeGenRegBank &) const;
+
+ // Return the sub-register index naming Reg as a sub-register of this
+ // register. Returns NULL if Reg is not a sub-register.
+ CodeGenSubRegIndex *getSubRegIndex(const CodeGenRegister *Reg) const {
+ return SubReg2Idx.lookup(Reg);
+ }
+
+ typedef std::vector<const CodeGenRegister *> SuperRegList;
+
+ // Get the list of super-registers in topological order, small to large.
+ // This is valid after computeSubRegs visits all registers during RegBank
+ // construction.
+ const SuperRegList &getSuperRegs() const {
+ assert(SubRegsComplete && "Must precompute sub-registers");
+ return SuperRegs;
+ }
+
+ // Get the list of ad hoc aliases. The graph is symmetric, so the list
+ // contains all registers in 'Aliases', and all registers that mention this
+ // register in 'Aliases'.
+ ArrayRef<CodeGenRegister *> getExplicitAliases() const {
+ return ExplicitAliases;
+ }
+
+ // Get the topological signature of this register. This is a small integer
+ // less than RegBank.getNumTopoSigs(). Registers with the same TopoSig have
+ // identical sub-register structure. That is, they support the same set of
+ // sub-register indices mapping to the same kind of sub-registers
+ // (TopoSig-wise).
+ unsigned getTopoSig() const {
+ assert(SuperRegsComplete && "TopoSigs haven't been computed yet.");
+ return TopoSig;
+ }
+
+ // List of register units in ascending order.
+ typedef SparseBitVector<> RegUnitList;
+ typedef SmallVector<LaneBitmask, 16> RegUnitLaneMaskList;
+
+ // How many entries in RegUnitList are native?
+ RegUnitList NativeRegUnits;
+
+ // Get the list of register units.
+ // This is only valid after computeSubRegs() completes.
+ const RegUnitList &getRegUnits() const { return RegUnits; }
+
+ ArrayRef<LaneBitmask> getRegUnitLaneMasks() const {
+ return ArrayRef(RegUnitLaneMasks).slice(0, NativeRegUnits.count());
+ }
+
+ // Get the native register units. This is a prefix of getRegUnits().
+ RegUnitList getNativeRegUnits() const { return NativeRegUnits; }
+
+ void setRegUnitLaneMasks(const RegUnitLaneMaskList &LaneMasks) {
+ RegUnitLaneMasks = LaneMasks;
+ }
+
+ // Inherit register units from subregisters.
+ // Return true if the RegUnits changed.
+ bool inheritRegUnits(CodeGenRegBank &RegBank);
+
+ // Adopt a register unit for pressure tracking.
+ // A unit is adopted iff its unit number is >= NativeRegUnits.count().
+ void adoptRegUnit(unsigned RUID) { RegUnits.set(RUID); }
+
+ // Get the sum of this register's register unit weights.
+ unsigned getWeight(const CodeGenRegBank &RegBank) const;
+
+ // Canonically ordered set.
+ typedef std::vector<const CodeGenRegister *> Vec;
+
+private:
+ bool SubRegsComplete;
+ bool SuperRegsComplete;
+ unsigned TopoSig;
+
+ // The sub-registers explicit in the .td file form a tree.
+ SmallVector<CodeGenSubRegIndex *, 8> ExplicitSubRegIndices;
+ SmallVector<CodeGenRegister *, 8> ExplicitSubRegs;
+
+ // Explicit ad hoc aliases, symmetrized to form an undirected graph.
+ SmallVector<CodeGenRegister *, 8> ExplicitAliases;
+
+ // Super-registers where this is the first explicit sub-register.
+ SuperRegList LeadingSuperRegs;
+
+ SubRegMap SubRegs;
+ SuperRegList SuperRegs;
+ DenseMap<const CodeGenRegister *, CodeGenSubRegIndex *> SubReg2Idx;
+ RegUnitList RegUnits;
+ RegUnitLaneMaskList RegUnitLaneMasks;
+};
+
+inline bool operator<(const CodeGenRegister &A, const CodeGenRegister &B) {
+ return A.EnumValue < B.EnumValue;
+}
+
+inline bool operator==(const CodeGenRegister &A, const CodeGenRegister &B) {
+ return A.EnumValue == B.EnumValue;
+}
+
+class CodeGenRegisterClass {
+ CodeGenRegister::Vec Members;
+ // Allocation orders. Order[0] always contains all registers in Members.
+ std::vector<SmallVector<Record *, 16>> Orders;
+ // Bit mask of sub-classes including this, indexed by their EnumValue.
+ BitVector SubClasses;
+ // List of super-classes, topologocally ordered to have the larger classes
+ // first. This is the same as sorting by EnumValue.
+ SmallVector<CodeGenRegisterClass *, 4> SuperClasses;
+ Record *TheDef;
+ std::string Name;
+
+ // For a synthesized class, inherit missing properties from the nearest
+ // super-class.
+ void inheritProperties(CodeGenRegBank &);
+
+ // Map SubRegIndex -> sub-class. This is the largest sub-class where all
+ // registers have a SubRegIndex sub-register.
+ DenseMap<const CodeGenSubRegIndex *, CodeGenRegisterClass *>
+ SubClassWithSubReg;
+
+ // Map SubRegIndex -> set of super-reg classes. This is all register
+ // classes SuperRC such that:
+ //
+ // R:SubRegIndex in this RC for all R in SuperRC.
+ //
+ DenseMap<const CodeGenSubRegIndex *, SmallPtrSet<CodeGenRegisterClass *, 8>>
+ SuperRegClasses;
+
+ // Bit vector of TopoSigs for the registers in this class. This will be
+ // very sparse on regular architectures.
+ BitVector TopoSigs;
+
+public:
+ unsigned EnumValue;
+ StringRef Namespace;
+ SmallVector<ValueTypeByHwMode, 4> VTs;
+ RegSizeInfoByHwMode RSI;
+ int CopyCost;
+ bool Allocatable;
+ StringRef AltOrderSelect;
+ uint8_t AllocationPriority;
+ bool GlobalPriority;
+ uint8_t TSFlags;
+ /// Contains the combination of the lane masks of all subregisters.
+ LaneBitmask LaneMask;
+ /// True if there are at least 2 subregisters which do not interfere.
+ bool HasDisjunctSubRegs;
+ bool CoveredBySubRegs;
+ /// A register class is artificial if all its members are artificial.
+ bool Artificial;
+ /// Generate register pressure set for this register class and any class
+ /// synthesized from it.
+ bool GeneratePressureSet;
+
+ // Return the Record that defined this class, or NULL if the class was
+ // created by TableGen.
+ Record *getDef() const { return TheDef; }
+
+ std::string getNamespaceQualification() const;
+ const std::string &getName() const { return Name; }
+ std::string getQualifiedName() const;
+ std::string getIdName() const;
+ std::string getQualifiedIdName() const;
+ ArrayRef<ValueTypeByHwMode> getValueTypes() const { return VTs; }
+ unsigned getNumValueTypes() const { return VTs.size(); }
+ bool hasType(const ValueTypeByHwMode &VT) const;
+
+ const ValueTypeByHwMode &getValueTypeNum(unsigned VTNum) const {
+ if (VTNum < VTs.size())
+ return VTs[VTNum];
+ llvm_unreachable("VTNum greater than number of ValueTypes in RegClass!");
+ }
+
+ // Return true if this class contains the register.
+ bool contains(const CodeGenRegister *) const;
+
+ // Returns true if RC is a subclass.
+ // RC is a sub-class of this class if it is a valid replacement for any
+ // instruction operand where a register of this classis required. It must
+ // satisfy these conditions:
+ //
+ // 1. All RC registers are also in this.
+ // 2. The RC spill size must not be smaller than our spill size.
+ // 3. RC spill alignment must be compatible with ours.
+ //
+ bool hasSubClass(const CodeGenRegisterClass *RC) const {
+ return SubClasses.test(RC->EnumValue);
+ }
+
+ // getSubClassWithSubReg - Returns the largest sub-class where all
+ // registers have a SubIdx sub-register.
+ CodeGenRegisterClass *
+ getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const {
+ return SubClassWithSubReg.lookup(SubIdx);
+ }
+
+ /// Find largest subclass where all registers have SubIdx subregisters in
+ /// SubRegClass and the largest subregister class that contains those
+ /// subregisters without (as far as possible) also containing additional
+ /// registers.
+ ///
+ /// This can be used to find a suitable pair of classes for subregister
+ /// copies. \return std::pair<SubClass, SubRegClass> where SubClass is a
+ /// SubClass is a class where every register has SubIdx and SubRegClass is a
+ /// class where every register is covered by the SubIdx subregister of
+ /// SubClass.
+ std::optional<std::pair<CodeGenRegisterClass *, CodeGenRegisterClass *>>
+ getMatchingSubClassWithSubRegs(CodeGenRegBank &RegBank,
+ const CodeGenSubRegIndex *SubIdx) const;
+
+ void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx,
+ CodeGenRegisterClass *SubRC) {
+ SubClassWithSubReg[SubIdx] = SubRC;
+ }
+
+ // getSuperRegClasses - Returns a bit vector of all register classes
+ // containing only SubIdx super-registers of this class.
+ void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
+ BitVector &Out) const;
+
+ // addSuperRegClass - Add a class containing only SubIdx super-registers.
+ void addSuperRegClass(CodeGenSubRegIndex *SubIdx,
+ CodeGenRegisterClass *SuperRC) {
+ SuperRegClasses[SubIdx].insert(SuperRC);
+ }
+
+ // getSubClasses - Returns a constant BitVector of subclasses indexed by
+ // EnumValue.
+ // The SubClasses vector includes an entry for this class.
+ const BitVector &getSubClasses() const { return SubClasses; }
+
+ // getSuperClasses - Returns a list of super classes ordered by EnumValue.
+ // The array does not include an entry for this class.
+ ArrayRef<CodeGenRegisterClass *> getSuperClasses() const {
+ return SuperClasses;
+ }
+
+ // Returns an ordered list of class members.
+ // The order of registers is the same as in the .td file.
+ // No = 0 is the default allocation order, No = 1 is the first alternative.
+ ArrayRef<Record *> getOrder(unsigned No = 0) const { return Orders[No]; }
+
+ // Return the total number of allocation orders available.
+ unsigned getNumOrders() const { return Orders.size(); }
+
+ // Get the set of registers. This set contains the same registers as
+ // getOrder(0).
+ const CodeGenRegister::Vec &getMembers() const { return Members; }
+
+ // Get a bit vector of TopoSigs present in this register class.
+ const BitVector &getTopoSigs() const { return TopoSigs; }
+
+ // Get a weight of this register class.
+ unsigned getWeight(const CodeGenRegBank &) const;
+
+ // Populate a unique sorted list of units from a register set.
+ void buildRegUnitSet(const CodeGenRegBank &RegBank,
+ std::vector<unsigned> &RegUnits) const;
+
+ CodeGenRegisterClass(CodeGenRegBank &, Record *R);
+ CodeGenRegisterClass(CodeGenRegisterClass &) = delete;
+
+ // A key representing the parts of a register class used for forming
+ // sub-classes. Note the ordering provided by this key is not the same as
+ // the topological order used for the EnumValues.
+ struct Key {
+ const CodeGenRegister::Vec *Members;
+ RegSizeInfoByHwMode RSI;
+
+ Key(const CodeGenRegister::Vec *M, const RegSizeInfoByHwMode &I)
+ : Members(M), RSI(I) {}
+
+ Key(const CodeGenRegisterClass &RC)
+ : Members(&RC.getMembers()), RSI(RC.RSI) {}
+
+ // Lexicographical order of (Members, RegSizeInfoByHwMode).
+ bool operator<(const Key &) const;
+ };
+
+ // Create a non-user defined register class.
+ CodeGenRegisterClass(CodeGenRegBank &, StringRef Name, Key Props);
+
+ // Called by CodeGenRegBank::CodeGenRegBank().
+ static void computeSubClasses(CodeGenRegBank &);
+
+ // Get ordering value among register base classes.
+ std::optional<int> getBaseClassOrder() const {
+ if (TheDef && !TheDef->isValueUnset("BaseClassOrder"))
+ return TheDef->getValueAsInt("BaseClassOrder");
+ return {};
+ }
+};
+
+// Register categories are used when we need to deterine the category a
+// register falls into (GPR, vector, fixed, etc.) without having to know
+// specific information about the target architecture.
+class CodeGenRegisterCategory {
+ Record *TheDef;
+ std::string Name;
+ std::list<CodeGenRegisterClass *> Classes;
+
+public:
+ CodeGenRegisterCategory(CodeGenRegBank &, Record *R);
+ CodeGenRegisterCategory(CodeGenRegisterCategory &) = delete;
+
+ // Return the Record that defined this class, or NULL if the class was
+ // created by TableGen.
+ Record *getDef() const { return TheDef; }
+
+ std::string getName() const { return Name; }
+ std::list<CodeGenRegisterClass *> getClasses() const { return Classes; }
+};
+
+// Register units are used to model interference and register pressure.
+// Every register is assigned one or more register units such that two
+// registers overlap if and only if they have a register unit in common.
+//
+// Normally, one register unit is created per leaf register. Non-leaf
+// registers inherit the units of their sub-registers.
+struct RegUnit {
+ // Weight assigned to this RegUnit for estimating register pressure.
+ // This is useful when equalizing weights in register classes with mixed
+ // register topologies.
+ unsigned Weight;
+
+ // Each native RegUnit corresponds to one or two root registers. The full
+ // set of registers containing this unit can be computed as the union of
+ // these two registers and their super-registers.
+ const CodeGenRegister *Roots[2];
+
+ // Index into RegClassUnitSets where we can find the list of UnitSets that
+ // contain this unit.
+ unsigned RegClassUnitSetsIdx;
+ // A register unit is artificial if at least one of its roots is
+ // artificial.
+ bool Artificial;
+
+ RegUnit() : Weight(0), RegClassUnitSetsIdx(0), Artificial(false) {
+ Roots[0] = Roots[1] = nullptr;
+ }
+
+ ArrayRef<const CodeGenRegister *> getRoots() const {
+ assert(!(Roots[1] && !Roots[0]) && "Invalid roots array");
+ return ArrayRef(Roots, !!Roots[0] + !!Roots[1]);
+ }
+};
+
+// Each RegUnitSet is a sorted vector with a name.
+struct RegUnitSet {
+ typedef std::vector<unsigned>::const_iterator iterator;
+
+ std::string Name;
+ std::vector<unsigned> Units;
+ unsigned Weight = 0; // Cache the sum of all unit weights.
+ unsigned Order = 0; // Cache the sort key.
+
+ RegUnitSet() = default;
+};
+
+// Base vector for identifying TopoSigs. The contents uniquely identify a
+// TopoSig, only computeSuperRegs needs to know how.
+typedef SmallVector<unsigned, 16> TopoSigId;
+
+// CodeGenRegBank - Represent a target's registers and the relations between
+// them.
+class CodeGenRegBank {
+ SetTheory Sets;
+
+ const CodeGenHwModes &CGH;
+
+ std::deque<CodeGenSubRegIndex> SubRegIndices;
+ DenseMap<Record *, CodeGenSubRegIndex *> Def2SubRegIdx;
+
+ CodeGenSubRegIndex *createSubRegIndex(StringRef Name, StringRef NameSpace);
+
+ typedef std::map<SmallVector<CodeGenSubRegIndex *, 8>, CodeGenSubRegIndex *>
+ ConcatIdxMap;
+ ConcatIdxMap ConcatIdx;
+
+ // Registers.
+ std::deque<CodeGenRegister> Registers;
+ StringMap<CodeGenRegister *> RegistersByName;
+ DenseMap<Record *, CodeGenRegister *> Def2Reg;
+ unsigned NumNativeRegUnits;
+
+ std::map<TopoSigId, unsigned> TopoSigs;
+
+ // Includes native (0..NumNativeRegUnits-1) and adopted register units.
+ SmallVector<RegUnit, 8> RegUnits;
+
+ // Register classes.
+ std::list<CodeGenRegisterClass> RegClasses;
+ DenseMap<Record *, CodeGenRegisterClass *> Def2RC;
+ typedef std::map<CodeGenRegisterClass::Key, CodeGenRegisterClass *> RCKeyMap;
+ RCKeyMap Key2RC;
+
+ // Register categories.
+ std::list<CodeGenRegisterCategory> RegCategories;
+ DenseMap<Record *, CodeGenRegisterCategory *> Def2RCat;
+ using RCatKeyMap =
+ std::map<CodeGenRegisterClass::Key, CodeGenRegisterCategory *>;
+ RCatKeyMap Key2RCat;
+
+ // Remember each unique set of register units. Initially, this contains a
+ // unique set for each register class. Simliar sets are coalesced with
+ // pruneUnitSets and new supersets are inferred during computeRegUnitSets.
+ std::vector<RegUnitSet> RegUnitSets;
+
+ // Map RegisterClass index to the index of the RegUnitSet that contains the
+ // class's units and any inferred RegUnit supersets.
+ //
+ // NOTE: This could grow beyond the number of register classes when we map
+ // register units to lists of unit sets. If the list of unit sets does not
+ // already exist for a register class, we create a new entry in this vector.
+ std::vector<std::vector<unsigned>> RegClassUnitSets;
+
+ // Give each register unit set an order based on sorting criteria.
+ std::vector<unsigned> RegUnitSetOrder;
+
+ // Keep track of synthesized definitions generated in TupleExpander.
+ std::vector<std::unique_ptr<Record>> SynthDefs;
+
+ // Add RC to *2RC maps.
+ void addToMaps(CodeGenRegisterClass *);
+
+ // Create a synthetic sub-class if it is missing.
+ CodeGenRegisterClass *getOrCreateSubClass(const CodeGenRegisterClass *RC,
+ const CodeGenRegister::Vec *Membs,
+ StringRef Name);
+
+ // Infer missing register classes.
+ void computeInferredRegisterClasses();
+ void inferCommonSubClass(CodeGenRegisterClass *RC);
+ void inferSubClassWithSubReg(CodeGenRegisterClass *RC);
+
+ void inferMatchingSuperRegClass(CodeGenRegisterClass *RC) {
+ inferMatchingSuperRegClass(RC, RegClasses.begin());
+ }
+
+ void inferMatchingSuperRegClass(
+ CodeGenRegisterClass *RC,
+ std::list<CodeGenRegisterClass>::iterator FirstSubRegRC);
+
+ // Iteratively prune unit sets.
+ void pruneUnitSets();
+
+ // Compute a weight for each register unit created during getSubRegs.
+ void computeRegUnitWeights();
+
+ // Create a RegUnitSet for each RegClass and infer superclasses.
+ void computeRegUnitSets();
+
+ // Populate the Composite map from sub-register relationships.
+ void computeComposites();
+
+ // Compute a lane mask for each sub-register index.
+ void computeSubRegLaneMasks();
+
+ /// Computes a lane mask for each register unit enumerated by a physical
+ /// register.
+ void computeRegUnitLaneMasks();
+
+public:
+ CodeGenRegBank(RecordKeeper &, const CodeGenHwModes &);
+ CodeGenRegBank(CodeGenRegBank &) = delete;
+
+ SetTheory &getSets() { return Sets; }
+
+ const CodeGenHwModes &getHwModes() const { return CGH; }
+
+ // Sub-register indices. The first NumNamedIndices are defined by the user
+ // in the .td files. The rest are synthesized such that all sub-registers
+ // have a unique name.
+ const std::deque<CodeGenSubRegIndex> &getSubRegIndices() const {
+ return SubRegIndices;
+ }
+
+ // Find a SubRegIndex from its Record def or add to the list if it does
+ // not exist there yet.
+ CodeGenSubRegIndex *getSubRegIdx(Record *);
+
+ // Find a SubRegIndex from its Record def.
+ const CodeGenSubRegIndex *findSubRegIdx(const Record *Def) const;
+
+ // Find or create a sub-register index representing the A+B composition.
+ CodeGenSubRegIndex *getCompositeSubRegIndex(CodeGenSubRegIndex *A,
+ CodeGenSubRegIndex *B);
+
+ // Find or create a sub-register index representing the concatenation of
+ // non-overlapping sibling indices.
+ CodeGenSubRegIndex *
+ getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8> &);
+
+ const std::deque<CodeGenRegister> &getRegisters() const { return Registers; }
+
+ const StringMap<CodeGenRegister *> &getRegistersByName() const {
+ return RegistersByName;
+ }
+
+ // Find a register from its Record def.
+ CodeGenRegister *getReg(Record *);
+
+ // Get a Register's index into the Registers array.
+ unsigned getRegIndex(const CodeGenRegister *Reg) const {
+ return Reg->EnumValue - 1;
+ }
+
+ // Return the number of allocated TopoSigs. The first TopoSig representing
+ // leaf registers is allocated number 0.
+ unsigned getNumTopoSigs() const { return TopoSigs.size(); }
+
+ // Find or create a TopoSig for the given TopoSigId.
+ // This function is only for use by CodeGenRegister::computeSuperRegs().
+ // Others should simply use Reg->getTopoSig().
+ unsigned getTopoSig(const TopoSigId &Id) {
+ return TopoSigs.insert(std::make_pair(Id, TopoSigs.size())).first->second;
+ }
+
+ // Create a native register unit that is associated with one or two root
+ // registers.
+ unsigned newRegUnit(CodeGenRegister *R0, CodeGenRegister *R1 = nullptr) {
+ RegUnits.resize(RegUnits.size() + 1);
+ RegUnit &RU = RegUnits.back();
+ RU.Roots[0] = R0;
+ RU.Roots[1] = R1;
+ RU.Artificial = R0->Artificial;
+ if (R1)
+ RU.Artificial |= R1->Artificial;
+ return RegUnits.size() - 1;
+ }
+
+ // Create a new non-native register unit that can be adopted by a register
+ // to increase its pressure. Note that NumNativeRegUnits is not increased.
+ unsigned newRegUnit(unsigned Weight) {
+ RegUnits.resize(RegUnits.size() + 1);
+ RegUnits.back().Weight = Weight;
+ return RegUnits.size() - 1;
+ }
+
+ // Native units are the singular unit of a leaf register. Register aliasing
+ // is completely characterized by native units. Adopted units exist to give
+ // register additional weight but don't affect aliasing.
+ bool isNativeUnit(unsigned RUID) const { return RUID < NumNativeRegUnits; }
+
+ unsigned getNumNativeRegUnits() const { return NumNativeRegUnits; }
+
+ RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; }
+ const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; }
+
+ std::list<CodeGenRegisterClass> &getRegClasses() { return RegClasses; }
+
+ const std::list<CodeGenRegisterClass> &getRegClasses() const {
+ return RegClasses;
+ }
+
+ std::list<CodeGenRegisterCategory> &getRegCategories() {
+ return RegCategories;
+ }
+
+ const std::list<CodeGenRegisterCategory> &getRegCategories() const {
+ return RegCategories;
+ }
+
+ // Find a register class from its def.
+ CodeGenRegisterClass *getRegClass(const Record *) const;
+
+ /// getRegisterClassForRegister - Find the register class that contains the
+ /// specified physical register. If the register is not in a register
+ /// class, return null. If the register is in multiple classes, and the
+ /// classes have a superset-subset relationship and the same set of types,
+ /// return the superclass. Otherwise return null.
+ const CodeGenRegisterClass *getRegClassForRegister(Record *R);
+
+ // Analog of TargetRegisterInfo::getMinimalPhysRegClass. Unlike
+ // getRegClassForRegister, this tries to find the smallest class containing
+ // the physical register. If \p VT is specified, it will only find classes
+ // with a matching type
+ const CodeGenRegisterClass *
+ getMinimalPhysRegClass(Record *RegRecord, ValueTypeByHwMode *VT = nullptr);
+
+ // Get the sum of unit weights.
+ unsigned getRegUnitSetWeight(const std::vector<unsigned> &Units) const {
+ unsigned Weight = 0;
+ for (unsigned Unit : Units)
+ Weight += getRegUnit(Unit).Weight;
+ return Weight;
+ }
+
+ unsigned getRegSetIDAt(unsigned Order) const {
+ return RegUnitSetOrder[Order];
+ }
+
+ const RegUnitSet &getRegSetAt(unsigned Order) const {
+ return RegUnitSets[RegUnitSetOrder[Order]];
+ }
+
+ // Increase a RegUnitWeight.
+ void increaseRegUnitWeight(unsigned RUID, unsigned Inc) {
+ getRegUnit(RUID).Weight += Inc;
+ }
+
+ // Get the number of register pressure dimensions.
+ unsigned getNumRegPressureSets() const { return RegUnitSets.size(); }
+
+ // Get a set of register unit IDs for a given dimension of pressure.
+ const RegUnitSet &getRegPressureSet(unsigned Idx) const {
+ return RegUnitSets[Idx];
+ }
+
+ // The number of pressure set lists may be larget than the number of
+ // register classes if some register units appeared in a list of sets that
+ // did not correspond to an existing register class.
+ unsigned getNumRegClassPressureSetLists() const {
+ return RegClassUnitSets.size();
+ }
+
+ // Get a list of pressure set IDs for a register class. Liveness of a
+ // register in this class impacts each pressure set in this list by the
+ // weight of the register. An exact solution requires all registers in a
+ // class to have the same class, but it is not strictly guaranteed.
+ ArrayRef<unsigned> getRCPressureSetIDs(unsigned RCIdx) const {
+ return RegClassUnitSets[RCIdx];
+ }
+
+ // Computed derived records such as missing sub-register indices.
+ void computeDerivedInfo();
+
+ // Compute the set of registers completely covered by the registers in Regs.
+ // The returned BitVector will have a bit set for each register in Regs,
+ // all sub-registers, and all super-registers that are covered by the
+ // registers in Regs.
+ //
+ // This is used to compute the mask of call-preserved registers from a list
+ // of callee-saves.
+ BitVector computeCoveredRegisters(ArrayRef<Record *> Regs);
+
+ // Bit mask of lanes that cover their registers. A sub-register index whose
+ // LaneMask is contained in CoveringLanes will be completely covered by
+ // another sub-register with the same or larger lane mask.
+ LaneBitmask CoveringLanes;
+
+ // Helper function for printing debug information. Handles artificial
+ // (non-native) reg units.
+ void printRegUnitName(unsigned Unit) const;
+};
+
+} // end namespace llvm
+
+#endif // LLVM_UTILS_TABLEGEN_CODEGENREGISTERS_H
diff --git a/llvm/utils/TableGen/CodeGenSchedule.cpp b/llvm/utils/TableGen/Common/CodeGenSchedule.cpp
similarity index 90%
rename from llvm/utils/TableGen/CodeGenSchedule.cpp
rename to llvm/utils/TableGen/Common/CodeGenSchedule.cpp
index 54463da1982147..9cebc427dbdbc7 100644
--- a/llvm/utils/TableGen/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenSchedule.cpp
@@ -51,7 +51,7 @@ struct InstrsOp : public SetTheory::Operator {
// (instregex "OpcPat",...) Find all instructions matching an opcode pattern.
struct InstRegexOp : public SetTheory::Operator {
const CodeGenTarget &Target;
- InstRegexOp(const CodeGenTarget &t): Target(t) {}
+ InstRegexOp(const CodeGenTarget &t) : Target(t) {}
/// Remove any text inside of parentheses from S.
static std::string removeParens(llvm::StringRef S) {
@@ -182,8 +182,8 @@ struct InstRegexOp : public SetTheory::Operator {
/// CodeGenModels ctor interprets machine model records and populates maps.
CodeGenSchedModels::CodeGenSchedModels(RecordKeeper &RK,
- const CodeGenTarget &TGT):
- Records(RK), Target(TGT) {
+ const CodeGenTarget &TGT)
+ : Records(RK), Target(TGT) {
Sets.addFieldExpander("InstRW", "Instrs");
@@ -298,9 +298,8 @@ static APInt constructOperandMask(ArrayRef<int64_t> Indices) {
return OperandMask;
}
-static void
-processSTIPredicate(STIPredicateFunction &Fn,
- const ProcModelMapTy &ProcModelMap) {
+static void processSTIPredicate(STIPredicateFunction &Fn,
+ const ProcModelMapTy &ProcModelMap) {
DenseMap<const Record *, unsigned> Opcode2Index;
using OpcodeMapPair = std::pair<const Record *, OpcodeInfo>;
std::vector<OpcodeMapPair> OpcodeMappings;
@@ -380,30 +379,29 @@ processSTIPredicate(STIPredicateFunction &Fn,
// Sort OpcodeMappings elements based on their CPU and predicate masks.
// As a last resort, order elements by opcode identifier.
- llvm::sort(OpcodeMappings,
- [&](const OpcodeMapPair &Lhs, const OpcodeMapPair &Rhs) {
- unsigned LhsIdx = Opcode2Index[Lhs.first];
- unsigned RhsIdx = Opcode2Index[Rhs.first];
- const std::pair<APInt, APInt> &LhsMasks = OpcodeMasks[LhsIdx];
- const std::pair<APInt, APInt> &RhsMasks = OpcodeMasks[RhsIdx];
-
- auto PopulationCountAndLeftBit =
- [](const APInt &Other) -> std::pair<int, int> {
- return std::pair<int, int>(Other.popcount(),
- -Other.countl_zero());
- };
- auto lhsmask_first = PopulationCountAndLeftBit(LhsMasks.first);
- auto rhsmask_first = PopulationCountAndLeftBit(RhsMasks.first);
- if (lhsmask_first != rhsmask_first)
- return lhsmask_first < rhsmask_first;
-
- auto lhsmask_second = PopulationCountAndLeftBit(LhsMasks.second);
- auto rhsmask_second = PopulationCountAndLeftBit(RhsMasks.second);
- if (lhsmask_second != rhsmask_second)
- return lhsmask_second < rhsmask_second;
-
- return LhsIdx < RhsIdx;
- });
+ llvm::sort(
+ OpcodeMappings, [&](const OpcodeMapPair &Lhs, const OpcodeMapPair &Rhs) {
+ unsigned LhsIdx = Opcode2Index[Lhs.first];
+ unsigned RhsIdx = Opcode2Index[Rhs.first];
+ const std::pair<APInt, APInt> &LhsMasks = OpcodeMasks[LhsIdx];
+ const std::pair<APInt, APInt> &RhsMasks = OpcodeMasks[RhsIdx];
+
+ auto PopulationCountAndLeftBit =
+ [](const APInt &Other) -> std::pair<int, int> {
+ return std::pair<int, int>(Other.popcount(), -Other.countl_zero());
+ };
+ auto lhsmask_first = PopulationCountAndLeftBit(LhsMasks.first);
+ auto rhsmask_first = PopulationCountAndLeftBit(RhsMasks.first);
+ if (lhsmask_first != rhsmask_first)
+ return lhsmask_first < rhsmask_first;
+
+ auto lhsmask_second = PopulationCountAndLeftBit(LhsMasks.second);
+ auto rhsmask_second = PopulationCountAndLeftBit(RhsMasks.second);
+ if (lhsmask_second != rhsmask_second)
+ return lhsmask_second < rhsmask_second;
+
+ return LhsIdx < RhsIdx;
+ });
// Now construct opcode groups. Groups are used by the SubtargetEmitter when
// expanding the body of a STIPredicate function. In particular, each opcode
@@ -498,8 +496,7 @@ void CodeGenSchedModels::collectLoadStoreQueueInfo() {
CodeGenProcModel &PM = getProcModel(Queue->getValueAsDef("SchedModel"));
if (Queue->isSubClassOf("LoadQueue")) {
if (PM.LoadQueue) {
- PrintError(Queue->getLoc(),
- "Expected a single LoadQueue definition");
+ PrintError(Queue->getLoc(), "Expected a single LoadQueue definition");
PrintNote(PM.LoadQueue->getLoc(),
"Previous definition of LoadQueue was here");
}
@@ -509,8 +506,7 @@ void CodeGenSchedModels::collectLoadStoreQueueInfo() {
if (Queue->isSubClassOf("StoreQueue")) {
if (PM.StoreQueue) {
- PrintError(Queue->getLoc(),
- "Expected a single StoreQueue definition");
+ PrintError(Queue->getLoc(), "Expected a single StoreQueue definition");
PrintNote(PM.StoreQueue->getLoc(),
"Previous definition of StoreQueue was here");
}
@@ -542,14 +538,15 @@ void CodeGenSchedModels::collectProcModels() {
// Check for duplicated names.
auto I = std::adjacent_find(ProcRecords.begin(), ProcRecords.end(),
[](const Record *Rec1, const Record *Rec2) {
- return Rec1->getValueAsString("Name") == Rec2->getValueAsString("Name");
- });
+ return Rec1->getValueAsString("Name") ==
+ Rec2->getValueAsString("Name");
+ });
if (I != ProcRecords.end())
PrintFatalError((*I)->getLoc(), "Duplicate processor name " +
- (*I)->getValueAsString("Name"));
+ (*I)->getValueAsString("Name"));
// Reserve space because we can. Reallocation would be ok.
- ProcModels.reserve(ProcRecords.size()+1);
+ ProcModels.reserve(ProcRecords.size() + 1);
// Use idx=0 for NoModel/NoItineraries.
Record *NoModelDef = Records.getDef("NoSchedModel");
@@ -574,8 +571,7 @@ void CodeGenSchedModels::addProcModel(Record *ProcDef) {
if (ModelKey->isSubClassOf("SchedMachineModel")) {
Record *ItinsDef = ModelKey->getValueAsDef("Itineraries");
ProcModels.emplace_back(ProcModels.size(), Name, ModelKey, ItinsDef);
- }
- else {
+ } else {
// An itinerary is defined without a machine model. Infer a new model.
if (!ModelKey->getValueAsListOfDefs("IID").empty())
Name = Name + "Model";
@@ -587,7 +583,7 @@ void CodeGenSchedModels::addProcModel(Record *ProcDef) {
// Recursively find all reachable SchedReadWrite records.
static void scanSchedRW(Record *RWDef, RecVec &RWDefs,
- SmallPtrSet<Record*, 16> &RWSet) {
+ SmallPtrSet<Record *, 16> &RWSet) {
if (!RWSet.insert(RWDef).second)
return;
RWDefs.push_back(RWDef);
@@ -596,8 +592,7 @@ static void scanSchedRW(Record *RWDef, RecVec &RWDefs,
RecVec Seq = RWDef->getValueAsListOfDefs("Writes");
for (Record *WSRec : Seq)
scanSchedRW(WSRec, RWDefs, RWSet);
- }
- else if (RWDef->isSubClassOf("SchedVariant")) {
+ } else if (RWDef->isSubClassOf("SchedVariant")) {
// Visit each variant (guarded by a different predicate).
RecVec Vars = RWDef->getValueAsListOfDefs("Variants");
for (Record *Variant : Vars) {
@@ -616,7 +611,7 @@ void CodeGenSchedModels::collectSchedRW() {
SchedWrites.resize(1);
SchedReads.resize(1);
- SmallPtrSet<Record*, 16> RWSet;
+ SmallPtrSet<Record *, 16> RWSet;
// Find all SchedReadWrites referenced by instruction defs.
RecVec SWDefs, SRDefs;
@@ -673,8 +668,7 @@ void CodeGenSchedModels::collectSchedRW() {
if (!AliasDef->isSubClassOf("SchedWrite"))
PrintFatalError(ADef->getLoc(), "SchedWrite Alias must be SchedWrite");
scanSchedRW(AliasDef, SWDefs, RWSet);
- }
- else {
+ } else {
assert(MatchDef->isSubClassOf("SchedRead") && "Unknown SchedReadWrite");
if (!AliasDef->isSubClassOf("SchedRead"))
PrintFatalError(ADef->getLoc(), "SchedRead Alias must be SchedRead");
@@ -690,7 +684,7 @@ void CodeGenSchedModels::collectSchedRW() {
}
llvm::sort(SRDefs, LessRecord());
for (Record *SRDef : SRDefs) {
- assert(!getSchedRWIdx(SRDef, /*IsRead-*/true) && "duplicate SchedWrite");
+ assert(!getSchedRWIdx(SRDef, /*IsRead-*/ true) && "duplicate SchedWrite");
SchedReads.emplace_back(SchedReads.size(), SRDef);
}
// Initialize WriteSequence vectors.
@@ -753,9 +747,9 @@ unsigned CodeGenSchedModels::getSchedRWIdx(const Record *Def,
}
bool CodeGenSchedModels::hasReadOfWrite(Record *WriteDef) const {
- for (auto& ProcModel : ProcModels) {
+ for (auto &ProcModel : ProcModels) {
const RecVec &RADefs = ProcModel.ReadAdvanceDefs;
- for (auto& RADef : RADefs) {
+ for (auto &RADef : RADefs) {
RecVec ValidWrites = RADef->getValueAsListOfDefs("ValidWrites");
if (is_contained(ValidWrites, WriteDef))
return true;
@@ -764,8 +758,8 @@ bool CodeGenSchedModels::hasReadOfWrite(Record *WriteDef) const {
return false;
}
-static void splitSchedReadWrites(const RecVec &RWDefs,
- RecVec &WriteDefs, RecVec &ReadDefs) {
+static void splitSchedReadWrites(const RecVec &RWDefs, RecVec &WriteDefs,
+ RecVec &ReadDefs) {
for (Record *RWDef : RWDefs) {
if (RWDef->isSubClassOf("SchedWrite"))
WriteDefs.push_back(RWDef);
@@ -777,8 +771,8 @@ static void splitSchedReadWrites(const RecVec &RWDefs,
}
// Split the SchedReadWrites defs and call findRWs for each list.
-void CodeGenSchedModels::findRWs(const RecVec &RWDefs,
- IdxVec &Writes, IdxVec &Reads) const {
+void CodeGenSchedModels::findRWs(const RecVec &RWDefs, IdxVec &Writes,
+ IdxVec &Reads) const {
RecVec WriteDefs;
RecVec ReadDefs;
splitSchedReadWrites(RWDefs, WriteDefs, ReadDefs);
@@ -803,8 +797,7 @@ void CodeGenSchedModels::expandRWSequence(unsigned RWIdx, IdxVec &RWSeq,
RWSeq.push_back(RWIdx);
return;
}
- int Repeat =
- SchedRW.TheDef ? SchedRW.TheDef->getValueAsInt("Repeat") : 1;
+ int Repeat = SchedRW.TheDef ? SchedRW.TheDef->getValueAsInt("Repeat") : 1;
for (int i = 0; i < Repeat; ++i) {
for (unsigned I : SchedRW.Sequence) {
expandRWSequence(I, RWSeq, IsRead);
@@ -815,8 +808,8 @@ void CodeGenSchedModels::expandRWSequence(unsigned RWIdx, IdxVec &RWSeq,
// Expand a SchedWrite as a sequence following any aliases that coincide with
// the given processor model.
void CodeGenSchedModels::expandRWSeqForProc(
- unsigned RWIdx, IdxVec &RWSeq, bool IsRead,
- const CodeGenProcModel &ProcModel) const {
+ unsigned RWIdx, IdxVec &RWSeq, bool IsRead,
+ const CodeGenProcModel &ProcModel) const {
const CodeGenSchedRW &SchedWrite = getSchedRW(RWIdx, IsRead);
Record *AliasDef = nullptr;
@@ -828,14 +821,16 @@ void CodeGenSchedModels::expandRWSeqForProc(
continue;
}
if (AliasDef)
- PrintFatalError(AliasRW.TheDef->getLoc(), "Multiple aliases "
- "defined for processor " + ProcModel.ModelName +
- " Ensure only one SchedAlias exists per RW.");
+ PrintFatalError(AliasRW.TheDef->getLoc(),
+ "Multiple aliases "
+ "defined for processor " +
+ ProcModel.ModelName +
+ " Ensure only one SchedAlias exists per RW.");
AliasDef = AliasRW.TheDef;
}
if (AliasDef) {
- expandRWSeqForProc(getSchedRWIdx(AliasDef, IsRead),
- RWSeq, IsRead,ProcModel);
+ expandRWSeqForProc(getSchedRWIdx(AliasDef, IsRead), RWSeq, IsRead,
+ ProcModel);
return;
}
if (!SchedWrite.IsSequence) {
@@ -843,7 +838,7 @@ void CodeGenSchedModels::expandRWSeqForProc(
return;
}
int Repeat =
- SchedWrite.TheDef ? SchedWrite.TheDef->getValueAsInt("Repeat") : 1;
+ SchedWrite.TheDef ? SchedWrite.TheDef->getValueAsInt("Repeat") : 1;
for (int I = 0, E = Repeat; I < E; ++I) {
for (unsigned Idx : SchedWrite.Sequence) {
expandRWSeqForProc(Idx, RWSeq, IsRead, ProcModel);
@@ -888,8 +883,7 @@ void CodeGenSchedModels::collectSchedClasses() {
// NoItinerary is always the first class at Idx=0
assert(SchedClasses.empty() && "Expected empty sched class");
- SchedClasses.emplace_back(0, "NoInstrModel",
- Records.getDef("NoItinerary"));
+ SchedClasses.emplace_back(0, "NoInstrModel", Records.getDef("NoItinerary"));
SchedClasses.back().ProcIndices.push_back(0);
// Create a SchedClass for each unique combination of itinerary class and
@@ -901,7 +895,7 @@ void CodeGenSchedModels::collectSchedClasses() {
findRWs(Inst->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads);
// ProcIdx == 0 indicates the class applies to all processors.
- unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, /*ProcIndices*/{0});
+ unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, /*ProcIndices*/ {0});
InstrClassMap[Inst->TheDef] = SCIdx;
}
// Create classes for InstRW defs.
@@ -933,7 +927,8 @@ void CodeGenSchedModels::collectSchedClasses() {
}
CodeGenSchedClass &SC = getSchedClass(SCIdx);
if (SC.ProcIndices[0] != 0)
- PrintFatalError(Inst->TheDef->getLoc(), "Instruction's sched class "
+ PrintFatalError(Inst->TheDef->getLoc(),
+ "Instruction's sched class "
"must not be subtarget specific.");
IdxVec ProcIndices;
@@ -962,8 +957,7 @@ void CodeGenSchedModels::collectSchedClasses() {
<< InstName);
IdxVec Writes;
IdxVec Reads;
- findRWs(RWDef->getValueAsListOfDefs("OperandReadWrites"),
- Writes, Reads);
+ findRWs(RWDef->getValueAsListOfDefs("OperandReadWrites"), Writes, Reads);
LLVM_DEBUG({
for (unsigned WIdx : Writes)
dbgs() << " " << SchedWrites[WIdx].Name;
@@ -1032,25 +1026,23 @@ unsigned CodeGenSchedModels::addSchedClass(Record *ItinClassDef,
assert(!ProcIndices.empty() && "expect at least one ProcIdx");
auto IsKeyEqual = [=](const CodeGenSchedClass &SC) {
- return SC.isKeyEqual(ItinClassDef, OperWrites, OperReads);
- };
+ return SC.isKeyEqual(ItinClassDef, OperWrites, OperReads);
+ };
auto I = find_if(make_range(schedClassBegin(), schedClassEnd()), IsKeyEqual);
unsigned Idx = I == schedClassEnd() ? 0 : std::distance(schedClassBegin(), I);
if (Idx || SchedClasses[0].isKeyEqual(ItinClassDef, OperWrites, OperReads)) {
IdxVec PI;
std::set_union(SchedClasses[Idx].ProcIndices.begin(),
- SchedClasses[Idx].ProcIndices.end(),
- ProcIndices.begin(), ProcIndices.end(),
- std::back_inserter(PI));
+ SchedClasses[Idx].ProcIndices.end(), ProcIndices.begin(),
+ ProcIndices.end(), std::back_inserter(PI));
SchedClasses[Idx].ProcIndices = std::move(PI);
return Idx;
}
Idx = SchedClasses.size();
- SchedClasses.emplace_back(Idx,
- createSchedClassName(ItinClassDef, OperWrites,
- OperReads),
- ItinClassDef);
+ SchedClasses.emplace_back(
+ Idx, createSchedClassName(ItinClassDef, OperWrites, OperReads),
+ ItinClassDef);
CodeGenSchedClass &SC = SchedClasses.back();
SC.Writes = OperWrites;
SC.Reads = OperReads;
@@ -1083,17 +1075,16 @@ void CodeGenSchedModels::createInstRWClass(Record *InstRWDef) {
// the Instrs to it.
for (auto &Entry : ClassInstrs) {
unsigned OldSCIdx = Entry.first;
- ArrayRef<Record*> InstDefs = Entry.second;
+ ArrayRef<Record *> InstDefs = Entry.second;
// If the all instrs in the current class are accounted for, then leave
// them mapped to their old class.
if (OldSCIdx) {
const RecVec &RWDefs = SchedClasses[OldSCIdx].InstRWs;
if (!RWDefs.empty()) {
const RecVec *OrigInstDefs = Sets.expand(RWDefs[0]);
- unsigned OrigNumInstrs =
- count_if(*OrigInstDefs, [&](Record *OIDef) {
- return InstrClassMap[OIDef] == OldSCIdx;
- });
+ unsigned OrigNumInstrs = count_if(*OrigInstDefs, [&](Record *OIDef) {
+ return InstrClassMap[OIDef] == OldSCIdx;
+ });
if (OrigNumInstrs == InstDefs.size()) {
assert(SchedClasses[OldSCIdx].ProcIndices[0] == 0 &&
"expected a generic SchedClass");
@@ -1148,8 +1139,7 @@ void CodeGenSchedModels::createInstRWClass(Record *InstRWDef) {
"\".");
PrintFatalNote(OldRWDef->getLoc(), "Previous match was here.");
}
- assert(OldRWDef != InstRWDef &&
- "SchedClass has duplicate InstRW def");
+ assert(OldRWDef != InstRWDef && "SchedClass has duplicate InstRW def");
SC.InstRWs.push_back(OldRWDef);
}
}
@@ -1162,7 +1152,8 @@ void CodeGenSchedModels::createInstRWClass(Record *InstRWDef) {
// True if collectProcItins found anything.
bool CodeGenSchedModels::hasItineraries() const {
- for (const CodeGenProcModel &PM : make_range(procModelBegin(),procModelEnd()))
+ for (const CodeGenProcModel &PM :
+ make_range(procModelBegin(), procModelEnd()))
if (PM.hasItineraries())
return true;
return false;
@@ -1217,14 +1208,14 @@ void CodeGenSchedModels::collectProcItins() {
void CodeGenSchedModels::collectProcItinRW() {
RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW");
llvm::sort(ItinRWDefs, LessRecord());
- for (Record *RWDef : ItinRWDefs) {
+ for (Record *RWDef : ItinRWDefs) {
if (!RWDef->getValueInit("SchedModel")->isComplete())
PrintFatalError(RWDef->getLoc(), "SchedModel is undefined");
Record *ModelDef = RWDef->getValueAsDef("SchedModel");
ProcModelMapTy::const_iterator I = ProcModelMap.find(ModelDef);
if (I == ProcModelMap.end()) {
- PrintFatalError(RWDef->getLoc(), "Undefined SchedMachineModel "
- + ModelDef->getName());
+ PrintFatalError(RWDef->getLoc(),
+ "Undefined SchedMachineModel " + ModelDef->getName());
}
ProcModels[I->second].ItinRWDefs.push_back(RWDef);
}
@@ -1254,10 +1245,10 @@ void CodeGenSchedModels::inferSchedClasses() {
if (!SchedClasses[Idx].InstRWs.empty())
inferFromInstRWs(Idx);
if (!SchedClasses[Idx].Writes.empty()) {
- inferFromRW(SchedClasses[Idx].Writes, SchedClasses[Idx].Reads,
- Idx, SchedClasses[Idx].ProcIndices);
+ inferFromRW(SchedClasses[Idx].Writes, SchedClasses[Idx].Reads, Idx,
+ SchedClasses[Idx].ProcIndices);
}
- assert(SchedClasses.size() < (NumInstrSchedClasses*6) &&
+ assert(SchedClasses.size() < (NumInstrSchedClasses * 6) &&
"too many SchedVariants");
}
}
@@ -1274,9 +1265,9 @@ void CodeGenSchedModels::inferFromItinClass(Record *ItinClassDef,
if (!llvm::is_contained(Matched, ItinClassDef))
continue;
if (HasMatch)
- PrintFatalError(Rec->getLoc(), "Duplicate itinerary class "
- + ItinClassDef->getName()
- + " in ItinResources for " + PM.ModelName);
+ PrintFatalError(Rec->getLoc(),
+ "Duplicate itinerary class " + ItinClassDef->getName() +
+ " in ItinResources for " + PM.ModelName);
HasMatch = true;
IdxVec Writes, Reads;
findRWs(Rec->getValueAsListOfDefs("OperandReadWrites"), Writes, Reads);
@@ -1317,8 +1308,8 @@ struct TransVariant {
unsigned ProcIdx; // Processor model index or zero for any.
unsigned TransVecIdx; // Index into PredTransitions::TransVec.
- TransVariant(Record *def, unsigned rwi, unsigned pi, unsigned ti):
- VarOrSeqDef(def), RWIdx(rwi), ProcIdx(pi), TransVecIdx(ti) {}
+ TransVariant(Record *def, unsigned rwi, unsigned pi, unsigned ti)
+ : VarOrSeqDef(def), RWIdx(rwi), ProcIdx(pi), TransVecIdx(ti) {}
};
// Associate a predicate with the SchedReadWrite that it guards.
@@ -1328,15 +1319,16 @@ struct PredCheck {
unsigned RWIdx;
Record *Predicate;
- PredCheck(bool r, unsigned w, Record *p): IsRead(r), RWIdx(w), Predicate(p) {}
+ PredCheck(bool r, unsigned w, Record *p)
+ : IsRead(r), RWIdx(w), Predicate(p) {}
};
// A Predicate transition is a list of RW sequences guarded by a PredTerm.
struct PredTransition {
// A predicate term is a conjunction of PredChecks.
SmallVector<PredCheck, 4> PredTerm;
- SmallVector<SmallVector<unsigned,4>, 16> WriteSequences;
- SmallVector<SmallVector<unsigned,4>, 16> ReadSequences;
+ SmallVector<SmallVector<unsigned, 4>, 16> WriteSequences;
+ SmallVector<SmallVector<unsigned, 4>, 16> ReadSequences;
unsigned ProcIndex = 0;
PredTransition() = default;
@@ -1354,7 +1346,7 @@ class PredTransitions {
public:
std::vector<PredTransition> TransVec;
- PredTransitions(CodeGenSchedModels &sm): SchedModels(sm) {}
+ PredTransitions(CodeGenSchedModels &sm) : SchedModels(sm) {}
bool substituteVariantOperand(const SmallVectorImpl<unsigned> &RWSeq,
bool IsRead, unsigned StartIdx);
@@ -1368,9 +1360,8 @@ class PredTransitions {
private:
bool mutuallyExclusive(Record *PredDef, ArrayRef<Record *> Preds,
ArrayRef<PredCheck> Term);
- void getIntersectingVariants(
- const CodeGenSchedRW &SchedRW, unsigned TransIdx,
- std::vector<TransVariant> &IntersectingVariants);
+ void getIntersectingVariants(const CodeGenSchedRW &SchedRW, unsigned TransIdx,
+ std::vector<TransVariant> &IntersectingVariants);
void pushVariant(const TransVariant &VInfo, bool IsRead);
};
@@ -1388,7 +1379,7 @@ class PredTransitions {
bool PredTransitions::mutuallyExclusive(Record *PredDef,
ArrayRef<Record *> Preds,
ArrayRef<PredCheck> Term) {
- for (const PredCheck &PC: Term) {
+ for (const PredCheck &PC : Term) {
if (PC.Predicate == PredDef)
return false;
@@ -1446,8 +1437,8 @@ static std::vector<Record *> getAllPredicates(ArrayRef<TransVariant> Variants,
// given SchedRW whose processor indices and predicates are not mutually
// exclusive with the given transition.
void PredTransitions::getIntersectingVariants(
- const CodeGenSchedRW &SchedRW, unsigned TransIdx,
- std::vector<TransVariant> &IntersectingVariants) {
+ const CodeGenSchedRW &SchedRW, unsigned TransIdx,
+ std::vector<TransVariant> &IntersectingVariants) {
bool GenericRW = false;
@@ -1489,7 +1480,7 @@ void PredTransitions::getIntersectingVariants(
}
const CodeGenSchedRW &AliasRW =
- SchedModels.getSchedRW((*AI)->getValueAsDef("AliasRW"));
+ SchedModels.getSchedRW((*AI)->getValueAsDef("AliasRW"));
if (AliasRW.HasVariants) {
const RecVec VarDefs = AliasRW.TheDef->getValueAsListOfDefs("Variants");
@@ -1516,8 +1507,7 @@ void PredTransitions::getIntersectingVariants(
// The first variant builds on the existing transition.
Variant.TransVecIdx = TransIdx;
IntersectingVariants.push_back(Variant);
- }
- else {
+ } else {
// Push another copy of the current transition for more variants.
Variant.TransVecIdx = TransVec.size();
IntersectingVariants.push_back(Variant);
@@ -1525,15 +1515,15 @@ void PredTransitions::getIntersectingVariants(
}
}
if (GenericRW && IntersectingVariants.empty()) {
- PrintFatalError(SchedRW.TheDef->getLoc(), "No variant of this type has "
+ PrintFatalError(SchedRW.TheDef->getLoc(),
+ "No variant of this type has "
"a matching predicate on any processor");
}
}
// Push the Reads/Writes selected by this variant onto the PredTransition
// specified by VInfo.
-void PredTransitions::
-pushVariant(const TransVariant &VInfo, bool IsRead) {
+void PredTransitions::pushVariant(const TransVariant &VInfo, bool IsRead) {
PredTransition &Trans = TransVec[VInfo.TransVecIdx];
// If this operand transition is reached through a processor-specific alias,
@@ -1541,11 +1531,10 @@ pushVariant(const TransVariant &VInfo, bool IsRead) {
IdxVec SelectedRWs;
if (VInfo.VarOrSeqDef->isSubClassOf("SchedVar")) {
Record *PredDef = VInfo.VarOrSeqDef->getValueAsDef("Predicate");
- Trans.PredTerm.emplace_back(IsRead, VInfo.RWIdx,PredDef);
+ Trans.PredTerm.emplace_back(IsRead, VInfo.RWIdx, PredDef);
RecVec SelectedDefs = VInfo.VarOrSeqDef->getValueAsListOfDefs("Selected");
SchedModels.findRWs(SelectedDefs, SelectedRWs, IsRead);
- }
- else {
+ } else {
assert(VInfo.VarOrSeqDef->isSubClassOf("WriteSequence") &&
"variant must be a SchedVariant or aliased WriteSequence");
SelectedRWs.push_back(SchedModels.getSchedRWIdx(VInfo.VarOrSeqDef, IsRead));
@@ -1553,10 +1542,10 @@ pushVariant(const TransVariant &VInfo, bool IsRead) {
const CodeGenSchedRW &SchedRW = SchedModels.getSchedRW(VInfo.RWIdx, IsRead);
- SmallVectorImpl<SmallVector<unsigned,4>> &RWSequences = IsRead
- ? Trans.ReadSequences : Trans.WriteSequences;
+ SmallVectorImpl<SmallVector<unsigned, 4>> &RWSequences =
+ IsRead ? Trans.ReadSequences : Trans.WriteSequences;
if (SchedRW.IsVariadic) {
- unsigned OperIdx = RWSequences.size()-1;
+ unsigned OperIdx = RWSequences.size() - 1;
// Make N-1 copies of this transition's last sequence.
RWSequences.reserve(RWSequences.size() + SelectedRWs.size() - 1);
RWSequences.insert(RWSequences.end(), SelectedRWs.size() - 1,
@@ -1565,8 +1554,8 @@ pushVariant(const TransVariant &VInfo, bool IsRead) {
// sequence (split the current operand into N operands).
// Note that write sequences should be expanded within this loop--the entire
// sequence belongs to a single operand.
- for (IdxIter RWI = SelectedRWs.begin(), RWE = SelectedRWs.end();
- RWI != RWE; ++RWI, ++OperIdx) {
+ for (IdxIter RWI = SelectedRWs.begin(), RWE = SelectedRWs.end(); RWI != RWE;
+ ++RWI, ++OperIdx) {
IdxVec ExpandedRWs;
if (IsRead)
ExpandedRWs.push_back(*RWI);
@@ -1575,8 +1564,7 @@ pushVariant(const TransVariant &VInfo, bool IsRead) {
llvm::append_range(RWSequences[OperIdx], ExpandedRWs);
}
assert(OperIdx == RWSequences.size() && "missed a sequence");
- }
- else {
+ } else {
// Push this transition's expanded sequence onto this transition's last
// sequence (add to the current operand's sequence).
SmallVectorImpl<unsigned> &Seq = RWSequences.back();
@@ -1644,8 +1632,9 @@ bool PredTransitions::substituteVariants(const PredTransition &Trans) {
// Visit each original write sequence.
for (const auto &WriteSequence : Trans.WriteSequences) {
// Push a new (empty) write sequence onto all partial Transitions.
- for (std::vector<PredTransition>::iterator I =
- TransVec.begin() + StartIdx, E = TransVec.end(); I != E; ++I) {
+ for (std::vector<PredTransition>::iterator I = TransVec.begin() + StartIdx,
+ E = TransVec.end();
+ I != E; ++I) {
I->WriteSequences.emplace_back();
}
Subst |=
@@ -1654,8 +1643,9 @@ bool PredTransitions::substituteVariants(const PredTransition &Trans) {
// Visit each original read sequence.
for (const auto &ReadSequence : Trans.ReadSequences) {
// Push a new (empty) read sequence onto all partial Transitions.
- for (std::vector<PredTransition>::iterator I =
- TransVec.begin() + StartIdx, E = TransVec.end(); I != E; ++I) {
+ for (std::vector<PredTransition>::iterator I = TransVec.begin() + StartIdx,
+ E = TransVec.end();
+ I != E; ++I) {
I->ReadSequences.emplace_back();
}
Subst |= substituteVariantOperand(ReadSequence, /*IsRead=*/true, StartIdx);
@@ -1814,7 +1804,7 @@ bool CodeGenSchedModels::hasSuperGroup(RecVec &SubUnits, CodeGenProcModel &PM) {
continue;
RecVec SuperUnits = ProcResourceDef->getValueAsListOfDefs("Resources");
RecIter RI = SubUnits.begin(), RE = SubUnits.end();
- for ( ; RI != RE; ++RI) {
+ for (; RI != RE; ++RI) {
if (!is_contained(SuperUnits, *RI)) {
break;
}
@@ -1831,22 +1821,22 @@ void CodeGenSchedModels::verifyProcResourceGroups(CodeGenProcModel &PM) {
if (!PM.ProcResourceDefs[i]->isSubClassOf("ProcResGroup"))
continue;
RecVec CheckUnits =
- PM.ProcResourceDefs[i]->getValueAsListOfDefs("Resources");
- for (unsigned j = i+1; j < e; ++j) {
+ PM.ProcResourceDefs[i]->getValueAsListOfDefs("Resources");
+ for (unsigned j = i + 1; j < e; ++j) {
if (!PM.ProcResourceDefs[j]->isSubClassOf("ProcResGroup"))
continue;
RecVec OtherUnits =
- PM.ProcResourceDefs[j]->getValueAsListOfDefs("Resources");
+ PM.ProcResourceDefs[j]->getValueAsListOfDefs("Resources");
if (std::find_first_of(CheckUnits.begin(), CheckUnits.end(),
- OtherUnits.begin(), OtherUnits.end())
- != CheckUnits.end()) {
+ OtherUnits.begin(),
+ OtherUnits.end()) != CheckUnits.end()) {
// CheckUnits and OtherUnits overlap
llvm::append_range(OtherUnits, CheckUnits);
if (!hasSuperGroup(OtherUnits, PM)) {
PrintFatalError((PM.ProcResourceDefs[i])->getLoc(),
- "proc resource group overlaps with "
- + PM.ProcResourceDefs[j]->getName()
- + " but no supergroup contains both.");
+ "proc resource group overlaps with " +
+ PM.ProcResourceDefs[j]->getName() +
+ " but no supergroup contains both.");
}
}
}
@@ -1862,7 +1852,7 @@ void CodeGenSchedModels::collectRegisterFiles() {
// For each register file definition, construct a CodeGenRegisterFile object
// and add it to the appropriate scheduling model.
CodeGenProcModel &PM = getProcModel(RF->getValueAsDef("SchedModel"));
- PM.RegisterFiles.emplace_back(CodeGenRegisterFile(RF->getName(),RF));
+ PM.RegisterFiles.emplace_back(CodeGenRegisterFile(RF->getName(), RF));
CodeGenRegisterFile &CGRF = PM.RegisterFiles.back();
CGRF.MaxMovesEliminatedPerCycle =
RF->getValueAsInt("MaxMovesEliminatedPerCycle");
@@ -2013,7 +2003,7 @@ void CodeGenSchedModels::checkCompleteness() {
PrintError(Inst->TheDef->getLoc(),
"No schedule information for instruction '" +
Inst->TheDef->getName() + "' in SchedMachineModel '" +
- ProcModel.ModelDef->getName() + "'");
+ ProcModel.ModelDef->getName() + "'");
Complete = false;
}
continue;
@@ -2039,14 +2029,18 @@ void CodeGenSchedModels::checkCompleteness() {
}
}
if (!Complete) {
- errs() << "\n\nIncomplete schedule models found.\n"
- << "- Consider setting 'CompleteModel = 0' while developing new models.\n"
- << "- Pseudo instructions can be marked with 'hasNoSchedulingInfo = 1'.\n"
- << "- Instructions should usually have Sched<[...]> as a superclass, "
- "you may temporarily use an empty list.\n"
- << "- Instructions related to unsupported features can be excluded with "
- "list<Predicate> UnsupportedFeatures = [HasA,..,HasY]; in the "
- "processor model.\n\n";
+ errs()
+ << "\n\nIncomplete schedule models found.\n"
+ << "- Consider setting 'CompleteModel = 0' while developing new "
+ "models.\n"
+ << "- Pseudo instructions can be marked with 'hasNoSchedulingInfo = "
+ "1'.\n"
+ << "- Instructions should usually have Sched<[...]> as a superclass, "
+ "you may temporarily use an empty list.\n"
+ << "- Instructions related to unsupported features can be excluded "
+ "with "
+ "list<Predicate> UnsupportedFeatures = [HasA,..,HasY]; in the "
+ "processor model.\n\n";
PrintFatalError("Incomplete schedule model");
}
}
@@ -2057,15 +2051,15 @@ void CodeGenSchedModels::collectItinProcResources(Record *ItinClassDef) {
const CodeGenProcModel &PM = ProcModels[PIdx];
// For all ItinRW entries.
bool HasMatch = false;
- for (RecIter II = PM.ItinRWDefs.begin(), IE = PM.ItinRWDefs.end();
- II != IE; ++II) {
+ for (RecIter II = PM.ItinRWDefs.begin(), IE = PM.ItinRWDefs.end(); II != IE;
+ ++II) {
RecVec Matched = (*II)->getValueAsListOfDefs("MatchedItinClasses");
if (!llvm::is_contained(Matched, ItinClassDef))
continue;
if (HasMatch)
- PrintFatalError((*II)->getLoc(), "Duplicate itinerary class "
- + ItinClassDef->getName()
- + " in ItinResources for " + PM.ModelName);
+ PrintFatalError((*II)->getLoc(),
+ "Duplicate itinerary class " + ItinClassDef->getName() +
+ " in ItinResources for " + PM.ModelName);
HasMatch = true;
IdxVec Writes, Reads;
findRWs((*II)->getValueAsListOfDefs("OperandReadWrites"), Writes, Reads);
@@ -2081,8 +2075,7 @@ void CodeGenSchedModels::collectRWResources(unsigned RWIdx, bool IsRead,
if (!IsRead && SchedRW.TheDef->isSubClassOf("SchedWriteRes")) {
for (unsigned Idx : ProcIndices)
addWriteRes(SchedRW.TheDef, Idx);
- }
- else if (IsRead && SchedRW.TheDef->isSubClassOf("SchedReadAdvance")) {
+ } else if (IsRead && SchedRW.TheDef->isSubClassOf("SchedReadAdvance")) {
for (unsigned Idx : ProcIndices)
addReadAdvance(SchedRW.TheDef, Idx);
}
@@ -2128,31 +2121,30 @@ Record *CodeGenSchedModels::findProcResUnits(Record *ProcResKind,
assert(!ProcResGroups.empty());
for (Record *ProcResDef : ProcResourceDefs) {
- if (ProcResDef->getValueAsDef("Kind") == ProcResKind
- && ProcResDef->getValueAsDef("SchedModel") == PM.ModelDef) {
+ if (ProcResDef->getValueAsDef("Kind") == ProcResKind &&
+ ProcResDef->getValueAsDef("SchedModel") == PM.ModelDef) {
if (ProcUnitDef) {
PrintFatalError(Loc,
- "Multiple ProcessorResourceUnits associated with "
- + ProcResKind->getName());
+ "Multiple ProcessorResourceUnits associated with " +
+ ProcResKind->getName());
}
ProcUnitDef = ProcResDef;
}
}
for (Record *ProcResGroup : ProcResGroups) {
- if (ProcResGroup == ProcResKind
- && ProcResGroup->getValueAsDef("SchedModel") == PM.ModelDef) {
+ if (ProcResGroup == ProcResKind &&
+ ProcResGroup->getValueAsDef("SchedModel") == PM.ModelDef) {
if (ProcUnitDef) {
PrintFatalError(Loc,
- "Multiple ProcessorResourceUnits associated with "
- + ProcResKind->getName());
+ "Multiple ProcessorResourceUnits associated with " +
+ ProcResKind->getName());
}
ProcUnitDef = ProcResGroup;
}
}
if (!ProcUnitDef) {
- PrintFatalError(Loc,
- "No ProcessorResources associated with "
- + ProcResKind->getName());
+ PrintFatalError(Loc, "No ProcessorResources associated with " +
+ ProcResKind->getName());
}
return ProcUnitDef;
}
@@ -2208,14 +2200,16 @@ unsigned CodeGenProcModel::getProcResourceIdx(Record *PRDef) const {
RecIter PRPos = find(ProcResourceDefs, PRDef);
if (PRPos == ProcResourceDefs.end())
PrintFatalError(PRDef->getLoc(), "ProcResource def is not included in "
- "the ProcResources list for " + ModelName);
+ "the ProcResources list for " +
+ ModelName);
// Idx=0 is reserved for invalid.
return 1 + (PRPos - ProcResourceDefs.begin());
}
bool CodeGenProcModel::isUnsupported(const CodeGenInstruction &Inst) const {
for (const Record *TheDef : UnsupportedFeaturesDefs) {
- for (const Record *PredDef : Inst.TheDef->getValueAsListOfDefs("Predicates")) {
+ for (const Record *PredDef :
+ Inst.TheDef->getValueAsListOfDefs("Predicates")) {
if (TheDef->getName() == PredDef->getName())
return true;
}
@@ -2239,12 +2233,11 @@ void CodeGenSchedRW::dump() const {
}
}
-void CodeGenSchedClass::dump(const CodeGenSchedModels* SchedModels) const {
- dbgs() << "SCHEDCLASS " << Index << ":" << Name << '\n'
- << " Writes: ";
+void CodeGenSchedClass::dump(const CodeGenSchedModels *SchedModels) const {
+ dbgs() << "SCHEDCLASS " << Index << ":" << Name << '\n' << " Writes: ";
for (unsigned i = 0, N = Writes.size(); i < N; ++i) {
SchedModels->getSchedWrite(Writes[i]).dump();
- if (i < N-1) {
+ if (i < N - 1) {
dbgs() << '\n';
dbgs().indent(10);
}
@@ -2252,12 +2245,13 @@ void CodeGenSchedClass::dump(const CodeGenSchedModels* SchedModels) const {
dbgs() << "\n Reads: ";
for (unsigned i = 0, N = Reads.size(); i < N; ++i) {
SchedModels->getSchedRead(Reads[i]).dump();
- if (i < N-1) {
+ if (i < N - 1) {
dbgs() << '\n';
dbgs().indent(10);
}
}
- dbgs() << "\n ProcIdx: "; dumpIdxVec(ProcIndices);
+ dbgs() << "\n ProcIdx: ";
+ dumpIdxVec(ProcIndices);
if (!Transitions.empty()) {
dbgs() << "\n Transitions for Proc ";
for (const CodeGenSchedTransition &Transition : Transitions) {
diff --git a/llvm/utils/TableGen/CodeGenSchedule.h b/llvm/utils/TableGen/Common/CodeGenSchedule.h
similarity index 93%
rename from llvm/utils/TableGen/CodeGenSchedule.h
rename to llvm/utils/TableGen/Common/CodeGenSchedule.h
index 76ef1e43953078..61980e7e196e5d 100644
--- a/llvm/utils/TableGen/CodeGenSchedule.h
+++ b/llvm/utils/TableGen/Common/CodeGenSchedule.h
@@ -33,8 +33,8 @@ class CodeGenTarget;
class CodeGenSchedModels;
class CodeGenInstruction;
-using RecVec = std::vector<Record*>;
-using RecIter = std::vector<Record*>::const_iterator;
+using RecVec = std::vector<Record *>;
+using RecIter = std::vector<Record *>::const_iterator;
using IdxVec = std::vector<unsigned>;
using IdxIter = std::vector<unsigned>::const_iterator;
@@ -59,10 +59,10 @@ struct CodeGenSchedRW {
RecVec Aliases;
CodeGenSchedRW()
- : Index(0), TheDef(nullptr), IsRead(false), IsAlias(false),
- HasVariants(false), IsVariadic(false), IsSequence(false) {}
+ : Index(0), TheDef(nullptr), IsRead(false), IsAlias(false),
+ HasVariants(false), IsVariadic(false), IsSequence(false) {}
CodeGenSchedRW(unsigned Idx, Record *Def)
- : Index(Idx), TheDef(Def), IsAlias(false), IsVariadic(false) {
+ : Index(Idx), TheDef(Def), IsAlias(false), IsVariadic(false) {
Name = std::string(Def->getName());
IsRead = Def->isSubClassOf("SchedRead");
HasVariants = Def->isSubClassOf("SchedVariant");
@@ -148,7 +148,7 @@ struct CodeGenSchedClass {
DenseSet<unsigned> InstRWProcIndices;
CodeGenSchedClass(unsigned Index, std::string Name, Record *ItinClassDef)
- : Index(Index), Name(std::move(Name)), ItinClassDef(ItinClassDef) {}
+ : Index(Index), Name(std::move(Name)), ItinClassDef(ItinClassDef) {}
bool isKeyEqual(Record *IC, ArrayRef<unsigned> W,
ArrayRef<unsigned> R) const {
@@ -173,7 +173,8 @@ struct CodeGenRegisterCost {
Record *RCDef;
unsigned Cost;
bool AllowMoveElimination;
- CodeGenRegisterCost(Record *RC, unsigned RegisterCost, bool AllowMoveElim = false)
+ CodeGenRegisterCost(Record *RC, unsigned RegisterCost,
+ bool AllowMoveElim = false)
: RCDef(RC), Cost(RegisterCost), AllowMoveElimination(AllowMoveElim) {}
CodeGenRegisterCost(const CodeGenRegisterCost &) = default;
CodeGenRegisterCost &operator=(const CodeGenRegisterCost &) = delete;
@@ -193,12 +194,12 @@ struct CodeGenRegisterFile {
unsigned NumPhysRegs;
std::vector<CodeGenRegisterCost> Costs;
- CodeGenRegisterFile(StringRef name, Record *def, unsigned MaxMoveElimPerCy = 0,
+ CodeGenRegisterFile(StringRef name, Record *def,
+ unsigned MaxMoveElimPerCy = 0,
bool AllowZeroMoveElimOnly = false)
: Name(name), RegisterFileDef(def),
MaxMovesEliminatedPerCycle(MaxMoveElimPerCy),
- AllowZeroMoveEliminationOnly(AllowZeroMoveElimOnly),
- NumPhysRegs(0) {}
+ AllowZeroMoveEliminationOnly(AllowZeroMoveElimOnly), NumPhysRegs(0) {}
bool hasDefaultCosts() const { return Costs.empty(); }
};
@@ -255,10 +256,9 @@ struct CodeGenProcModel {
Record *LoadQueue;
Record *StoreQueue;
- CodeGenProcModel(unsigned Idx, std::string Name, Record *MDef,
- Record *IDef) :
- Index(Idx), ModelName(std::move(Name)), ModelDef(MDef), ItinsDef(IDef),
- RetireControlUnit(nullptr), LoadQueue(nullptr), StoreQueue(nullptr) {}
+ CodeGenProcModel(unsigned Idx, std::string Name, Record *MDef, Record *IDef)
+ : Index(Idx), ModelName(std::move(Name)), ModelDef(MDef), ItinsDef(IDef),
+ RetireControlUnit(nullptr), LoadQueue(nullptr), StoreQueue(nullptr) {}
bool hasItineraries() const {
return !ItinsDef->getValueAsListOfDefs("IID").empty();
@@ -443,14 +443,14 @@ class CodeGenSchedModels {
// Map each instruction to its unique SchedClass index considering the
// combination of it's itinerary class, SchedRW list, and InstRW records.
- using InstClassMapTy = DenseMap<Record*, unsigned>;
+ using InstClassMapTy = DenseMap<Record *, unsigned>;
InstClassMapTy InstrClassMap;
std::vector<STIPredicateFunction> STIPredicates;
std::vector<unsigned> getAllProcIndices() const;
public:
- CodeGenSchedModels(RecordKeeper& RK, const CodeGenTarget &TGT);
+ CodeGenSchedModels(RecordKeeper &RK, const CodeGenTarget &TGT);
// iterator access to the scheduling classes.
using class_iterator = std::vector<CodeGenSchedClass>::iterator;
@@ -460,10 +460,10 @@ class CodeGenSchedModels {
class_iterator classes_end() { return SchedClasses.end(); }
const_class_iterator classes_end() const { return SchedClasses.end(); }
iterator_range<class_iterator> classes() {
- return make_range(classes_begin(), classes_end());
+ return make_range(classes_begin(), classes_end());
}
iterator_range<const_class_iterator> classes() const {
- return make_range(classes_begin(), classes_end());
+ return make_range(classes_begin(), classes_end());
}
iterator_range<class_iterator> explicit_classes() {
return make_range(classes_begin(), classes_begin() + NumInstrSchedClasses);
@@ -476,8 +476,8 @@ class CodeGenSchedModels {
Record *ModelDef = ProcDef->getValueAsDef("SchedModel");
Record *ItinsDef = ProcDef->getValueAsDef("ProcItin");
if (!ItinsDef->getValueAsListOfDefs("IID").empty()) {
- assert(ModelDef->getValueAsBit("NoModel")
- && "Itineraries must be defined within SchedMachineModel");
+ assert(ModelDef->getValueAsBit("NoModel") &&
+ "Itineraries must be defined within SchedMachineModel");
return ItinsDef;
}
return ModelDef;
@@ -496,7 +496,7 @@ class CodeGenSchedModels {
return ProcModels[I->second];
}
const CodeGenProcModel &getProcModel(Record *ModelDef) const {
- return const_cast<CodeGenSchedModels*>(this)->getProcModel(ModelDef);
+ return const_cast<CodeGenSchedModels *>(this)->getProcModel(ModelDef);
}
// Iterate over the unique processor models.
@@ -527,11 +527,11 @@ class CodeGenSchedModels {
CodeGenSchedRW &getSchedRW(Record *Def) {
bool IsRead = Def->isSubClassOf("SchedRead");
unsigned Idx = getSchedRWIdx(Def, IsRead);
- return const_cast<CodeGenSchedRW&>(
- IsRead ? getSchedRead(Idx) : getSchedWrite(Idx));
+ return const_cast<CodeGenSchedRW &>(IsRead ? getSchedRead(Idx)
+ : getSchedWrite(Idx));
}
const CodeGenSchedRW &getSchedRW(Record *Def) const {
- return const_cast<CodeGenSchedModels&>(*this).getSchedRW(Def);
+ return const_cast<CodeGenSchedModels &>(*this).getSchedRW(Def);
}
unsigned getSchedRWIdx(const Record *Def, bool IsRead) const;
@@ -579,6 +579,7 @@ class CodeGenSchedModels {
ArrayRef<STIPredicateFunction> getSTIPredicates() const {
return STIPredicates;
}
+
private:
void collectProcModels();
diff --git a/llvm/utils/TableGen/CodeGenTarget.cpp b/llvm/utils/TableGen/Common/CodeGenTarget.cpp
similarity index 94%
rename from llvm/utils/TableGen/CodeGenTarget.cpp
rename to llvm/utils/TableGen/Common/CodeGenTarget.cpp
index 37fa30349eea9f..584f9b87459894 100644
--- a/llvm/utils/TableGen/CodeGenTarget.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenTarget.cpp
@@ -49,10 +49,14 @@ MVT::SimpleValueType llvm::getValueType(const Record *Rec) {
StringRef llvm::getName(MVT::SimpleValueType T) {
switch (T) {
- case MVT::Other: return "UNKNOWN";
- case MVT::iPTR: return "TLI.getPointerTy()";
- case MVT::iPTRAny: return "TLI.getPointerTy()";
- default: return getEnumName(T);
+ case MVT::Other:
+ return "UNKNOWN";
+ case MVT::iPTR:
+ return "TLI.getPointerTy()";
+ case MVT::iPTRAny:
+ return "TLI.getPointerTy()";
+ default:
+ return getEnumName(T);
}
}
@@ -280,12 +284,11 @@ std::string llvm::getQualifiedName(const Record *R) {
return Namespace + "::" + R->getName().str();
}
-
/// getTarget - Return the current instance of the Target class.
///
CodeGenTarget::CodeGenTarget(RecordKeeper &records)
- : Records(records), CGH(records) {
- std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
+ : Records(records), CGH(records) {
+ std::vector<Record *> Targets = Records.getAllDerivedDefinitions("Target");
if (Targets.size() == 0)
PrintFatalError("No 'Target' subclasses defined!");
if (Targets.size() != 1)
@@ -294,8 +297,7 @@ CodeGenTarget::CodeGenTarget(RecordKeeper &records)
MacroFusions = Records.getAllDerivedDefinitions("Fusion");
}
-CodeGenTarget::~CodeGenTarget() {
-}
+CodeGenTarget::~CodeGenTarget() {}
StringRef CodeGenTarget::getName() const { return TargetRec->getName(); }
@@ -331,7 +333,7 @@ bool CodeGenTarget::getAllowRegisterRenaming() const {
/// getAsmParser - Return the AssemblyParser definition for this target.
///
Record *CodeGenTarget::getAsmParser() const {
- std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers");
+ std::vector<Record *> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers");
if (AsmParserNum >= LI.size())
PrintFatalError("Target does not have an AsmParser #" +
Twine(AsmParserNum) + "!");
@@ -342,8 +344,8 @@ Record *CodeGenTarget::getAsmParser() const {
/// this target.
///
Record *CodeGenTarget::getAsmParserVariant(unsigned i) const {
- std::vector<Record*> LI =
- TargetRec->getValueAsListOfDefs("AssemblyParserVariants");
+ std::vector<Record *> LI =
+ TargetRec->getValueAsListOfDefs("AssemblyParserVariants");
if (i >= LI.size())
PrintFatalError("Target does not have an AsmParserVariant #" + Twine(i) +
"!");
@@ -354,15 +356,15 @@ Record *CodeGenTarget::getAsmParserVariant(unsigned i) const {
/// available for this target.
///
unsigned CodeGenTarget::getAsmParserVariantCount() const {
- std::vector<Record*> LI =
- TargetRec->getValueAsListOfDefs("AssemblyParserVariants");
+ std::vector<Record *> LI =
+ TargetRec->getValueAsListOfDefs("AssemblyParserVariants");
return LI.size();
}
/// getAsmWriter - Return the AssemblyWriter definition for this target.
///
Record *CodeGenTarget::getAsmWriter() const {
- std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters");
+ std::vector<Record *> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters");
if (AsmWriterNum >= LI.size())
PrintFatalError("Target does not have an AsmWriter #" +
Twine(AsmWriterNum) + "!");
@@ -437,8 +439,7 @@ const CodeGenRegisterClass &CodeGenTarget::getRegisterClass(Record *R) const {
return *getRegBank().getRegClass(R);
}
-std::vector<ValueTypeByHwMode> CodeGenTarget::getRegisterVTs(Record *R)
- const {
+std::vector<ValueTypeByHwMode> CodeGenTarget::getRegisterVTs(Record *R) const {
const CodeGenRegister *Reg = getRegBank().getReg(R);
std::vector<ValueTypeByHwMode> Result;
for (const auto &RC : getRegBank().getRegClasses()) {
@@ -454,16 +455,15 @@ std::vector<ValueTypeByHwMode> CodeGenTarget::getRegisterVTs(Record *R)
return Result;
}
-
void CodeGenTarget::ReadLegalValueTypes() const {
for (const auto &RC : getRegBank().getRegClasses())
llvm::append_range(LegalValueTypes, RC.VTs);
// Remove duplicates.
llvm::sort(LegalValueTypes);
- LegalValueTypes.erase(std::unique(LegalValueTypes.begin(),
- LegalValueTypes.end()),
- LegalValueTypes.end());
+ LegalValueTypes.erase(
+ std::unique(LegalValueTypes.begin(), LegalValueTypes.end()),
+ LegalValueTypes.end());
}
CodeGenSchedModels &CodeGenTarget::getSchedModels() const {
@@ -473,7 +473,7 @@ CodeGenSchedModels &CodeGenTarget::getSchedModels() const {
}
void CodeGenTarget::ReadInstructions() const {
- std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
+ std::vector<Record *> Insts = Records.getAllDerivedDefinitions("Instruction");
if (Insts.size() <= 2)
PrintFatalError("No 'Instruction' subclasses defined!");
@@ -482,11 +482,10 @@ void CodeGenTarget::ReadInstructions() const {
Instructions[Insts[i]] = std::make_unique<CodeGenInstruction>(Insts[i]);
}
-static const CodeGenInstruction *
-GetInstByName(const char *Name,
- const DenseMap<const Record*,
- std::unique_ptr<CodeGenInstruction>> &Insts,
- RecordKeeper &Records) {
+static const CodeGenInstruction *GetInstByName(
+ const char *Name,
+ const DenseMap<const Record *, std::unique_ptr<CodeGenInstruction>> &Insts,
+ RecordKeeper &Records) {
const Record *Rec = Records.getDef(Name);
const auto I = Insts.find(Rec);
@@ -540,7 +539,6 @@ void CodeGenTarget::ComputeInstrsByEnum() const {
});
}
-
/// isLittleEndianEncoding - Return whether this target encodes its instruction
/// in little-endian format, i.e. bits laid out in the order [0..n]
///
@@ -571,7 +569,7 @@ void CodeGenTarget::reverseBitsForLittleEndianEncoding() {
unsigned bitSwapIdx = numBits - bit - 1;
Init *OrigBit = BI->getBit(bit);
Init *BitSwap = BI->getBit(bitSwapIdx);
- NewBits[bit] = BitSwap;
+ NewBits[bit] = BitSwap;
NewBits[bitSwapIdx] = OrigBit;
}
if (numBits % 2) {
@@ -600,10 +598,10 @@ bool CodeGenTarget::guessInstructionProperties() const {
// ComplexPattern implementation
//
ComplexPattern::ComplexPattern(Record *R) {
- Ty = R->getValueAsDef("Ty");
+ Ty = R->getValueAsDef("Ty");
NumOperands = R->getValueAsInt("NumOperands");
SelectFunc = std::string(R->getValueAsString("SelectFunc"));
- RootNodes = R->getValueAsListOfDefs("RootNodes");
+ RootNodes = R->getValueAsListOfDefs("RootNodes");
// FIXME: This is a hack to statically increase the priority of patterns which
// maps a sub-dag to a complex pattern. e.g. favors LEA over ADD. To get best
@@ -618,7 +616,7 @@ ComplexPattern::ComplexPattern(Record *R) {
// FIXME: Why is this different from parseSDPatternOperatorProperties?
// Parse the properties.
Properties = 0;
- std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties");
+ std::vector<Record *> PropList = R->getValueAsListOfDefs("Properties");
for (unsigned i = 0, e = PropList.size(); i != e; ++i)
if (PropList[i]->getName() == "SDNPHasChain") {
Properties |= 1 << SDNPHasChain;
diff --git a/llvm/utils/TableGen/CodeGenTarget.h b/llvm/utils/TableGen/Common/CodeGenTarget.h
similarity index 90%
rename from llvm/utils/TableGen/CodeGenTarget.h
rename to llvm/utils/TableGen/Common/CodeGenTarget.h
index 64c3f4470d5e08..05b7a936755d56 100644
--- a/llvm/utils/TableGen/CodeGenTarget.h
+++ b/llvm/utils/TableGen/Common/CodeGenTarget.h
@@ -16,9 +16,9 @@
#ifndef LLVM_UTILS_TABLEGEN_CODEGENTARGET_H
#define LLVM_UTILS_TABLEGEN_CODEGENTARGET_H
+#include "Basic/SDNodeProperties.h"
#include "CodeGenHwModes.h"
#include "InfoByHwMode.h"
-#include "SDNodeProperties.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SmallVector.h"
@@ -58,10 +58,10 @@ class CodeGenTarget {
RecordKeeper &Records;
Record *TargetRec;
- mutable DenseMap<const Record*,
- std::unique_ptr<CodeGenInstruction>> Instructions;
+ mutable DenseMap<const Record *, std::unique_ptr<CodeGenInstruction>>
+ Instructions;
mutable std::unique_ptr<CodeGenRegBank> RegBank;
- mutable std::vector<Record*> RegAltNameIndices;
+ mutable std::vector<Record *> RegAltNameIndices;
mutable SmallVector<ValueTypeByHwMode, 8> LegalValueTypes;
CodeGenHwModes CGH;
std::vector<Record *> MacroFusions;
@@ -73,8 +73,9 @@ class CodeGenTarget {
mutable std::unique_ptr<CodeGenSchedModels> SchedModels;
mutable StringRef InstNamespace;
- mutable std::vector<const CodeGenInstruction*> InstrsByEnum;
+ mutable std::vector<const CodeGenInstruction *> InstrsByEnum;
mutable unsigned NumPseudoInstructions = 0;
+
public:
CodeGenTarget(RecordKeeper &Records);
~CodeGenTarget();
@@ -130,8 +131,9 @@ class CodeGenTarget {
/// return it.
const CodeGenRegister *getRegisterByName(StringRef Name) const;
- const std::vector<Record*> &getRegAltNameIndices() const {
- if (RegAltNameIndices.empty()) ReadRegAltNameIndices();
+ const std::vector<Record *> &getRegAltNameIndices() const {
+ if (RegAltNameIndices.empty())
+ ReadRegAltNameIndices();
return RegAltNameIndices;
}
@@ -156,15 +158,17 @@ class CodeGenTarget {
const std::vector<Record *> getMacroFusions() const { return MacroFusions; }
private:
- DenseMap<const Record*, std::unique_ptr<CodeGenInstruction>> &
+ DenseMap<const Record *, std::unique_ptr<CodeGenInstruction>> &
getInstructions() const {
- if (Instructions.empty()) ReadInstructions();
+ if (Instructions.empty())
+ ReadInstructions();
return Instructions;
}
-public:
+public:
CodeGenInstruction &getInstruction(const Record *InstRec) const {
- if (Instructions.empty()) ReadInstructions();
+ if (Instructions.empty())
+ ReadInstructions();
auto I = Instructions.find(InstRec);
assert(I != Instructions.end() && "Not an instruction");
return *I->second;
@@ -193,10 +197,11 @@ class CodeGenTarget {
}
typedef ArrayRef<const CodeGenInstruction *>::const_iterator inst_iterator;
- inst_iterator inst_begin() const{return getInstructionsByEnumValue().begin();}
+ inst_iterator inst_begin() const {
+ return getInstructionsByEnumValue().begin();
+ }
inst_iterator inst_end() const { return getInstructionsByEnumValue().end(); }
-
/// isLittleEndianEncoding - are instruction bit patterns defined as [0..n]?
///
bool isLittleEndianEncoding() const;
@@ -219,22 +224,21 @@ class ComplexPattern {
Record *Ty;
unsigned NumOperands;
std::string SelectFunc;
- std::vector<Record*> RootNodes;
+ std::vector<Record *> RootNodes;
unsigned Properties; // Node properties
unsigned Complexity;
+
public:
ComplexPattern(Record *R);
Record *getValueType() const { return Ty; }
unsigned getNumOperands() const { return NumOperands; }
const std::string &getSelectFunc() const { return SelectFunc; }
- const std::vector<Record*> &getRootNodes() const {
- return RootNodes;
- }
+ const std::vector<Record *> &getRootNodes() const { return RootNodes; }
bool hasProperty(enum SDNP Prop) const { return Properties & (1 << Prop); }
unsigned getComplexity() const { return Complexity; }
};
-} // End llvm namespace
+} // namespace llvm
#endif
diff --git a/llvm/utils/TableGen/DAGISelMatcher.cpp b/llvm/utils/TableGen/Common/DAGISelMatcher.cpp
similarity index 89%
rename from llvm/utils/TableGen/DAGISelMatcher.cpp
rename to llvm/utils/TableGen/Common/DAGISelMatcher.cpp
index 1a5c728fafd9ca..54614811db977c 100644
--- a/llvm/utils/TableGen/DAGISelMatcher.cpp
+++ b/llvm/utils/TableGen/Common/DAGISelMatcher.cpp
@@ -15,11 +15,9 @@
#include "llvm/TableGen/Record.h"
using namespace llvm;
-void Matcher::anchor() { }
+void Matcher::anchor() {}
-void Matcher::dump() const {
- print(errs(), 0);
-}
+void Matcher::dump() const { print(errs(), 0); }
void Matcher::print(raw_ostream &OS, unsigned indent) const {
printImpl(OS, indent);
@@ -27,9 +25,7 @@ void Matcher::print(raw_ostream &OS, unsigned indent) const {
return Next->print(OS, indent);
}
-void Matcher::printOne(raw_ostream &OS) const {
- printImpl(OS, 0);
-}
+void Matcher::printOne(raw_ostream &OS) const { printImpl(OS, 0); }
/// unlinkNode - Unlink the specified node from this chain. If Other == this,
/// we unlink the next pointer and return it. Otherwise we unlink Other from
@@ -43,7 +39,8 @@ Matcher *Matcher::unlinkNode(Matcher *Other) {
for (; Cur && Cur->getNext() != Other; Cur = Cur->getNext())
/*empty*/;
- if (!Cur) return nullptr;
+ if (!Cur)
+ return nullptr;
Cur->takeNext();
Cur->setNext(Other->takeNext());
return this;
@@ -55,7 +52,8 @@ Matcher *Matcher::unlinkNode(Matcher *Other) {
bool Matcher::canMoveBefore(const Matcher *Other) const {
for (;; Other = Other->getNext()) {
assert(Other && "Other didn't come before 'this'?");
- if (this == Other) return true;
+ if (this == Other)
+ return true;
// We have to be able to move this node across the Other node.
if (!canMoveBeforeNode(Other))
@@ -78,7 +76,6 @@ bool Matcher::canMoveBeforeNode(const Matcher *Other) const {
return false;
}
-
ScopeMatcher::~ScopeMatcher() {
for (Matcher *C : Children)
delete C;
@@ -96,8 +93,8 @@ SwitchTypeMatcher::~SwitchTypeMatcher() {
CheckPredicateMatcher::CheckPredicateMatcher(
const TreePredicateFn &pred, const SmallVectorImpl<unsigned> &Ops)
- : Matcher(CheckPredicate), Pred(pred.getOrigPatFragRecord()),
- Operands(Ops.begin(), Ops.end()) {}
+ : Matcher(CheckPredicate), Pred(pred.getOrigPatFragRecord()),
+ Operands(Ops.begin(), Ops.end()) {}
TreePredicateFn CheckPredicateMatcher::getPredicate() const {
return TreePredicateFn(Pred);
@@ -112,16 +109,15 @@ unsigned CheckPredicateMatcher::getOperandNo(unsigned i) const {
return Operands[i];
}
-
// printImpl methods.
void ScopeMatcher::printImpl(raw_ostream &OS, unsigned indent) const {
OS.indent(indent) << "Scope\n";
for (const Matcher *C : Children) {
if (!C)
- OS.indent(indent+1) << "NULL POINTER\n";
+ OS.indent(indent + 1) << "NULL POINTER\n";
else
- C->print(OS, indent+2);
+ C->print(OS, indent + 2);
}
}
@@ -137,7 +133,8 @@ void RecordMemRefMatcher::printImpl(raw_ostream &OS, unsigned indent) const {
OS.indent(indent) << "RecordMemRef\n";
}
-void CaptureGlueInputMatcher::printImpl(raw_ostream &OS, unsigned indent) const{
+void CaptureGlueInputMatcher::printImpl(raw_ostream &OS,
+ unsigned indent) const {
OS.indent(indent) << "CaptureGlueInput\n";
}
@@ -161,8 +158,8 @@ void CheckChildSameMatcher::printImpl(raw_ostream &OS, unsigned indent) const {
OS.indent(indent) << "CheckChild" << ChildNo << "Same\n";
}
-void CheckPatternPredicateMatcher::
-printImpl(raw_ostream &OS, unsigned indent) const {
+void CheckPatternPredicateMatcher::printImpl(raw_ostream &OS,
+ unsigned indent) const {
OS.indent(indent) << "CheckPatternPredicate " << Predicate << '\n';
}
@@ -178,32 +175,30 @@ void SwitchOpcodeMatcher::printImpl(raw_ostream &OS, unsigned indent) const {
OS.indent(indent) << "SwitchOpcode: {\n";
for (const auto &C : Cases) {
OS.indent(indent) << "case " << C.first->getEnumName() << ":\n";
- C.second->print(OS, indent+2);
+ C.second->print(OS, indent + 2);
}
OS.indent(indent) << "}\n";
}
-
void CheckTypeMatcher::printImpl(raw_ostream &OS, unsigned indent) const {
- OS.indent(indent) << "CheckType " << getEnumName(Type) << ", ResNo="
- << ResNo << '\n';
+ OS.indent(indent) << "CheckType " << getEnumName(Type) << ", ResNo=" << ResNo
+ << '\n';
}
void SwitchTypeMatcher::printImpl(raw_ostream &OS, unsigned indent) const {
OS.indent(indent) << "SwitchType: {\n";
for (const auto &C : Cases) {
OS.indent(indent) << "case " << getEnumName(C.first) << ":\n";
- C.second->print(OS, indent+2);
+ C.second->print(OS, indent + 2);
}
OS.indent(indent) << "}\n";
}
void CheckChildTypeMatcher::printImpl(raw_ostream &OS, unsigned indent) const {
- OS.indent(indent) << "CheckChildType " << ChildNo << " "
- << getEnumName(Type) << '\n';
+ OS.indent(indent) << "CheckChildType " << ChildNo << " " << getEnumName(Type)
+ << '\n';
}
-
void CheckIntegerMatcher::printImpl(raw_ostream &OS, unsigned indent) const {
OS.indent(indent) << "CheckInteger " << Value << '\n';
}
@@ -258,8 +253,8 @@ void EmitIntegerMatcher::printImpl(raw_ostream &OS, unsigned indent) const {
<< '\n';
}
-void EmitStringIntegerMatcher::
-printImpl(raw_ostream &OS, unsigned indent) const {
+void EmitStringIntegerMatcher::printImpl(raw_ostream &OS,
+ unsigned indent) const {
OS.indent(indent) << "EmitStringInteger " << Val << " VT=" << getEnumName(VT)
<< '\n';
}
@@ -273,13 +268,13 @@ void EmitRegisterMatcher::printImpl(raw_ostream &OS, unsigned indent) const {
OS << " VT=" << getEnumName(VT) << '\n';
}
-void EmitConvertToTargetMatcher::
-printImpl(raw_ostream &OS, unsigned indent) const {
+void EmitConvertToTargetMatcher::printImpl(raw_ostream &OS,
+ unsigned indent) const {
OS.indent(indent) << "EmitConvertToTarget " << Slot << '\n';
}
-void EmitMergeInputChainsMatcher::
-printImpl(raw_ostream &OS, unsigned indent) const {
+void EmitMergeInputChainsMatcher::printImpl(raw_ostream &OS,
+ unsigned indent) const {
OS.indent(indent) << "EmitMergeInputChains <todo: args>\n";
}
@@ -289,10 +284,9 @@ void EmitCopyToRegMatcher::printImpl(raw_ostream &OS, unsigned indent) const {
void EmitNodeXFormMatcher::printImpl(raw_ostream &OS, unsigned indent) const {
OS.indent(indent) << "EmitNodeXForm " << NodeXForm->getName()
- << " Slot=" << Slot << '\n';
+ << " Slot=" << Slot << '\n';
}
-
void EmitNodeMatcherCommon::printImpl(raw_ostream &OS, unsigned indent) const {
OS.indent(indent);
OS << (isa<MorphNodeToMatcher>(this) ? "MorphNodeTo: " : "EmitNode: ")
@@ -316,7 +310,7 @@ bool CheckOpcodeMatcher::isEqualImpl(const Matcher *M) const {
// Note: pointer equality isn't enough here, we have to check the enum names
// to ensure that the nodes are for the same opcode.
return cast<CheckOpcodeMatcher>(M)->Opcode.getEnumName() ==
- Opcode.getEnumName();
+ Opcode.getEnumName();
}
bool EmitNodeMatcherCommon::isEqualImpl(const Matcher *m) const {
@@ -327,9 +321,9 @@ bool EmitNodeMatcherCommon::isEqualImpl(const Matcher *m) const {
M->NumFixedArityOperands == NumFixedArityOperands;
}
-void EmitNodeMatcher::anchor() { }
+void EmitNodeMatcher::anchor() {}
-void MorphNodeToMatcher::anchor() { }
+void MorphNodeToMatcher::anchor() {}
// isContradictoryImpl Implementations.
@@ -337,7 +331,8 @@ static bool TypesAreContradictory(MVT::SimpleValueType T1,
MVT::SimpleValueType T2) {
// If the two types are the same, then they are the same, so they don't
// contradict.
- if (T1 == T2) return false;
+ if (T1 == T2)
+ return false;
// If either type is about iPtr, then they don't conflict unless the other
// one is not a scalar integer type.
@@ -400,7 +395,8 @@ bool CheckIntegerMatcher::isContradictoryImpl(const Matcher *M) const {
}
bool CheckChildIntegerMatcher::isContradictoryImpl(const Matcher *M) const {
- if (const CheckChildIntegerMatcher *CCIM = dyn_cast<CheckChildIntegerMatcher>(M)) {
+ if (const CheckChildIntegerMatcher *CCIM =
+ dyn_cast<CheckChildIntegerMatcher>(M)) {
// If the two checks are about different nodes, we don't know if they
// conflict!
if (CCIM->getChildNo() != getChildNo())
diff --git a/llvm/utils/TableGen/DAGISelMatcher.h b/llvm/utils/TableGen/Common/DAGISelMatcher.h
similarity index 74%
rename from llvm/utils/TableGen/DAGISelMatcher.h
rename to llvm/utils/TableGen/Common/DAGISelMatcher.h
index 6615a15e467ea9..d4fe513e2e9674 100644
--- a/llvm/utils/TableGen/DAGISelMatcher.h
+++ b/llvm/utils/TableGen/Common/DAGISelMatcher.h
@@ -21,185 +21,186 @@
#include <utility>
namespace llvm {
- class CodeGenRegister;
- class CodeGenDAGPatterns;
- class CodeGenInstruction;
- class Matcher;
- class PatternToMatch;
- class raw_ostream;
- class ComplexPattern;
- class Record;
- class SDNodeInfo;
- class TreePredicateFn;
- class TreePattern;
-
- Matcher *ConvertPatternToMatcher(const PatternToMatch &Pattern,
- unsigned Variant,
- const CodeGenDAGPatterns &CGP);
- void OptimizeMatcher(std::unique_ptr<Matcher> &Matcher,
- const CodeGenDAGPatterns &CGP);
- void EmitMatcherTable(Matcher *Matcher, const CodeGenDAGPatterns &CGP,
- raw_ostream &OS);
-
- /// Matcher - Base class for all the DAG ISel Matcher representation
- /// nodes.
- class Matcher {
- // The next matcher node that is executed after this one. Null if this is
- // the last stage of a match.
- std::unique_ptr<Matcher> Next;
- size_t Size = 0; // Size in bytes of matcher and all its children (if any).
- virtual void anchor();
-
- public:
- enum KindTy {
- // Matcher state manipulation.
- Scope, // Push a checking scope.
- RecordNode, // Record the current node.
- RecordChild, // Record a child of the current node.
- RecordMemRef, // Record the memref in the current node.
- CaptureGlueInput, // If the current node has an input glue, save it.
- MoveChild, // Move current node to specified child.
- MoveSibling, // Move current node to specified sibling.
- MoveParent, // Move current node to parent.
-
- // Predicate checking.
- CheckSame, // Fail if not same as prev match.
- CheckChildSame, // Fail if child not same as prev match.
- CheckPatternPredicate,
- CheckPredicate, // Fail if node predicate fails.
- CheckOpcode, // Fail if not opcode.
- SwitchOpcode, // Dispatch based on opcode.
- CheckType, // Fail if not correct type.
- SwitchType, // Dispatch based on type.
- CheckChildType, // Fail if child has wrong type.
- CheckInteger, // Fail if wrong val.
- CheckChildInteger, // Fail if child is wrong val.
- CheckCondCode, // Fail if not condcode.
- CheckChild2CondCode, // Fail if child is wrong condcode.
- CheckValueType,
- CheckComplexPat,
- CheckAndImm,
- CheckOrImm,
- CheckImmAllOnesV,
- CheckImmAllZerosV,
- CheckFoldableChainNode,
-
- // Node creation/emisssion.
- EmitInteger, // Create a TargetConstant
- EmitStringInteger, // Create a TargetConstant from a string.
- EmitRegister, // Create a register.
- EmitConvertToTarget, // Convert a imm/fpimm to target imm/fpimm
- EmitMergeInputChains, // Merge together a chains for an input.
- EmitCopyToReg, // Emit a copytoreg into a physreg.
- EmitNode, // Create a DAG node
- EmitNodeXForm, // Run a SDNodeXForm
- CompleteMatch, // Finish a match and update the results.
- MorphNodeTo, // Build a node, finish a match and update results.
-
- // Highest enum value; watch out when adding more.
- HighestKind = MorphNodeTo
- };
- const KindTy Kind;
-
- protected:
- Matcher(KindTy K) : Kind(K) {}
-
- public:
- virtual ~Matcher() {}
-
- unsigned getSize() const { return Size; }
- void setSize(unsigned sz) { Size = sz; }
- KindTy getKind() const { return Kind; }
-
- Matcher *getNext() { return Next.get(); }
- const Matcher *getNext() const { return Next.get(); }
- void setNext(Matcher *C) { Next.reset(C); }
- Matcher *takeNext() { return Next.release(); }
-
- std::unique_ptr<Matcher> &getNextPtr() { return Next; }
-
- bool isEqual(const Matcher *M) const {
- if (getKind() != M->getKind())
- return false;
- return isEqualImpl(M);
- }
+class CodeGenRegister;
+class CodeGenDAGPatterns;
+class CodeGenInstruction;
+class Matcher;
+class PatternToMatch;
+class raw_ostream;
+class ComplexPattern;
+class Record;
+class SDNodeInfo;
+class TreePredicateFn;
+class TreePattern;
+
+Matcher *ConvertPatternToMatcher(const PatternToMatch &Pattern,
+ unsigned Variant,
+ const CodeGenDAGPatterns &CGP);
+void OptimizeMatcher(std::unique_ptr<Matcher> &Matcher,
+ const CodeGenDAGPatterns &CGP);
+void EmitMatcherTable(Matcher *Matcher, const CodeGenDAGPatterns &CGP,
+ raw_ostream &OS);
+
+/// Matcher - Base class for all the DAG ISel Matcher representation
+/// nodes.
+class Matcher {
+ // The next matcher node that is executed after this one. Null if this is
+ // the last stage of a match.
+ std::unique_ptr<Matcher> Next;
+ size_t Size = 0; // Size in bytes of matcher and all its children (if any).
+ virtual void anchor();
- /// isSimplePredicateNode - Return true if this is a simple predicate that
- /// operates on the node or its children without potential side effects or a
- /// change of the current node.
- bool isSimplePredicateNode() const {
- switch (getKind()) {
- default:
- return false;
- case CheckSame:
- case CheckChildSame:
- case CheckPatternPredicate:
- case CheckPredicate:
- case CheckOpcode:
- case CheckType:
- case CheckChildType:
- case CheckInteger:
- case CheckChildInteger:
- case CheckCondCode:
- case CheckChild2CondCode:
- case CheckValueType:
- case CheckAndImm:
- case CheckOrImm:
- case CheckImmAllOnesV:
- case CheckImmAllZerosV:
- case CheckFoldableChainNode:
- return true;
- }
- }
+public:
+ enum KindTy {
+ // Matcher state manipulation.
+ Scope, // Push a checking scope.
+ RecordNode, // Record the current node.
+ RecordChild, // Record a child of the current node.
+ RecordMemRef, // Record the memref in the current node.
+ CaptureGlueInput, // If the current node has an input glue, save it.
+ MoveChild, // Move current node to specified child.
+ MoveSibling, // Move current node to specified sibling.
+ MoveParent, // Move current node to parent.
+
+ // Predicate checking.
+ CheckSame, // Fail if not same as prev match.
+ CheckChildSame, // Fail if child not same as prev match.
+ CheckPatternPredicate,
+ CheckPredicate, // Fail if node predicate fails.
+ CheckOpcode, // Fail if not opcode.
+ SwitchOpcode, // Dispatch based on opcode.
+ CheckType, // Fail if not correct type.
+ SwitchType, // Dispatch based on type.
+ CheckChildType, // Fail if child has wrong type.
+ CheckInteger, // Fail if wrong val.
+ CheckChildInteger, // Fail if child is wrong val.
+ CheckCondCode, // Fail if not condcode.
+ CheckChild2CondCode, // Fail if child is wrong condcode.
+ CheckValueType,
+ CheckComplexPat,
+ CheckAndImm,
+ CheckOrImm,
+ CheckImmAllOnesV,
+ CheckImmAllZerosV,
+ CheckFoldableChainNode,
+
+ // Node creation/emisssion.
+ EmitInteger, // Create a TargetConstant
+ EmitStringInteger, // Create a TargetConstant from a string.
+ EmitRegister, // Create a register.
+ EmitConvertToTarget, // Convert a imm/fpimm to target imm/fpimm
+ EmitMergeInputChains, // Merge together a chains for an input.
+ EmitCopyToReg, // Emit a copytoreg into a physreg.
+ EmitNode, // Create a DAG node
+ EmitNodeXForm, // Run a SDNodeXForm
+ CompleteMatch, // Finish a match and update the results.
+ MorphNodeTo, // Build a node, finish a match and update results.
+
+ // Highest enum value; watch out when adding more.
+ HighestKind = MorphNodeTo
+ };
+ const KindTy Kind;
- /// isSimplePredicateOrRecordNode - Return true if this is a record node or
- /// a simple predicate.
- bool isSimplePredicateOrRecordNode() const {
- return isSimplePredicateNode() || getKind() == RecordNode ||
- getKind() == RecordChild;
- }
+protected:
+ Matcher(KindTy K) : Kind(K) {}
- /// unlinkNode - Unlink the specified node from this chain. If Other ==
- /// this, we unlink the next pointer and return it. Otherwise we unlink
- /// Other from the list and return this.
- Matcher *unlinkNode(Matcher *Other);
-
- /// canMoveBefore - Return true if this matcher is the same as Other, or if
- /// we can move this matcher past all of the nodes in-between Other and this
- /// node. Other must be equal to or before this.
- bool canMoveBefore(const Matcher *Other) const;
-
- /// canMoveBeforeNode - Return true if it is safe to move the current
- /// matcher across the specified one.
- bool canMoveBeforeNode(const Matcher *Other) const;
-
- /// isContradictory - Return true of these two matchers could never match on
- /// the same node.
- bool isContradictory(const Matcher *Other) const {
- // Since this predicate is reflexive, we canonicalize the ordering so that
- // we always match a node against nodes with kinds that are greater or
- // equal to them. For example, we'll pass in a CheckType node as an
- // argument to the CheckOpcode method, not the other way around.
- if (getKind() < Other->getKind())
- return isContradictoryImpl(Other);
- return Other->isContradictoryImpl(this);
+public:
+ virtual ~Matcher() {}
+
+ unsigned getSize() const { return Size; }
+ void setSize(unsigned sz) { Size = sz; }
+ KindTy getKind() const { return Kind; }
+
+ Matcher *getNext() { return Next.get(); }
+ const Matcher *getNext() const { return Next.get(); }
+ void setNext(Matcher *C) { Next.reset(C); }
+ Matcher *takeNext() { return Next.release(); }
+
+ std::unique_ptr<Matcher> &getNextPtr() { return Next; }
+
+ bool isEqual(const Matcher *M) const {
+ if (getKind() != M->getKind())
+ return false;
+ return isEqualImpl(M);
+ }
+
+ /// isSimplePredicateNode - Return true if this is a simple predicate that
+ /// operates on the node or its children without potential side effects or a
+ /// change of the current node.
+ bool isSimplePredicateNode() const {
+ switch (getKind()) {
+ default:
+ return false;
+ case CheckSame:
+ case CheckChildSame:
+ case CheckPatternPredicate:
+ case CheckPredicate:
+ case CheckOpcode:
+ case CheckType:
+ case CheckChildType:
+ case CheckInteger:
+ case CheckChildInteger:
+ case CheckCondCode:
+ case CheckChild2CondCode:
+ case CheckValueType:
+ case CheckAndImm:
+ case CheckOrImm:
+ case CheckImmAllOnesV:
+ case CheckImmAllZerosV:
+ case CheckFoldableChainNode:
+ return true;
}
+ }
- void print(raw_ostream &OS, unsigned indent = 0) const;
- void printOne(raw_ostream &OS) const;
- void dump() const;
+ /// isSimplePredicateOrRecordNode - Return true if this is a record node or
+ /// a simple predicate.
+ bool isSimplePredicateOrRecordNode() const {
+ return isSimplePredicateNode() || getKind() == RecordNode ||
+ getKind() == RecordChild;
+ }
- protected:
- virtual void printImpl(raw_ostream &OS, unsigned indent) const = 0;
- virtual bool isEqualImpl(const Matcher *M) const = 0;
- virtual bool isContradictoryImpl(const Matcher *M) const { return false; }
- };
+ /// unlinkNode - Unlink the specified node from this chain. If Other ==
+ /// this, we unlink the next pointer and return it. Otherwise we unlink
+ /// Other from the list and return this.
+ Matcher *unlinkNode(Matcher *Other);
+
+ /// canMoveBefore - Return true if this matcher is the same as Other, or if
+ /// we can move this matcher past all of the nodes in-between Other and this
+ /// node. Other must be equal to or before this.
+ bool canMoveBefore(const Matcher *Other) const;
+
+ /// canMoveBeforeNode - Return true if it is safe to move the current
+ /// matcher across the specified one.
+ bool canMoveBeforeNode(const Matcher *Other) const;
+
+ /// isContradictory - Return true of these two matchers could never match on
+ /// the same node.
+ bool isContradictory(const Matcher *Other) const {
+ // Since this predicate is reflexive, we canonicalize the ordering so that
+ // we always match a node against nodes with kinds that are greater or
+ // equal to them. For example, we'll pass in a CheckType node as an
+ // argument to the CheckOpcode method, not the other way around.
+ if (getKind() < Other->getKind())
+ return isContradictoryImpl(Other);
+ return Other->isContradictoryImpl(this);
+ }
+
+ void print(raw_ostream &OS, unsigned indent = 0) const;
+ void printOne(raw_ostream &OS) const;
+ void dump() const;
+
+protected:
+ virtual void printImpl(raw_ostream &OS, unsigned indent) const = 0;
+ virtual bool isEqualImpl(const Matcher *M) const = 0;
+ virtual bool isContradictoryImpl(const Matcher *M) const { return false; }
+};
/// ScopeMatcher - This attempts to match each of its children to find the first
/// one that successfully matches. If one child fails, it tries the next child.
/// If none of the children match then this check fails. It never has a 'next'.
class ScopeMatcher : public Matcher {
- SmallVector<Matcher*, 4> Children;
+ SmallVector<Matcher *, 4> Children;
+
public:
ScopeMatcher(SmallVectorImpl<Matcher *> &&children)
: Matcher(Scope), Children(std::move(children)) {}
@@ -230,9 +231,7 @@ class ScopeMatcher : public Matcher {
Children.resize(NC);
}
- static bool classof(const Matcher *N) {
- return N->getKind() == Scope;
- }
+ static bool classof(const Matcher *N) { return N->getKind() == Scope; }
private:
void printImpl(raw_ostream &OS, unsigned indent) const override;
@@ -248,16 +247,15 @@ class RecordMatcher : public Matcher {
/// ResultNo - The slot number in the RecordedNodes vector that this will be,
/// just printed as a comment.
unsigned ResultNo;
+
public:
RecordMatcher(const std::string &whatfor, unsigned resultNo)
- : Matcher(RecordNode), WhatFor(whatfor), ResultNo(resultNo) {}
+ : Matcher(RecordNode), WhatFor(whatfor), ResultNo(resultNo) {}
const std::string &getWhatFor() const { return WhatFor; }
unsigned getResultNo() const { return ResultNo; }
- static bool classof(const Matcher *N) {
- return N->getKind() == RecordNode;
- }
+ static bool classof(const Matcher *N) { return N->getKind() == RecordNode; }
private:
void printImpl(raw_ostream &OS, unsigned indent) const override;
@@ -277,19 +275,18 @@ class RecordChildMatcher : public Matcher {
/// ResultNo - The slot number in the RecordedNodes vector that this will be,
/// just printed as a comment.
unsigned ResultNo;
+
public:
RecordChildMatcher(unsigned childno, const std::string &whatfor,
unsigned resultNo)
- : Matcher(RecordChild), ChildNo(childno), WhatFor(whatfor),
- ResultNo(resultNo) {}
+ : Matcher(RecordChild), ChildNo(childno), WhatFor(whatfor),
+ ResultNo(resultNo) {}
unsigned getChildNo() const { return ChildNo; }
const std::string &getWhatFor() const { return WhatFor; }
unsigned getResultNo() const { return ResultNo; }
- static bool classof(const Matcher *N) {
- return N->getKind() == RecordChild;
- }
+ static bool classof(const Matcher *N) { return N->getKind() == RecordChild; }
private:
void printImpl(raw_ostream &OS, unsigned indent) const override;
@@ -303,16 +300,13 @@ class RecordMemRefMatcher : public Matcher {
public:
RecordMemRefMatcher() : Matcher(RecordMemRef) {}
- static bool classof(const Matcher *N) {
- return N->getKind() == RecordMemRef;
- }
+ static bool classof(const Matcher *N) { return N->getKind() == RecordMemRef; }
private:
void printImpl(raw_ostream &OS, unsigned indent) const override;
bool isEqualImpl(const Matcher *M) const override { return true; }
};
-
/// CaptureGlueInputMatcher - If the current record has a glue input, record
/// it so that it is used as an input to the generated code.
class CaptureGlueInputMatcher : public Matcher {
@@ -332,14 +326,13 @@ class CaptureGlueInputMatcher : public Matcher {
/// specified child node.
class MoveChildMatcher : public Matcher {
unsigned ChildNo;
+
public:
MoveChildMatcher(unsigned childNo) : Matcher(MoveChild), ChildNo(childNo) {}
unsigned getChildNo() const { return ChildNo; }
- static bool classof(const Matcher *N) {
- return N->getKind() == MoveChild;
- }
+ static bool classof(const Matcher *N) { return N->getKind() == MoveChild; }
private:
void printImpl(raw_ostream &OS, unsigned indent) const override;
@@ -374,9 +367,7 @@ class MoveParentMatcher : public Matcher {
public:
MoveParentMatcher() : Matcher(MoveParent) {}
- static bool classof(const Matcher *N) {
- return N->getKind() == MoveParent;
- }
+ static bool classof(const Matcher *N) { return N->getKind() == MoveParent; }
private:
void printImpl(raw_ostream &OS, unsigned indent) const override;
@@ -388,15 +379,14 @@ class MoveParentMatcher : public Matcher {
/// when patterns have the same name in them, like '(mul GPR:$in, GPR:$in)'.
class CheckSameMatcher : public Matcher {
unsigned MatchNumber;
+
public:
CheckSameMatcher(unsigned matchnumber)
- : Matcher(CheckSame), MatchNumber(matchnumber) {}
+ : Matcher(CheckSame), MatchNumber(matchnumber) {}
unsigned getMatchNumber() const { return MatchNumber; }
- static bool classof(const Matcher *N) {
- return N->getKind() == CheckSame;
- }
+ static bool classof(const Matcher *N) { return N->getKind() == CheckSame; }
private:
void printImpl(raw_ostream &OS, unsigned indent) const override;
@@ -411,9 +401,10 @@ class CheckSameMatcher : public Matcher {
class CheckChildSameMatcher : public Matcher {
unsigned ChildNo;
unsigned MatchNumber;
+
public:
CheckChildSameMatcher(unsigned childno, unsigned matchnumber)
- : Matcher(CheckChildSame), ChildNo(childno), MatchNumber(matchnumber) {}
+ : Matcher(CheckChildSame), ChildNo(childno), MatchNumber(matchnumber) {}
unsigned getChildNo() const { return ChildNo; }
unsigned getMatchNumber() const { return MatchNumber; }
@@ -435,9 +426,10 @@ class CheckChildSameMatcher : public Matcher {
/// not take a node as input. This is used for subtarget feature checks etc.
class CheckPatternPredicateMatcher : public Matcher {
std::string Predicate;
+
public:
CheckPatternPredicateMatcher(StringRef predicate)
- : Matcher(CheckPatternPredicate), Predicate(predicate) {}
+ : Matcher(CheckPatternPredicate), Predicate(predicate) {}
StringRef getPredicate() const { return Predicate; }
@@ -457,6 +449,7 @@ class CheckPatternPredicateMatcher : public Matcher {
class CheckPredicateMatcher : public Matcher {
TreePattern *Pred;
const SmallVector<unsigned, 4> Operands;
+
public:
CheckPredicateMatcher(const TreePredicateFn &pred,
const SmallVectorImpl<unsigned> &Operands);
@@ -476,20 +469,18 @@ class CheckPredicateMatcher : public Matcher {
}
};
-
/// CheckOpcodeMatcher - This checks to see if the current node has the
/// specified opcode, if not it fails to match.
class CheckOpcodeMatcher : public Matcher {
const SDNodeInfo &Opcode;
+
public:
CheckOpcodeMatcher(const SDNodeInfo &opcode)
- : Matcher(CheckOpcode), Opcode(opcode) {}
+ : Matcher(CheckOpcode), Opcode(opcode) {}
const SDNodeInfo &getOpcode() const { return Opcode; }
- static bool classof(const Matcher *N) {
- return N->getKind() == CheckOpcode;
- }
+ static bool classof(const Matcher *N) { return N->getKind() == CheckOpcode; }
private:
void printImpl(raw_ostream &OS, unsigned indent) const override;
@@ -502,16 +493,15 @@ class CheckOpcodeMatcher : public Matcher {
/// then the match fails. This is semantically equivalent to a Scope node where
/// every child does a CheckOpcode, but is much faster.
class SwitchOpcodeMatcher : public Matcher {
- SmallVector<std::pair<const SDNodeInfo*, Matcher*>, 8> Cases;
+ SmallVector<std::pair<const SDNodeInfo *, Matcher *>, 8> Cases;
+
public:
SwitchOpcodeMatcher(
SmallVectorImpl<std::pair<const SDNodeInfo *, Matcher *>> &&cases)
: Matcher(SwitchOpcode), Cases(std::move(cases)) {}
~SwitchOpcodeMatcher() override;
- static bool classof(const Matcher *N) {
- return N->getKind() == SwitchOpcode;
- }
+ static bool classof(const Matcher *N) { return N->getKind() == SwitchOpcode; }
unsigned getNumCases() const { return Cases.size(); }
@@ -529,16 +519,15 @@ class SwitchOpcodeMatcher : public Matcher {
class CheckTypeMatcher : public Matcher {
MVT::SimpleValueType Type;
unsigned ResNo;
+
public:
CheckTypeMatcher(MVT::SimpleValueType type, unsigned resno)
- : Matcher(CheckType), Type(type), ResNo(resno) {}
+ : Matcher(CheckType), Type(type), ResNo(resno) {}
MVT::SimpleValueType getType() const { return Type; }
unsigned getResNo() const { return ResNo; }
- static bool classof(const Matcher *N) {
- return N->getKind() == CheckType;
- }
+ static bool classof(const Matcher *N) { return N->getKind() == CheckType; }
private:
void printImpl(raw_ostream &OS, unsigned indent) const override;
@@ -553,16 +542,15 @@ class CheckTypeMatcher : public Matcher {
/// then the match fails. This is semantically equivalent to a Scope node where
/// every child does a CheckType, but is much faster.
class SwitchTypeMatcher : public Matcher {
- SmallVector<std::pair<MVT::SimpleValueType, Matcher*>, 8> Cases;
+ SmallVector<std::pair<MVT::SimpleValueType, Matcher *>, 8> Cases;
+
public:
SwitchTypeMatcher(
SmallVectorImpl<std::pair<MVT::SimpleValueType, Matcher *>> &&cases)
: Matcher(SwitchType), Cases(std::move(cases)) {}
~SwitchTypeMatcher() override;
- static bool classof(const Matcher *N) {
- return N->getKind() == SwitchType;
- }
+ static bool classof(const Matcher *N) { return N->getKind() == SwitchType; }
unsigned getNumCases() const { return Cases.size(); }
@@ -575,15 +563,15 @@ class SwitchTypeMatcher : public Matcher {
bool isEqualImpl(const Matcher *M) const override { return false; }
};
-
/// CheckChildTypeMatcher - This checks to see if a child node has the
/// specified type, if not it fails to match.
class CheckChildTypeMatcher : public Matcher {
unsigned ChildNo;
MVT::SimpleValueType Type;
+
public:
CheckChildTypeMatcher(unsigned childno, MVT::SimpleValueType type)
- : Matcher(CheckChildType), ChildNo(childno), Type(type) {}
+ : Matcher(CheckChildType), ChildNo(childno), Type(type) {}
unsigned getChildNo() const { return ChildNo; }
MVT::SimpleValueType getType() const { return Type; }
@@ -601,20 +589,17 @@ class CheckChildTypeMatcher : public Matcher {
bool isContradictoryImpl(const Matcher *M) const override;
};
-
/// CheckIntegerMatcher - This checks to see if the current node is a
/// ConstantSDNode with the specified integer value, if not it fails to match.
class CheckIntegerMatcher : public Matcher {
int64_t Value;
+
public:
- CheckIntegerMatcher(int64_t value)
- : Matcher(CheckInteger), Value(value) {}
+ CheckIntegerMatcher(int64_t value) : Matcher(CheckInteger), Value(value) {}
int64_t getValue() const { return Value; }
- static bool classof(const Matcher *N) {
- return N->getKind() == CheckInteger;
- }
+ static bool classof(const Matcher *N) { return N->getKind() == CheckInteger; }
private:
void printImpl(raw_ostream &OS, unsigned indent) const override;
@@ -629,9 +614,10 @@ class CheckIntegerMatcher : public Matcher {
class CheckChildIntegerMatcher : public Matcher {
unsigned ChildNo;
int64_t Value;
+
public:
CheckChildIntegerMatcher(unsigned childno, int64_t value)
- : Matcher(CheckChildInteger), ChildNo(childno), Value(value) {}
+ : Matcher(CheckChildInteger), ChildNo(childno), Value(value) {}
unsigned getChildNo() const { return ChildNo; }
int64_t getValue() const { return Value; }
@@ -653,9 +639,10 @@ class CheckChildIntegerMatcher : public Matcher {
/// CondCodeSDNode with the specified condition, if not it fails to match.
class CheckCondCodeMatcher : public Matcher {
StringRef CondCodeName;
+
public:
CheckCondCodeMatcher(StringRef condcodename)
- : Matcher(CheckCondCode), CondCodeName(condcodename) {}
+ : Matcher(CheckCondCode), CondCodeName(condcodename) {}
StringRef getCondCodeName() const { return CondCodeName; }
@@ -675,9 +662,10 @@ class CheckCondCodeMatcher : public Matcher {
/// CondCodeSDNode with the specified condition, if not it fails to match.
class CheckChild2CondCodeMatcher : public Matcher {
StringRef CondCodeName;
+
public:
CheckChild2CondCodeMatcher(StringRef condcodename)
- : Matcher(CheckChild2CondCode), CondCodeName(condcodename) {}
+ : Matcher(CheckChild2CondCode), CondCodeName(condcodename) {}
StringRef getCondCodeName() const { return CondCodeName; }
@@ -697,9 +685,10 @@ class CheckChild2CondCodeMatcher : public Matcher {
/// VTSDNode with the specified type, if not it fails to match.
class CheckValueTypeMatcher : public Matcher {
StringRef TypeName;
+
public:
CheckValueTypeMatcher(StringRef type_name)
- : Matcher(CheckValueType), TypeName(type_name) {}
+ : Matcher(CheckValueType), TypeName(type_name) {}
StringRef getTypeName() const { return TypeName; }
@@ -715,8 +704,6 @@ class CheckValueTypeMatcher : public Matcher {
bool isContradictoryImpl(const Matcher *M) const override;
};
-
-
/// CheckComplexPatMatcher - This node runs the specified ComplexPattern on
/// the current node.
class CheckComplexPatMatcher : public Matcher {
@@ -732,11 +719,12 @@ class CheckComplexPatMatcher : public Matcher {
/// FirstResult - This is the first slot in the RecordedNodes list that the
/// result of the match populates.
unsigned FirstResult;
+
public:
CheckComplexPatMatcher(const ComplexPattern &pattern, unsigned matchnumber,
const std::string &name, unsigned firstresult)
- : Matcher(CheckComplexPat), Pattern(pattern), MatchNumber(matchnumber),
- Name(name), FirstResult(firstresult) {}
+ : Matcher(CheckComplexPat), Pattern(pattern), MatchNumber(matchnumber),
+ Name(name), FirstResult(firstresult) {}
const ComplexPattern &getPattern() const { return Pattern; }
unsigned getMatchNumber() const { return MatchNumber; }
@@ -760,15 +748,13 @@ class CheckComplexPatMatcher : public Matcher {
/// with something equivalent to the specified immediate.
class CheckAndImmMatcher : public Matcher {
int64_t Value;
+
public:
- CheckAndImmMatcher(int64_t value)
- : Matcher(CheckAndImm), Value(value) {}
+ CheckAndImmMatcher(int64_t value) : Matcher(CheckAndImm), Value(value) {}
int64_t getValue() const { return Value; }
- static bool classof(const Matcher *N) {
- return N->getKind() == CheckAndImm;
- }
+ static bool classof(const Matcher *N) { return N->getKind() == CheckAndImm; }
private:
void printImpl(raw_ostream &OS, unsigned indent) const override;
@@ -781,15 +767,13 @@ class CheckAndImmMatcher : public Matcher {
/// with something equivalent to the specified immediate.
class CheckOrImmMatcher : public Matcher {
int64_t Value;
+
public:
- CheckOrImmMatcher(int64_t value)
- : Matcher(CheckOrImm), Value(value) {}
+ CheckOrImmMatcher(int64_t value) : Matcher(CheckOrImm), Value(value) {}
int64_t getValue() const { return Value; }
- static bool classof(const Matcher *N) {
- return N->getKind() == CheckOrImm;
- }
+ static bool classof(const Matcher *N) { return N->getKind() == CheckOrImm; }
private:
void printImpl(raw_ostream &OS, unsigned indent) const override;
@@ -834,8 +818,7 @@ class CheckImmAllZerosVMatcher : public Matcher {
/// (which defines a chain operand) is safe to fold into a larger pattern.
class CheckFoldableChainNodeMatcher : public Matcher {
public:
- CheckFoldableChainNodeMatcher()
- : Matcher(CheckFoldableChainNode) {}
+ CheckFoldableChainNodeMatcher() : Matcher(CheckFoldableChainNode) {}
static bool classof(const Matcher *N) {
return N->getKind() == CheckFoldableChainNode;
@@ -850,16 +833,15 @@ class CheckFoldableChainNodeMatcher : public Matcher {
class EmitIntegerMatcher : public Matcher {
int64_t Val;
MVT::SimpleValueType VT;
+
public:
EmitIntegerMatcher(int64_t val, MVT::SimpleValueType vt)
- : Matcher(EmitInteger), Val(val), VT(vt) {}
+ : Matcher(EmitInteger), Val(val), VT(vt) {}
int64_t getValue() const { return Val; }
MVT::SimpleValueType getVT() const { return VT; }
- static bool classof(const Matcher *N) {
- return N->getKind() == EmitInteger;
- }
+ static bool classof(const Matcher *N) { return N->getKind() == EmitInteger; }
private:
void printImpl(raw_ostream &OS, unsigned indent) const override;
@@ -874,9 +856,10 @@ class EmitIntegerMatcher : public Matcher {
class EmitStringIntegerMatcher : public Matcher {
std::string Val;
MVT::SimpleValueType VT;
+
public:
EmitStringIntegerMatcher(const std::string &val, MVT::SimpleValueType vt)
- : Matcher(EmitStringInteger), Val(val), VT(vt) {}
+ : Matcher(EmitStringInteger), Val(val), VT(vt) {}
const std::string &getValue() const { return Val; }
MVT::SimpleValueType getVT() const { return VT; }
@@ -899,16 +882,15 @@ class EmitRegisterMatcher : public Matcher {
/// this is a reference to zero_reg.
const CodeGenRegister *Reg;
MVT::SimpleValueType VT;
+
public:
EmitRegisterMatcher(const CodeGenRegister *reg, MVT::SimpleValueType vt)
- : Matcher(EmitRegister), Reg(reg), VT(vt) {}
+ : Matcher(EmitRegister), Reg(reg), VT(vt) {}
const CodeGenRegister *getReg() const { return Reg; }
MVT::SimpleValueType getVT() const { return VT; }
- static bool classof(const Matcher *N) {
- return N->getKind() == EmitRegister;
- }
+ static bool classof(const Matcher *N) { return N->getKind() == EmitRegister; }
private:
void printImpl(raw_ostream &OS, unsigned indent) const override;
@@ -923,9 +905,10 @@ class EmitRegisterMatcher : public Matcher {
/// ISD::TargetConstant, likewise for ConstantFP.
class EmitConvertToTargetMatcher : public Matcher {
unsigned Slot;
+
public:
EmitConvertToTargetMatcher(unsigned slot)
- : Matcher(EmitConvertToTarget), Slot(slot) {}
+ : Matcher(EmitConvertToTarget), Slot(slot) {}
unsigned getSlot() const { return Slot; }
@@ -946,9 +929,10 @@ class EmitConvertToTargetMatcher : public Matcher {
/// chains of these nodes if they are not themselves a node in the pattern.
class EmitMergeInputChainsMatcher : public Matcher {
SmallVector<unsigned, 3> ChainNodes;
+
public:
EmitMergeInputChainsMatcher(ArrayRef<unsigned> nodes)
- : Matcher(EmitMergeInputChains), ChainNodes(nodes.begin(), nodes.end()) {}
+ : Matcher(EmitMergeInputChains), ChainNodes(nodes.begin(), nodes.end()) {}
unsigned getNumNodes() const { return ChainNodes.size(); }
@@ -976,9 +960,8 @@ class EmitCopyToRegMatcher : public Matcher {
const CodeGenRegister *DestPhysReg;
public:
- EmitCopyToRegMatcher(unsigned srcSlot,
- const CodeGenRegister *destPhysReg)
- : Matcher(EmitCopyToReg), SrcSlot(srcSlot), DestPhysReg(destPhysReg) {}
+ EmitCopyToRegMatcher(unsigned srcSlot, const CodeGenRegister *destPhysReg)
+ : Matcher(EmitCopyToReg), SrcSlot(srcSlot), DestPhysReg(destPhysReg) {}
unsigned getSrcSlot() const { return SrcSlot; }
const CodeGenRegister *getDestPhysReg() const { return DestPhysReg; }
@@ -995,16 +978,15 @@ class EmitCopyToRegMatcher : public Matcher {
}
};
-
-
/// EmitNodeXFormMatcher - Emit an operation that runs an SDNodeXForm on a
/// recorded node and records the result.
class EmitNodeXFormMatcher : public Matcher {
unsigned Slot;
Record *NodeXForm;
+
public:
EmitNodeXFormMatcher(unsigned slot, Record *nodeXForm)
- : Matcher(EmitNodeXForm), Slot(slot), NodeXForm(nodeXForm) {}
+ : Matcher(EmitNodeXForm), Slot(slot), NodeXForm(nodeXForm) {}
unsigned getSlot() const { return Slot; }
Record *getNodeXForm() const { return NodeXForm; }
@@ -1033,6 +1015,7 @@ class EmitNodeMatcherCommon : public Matcher {
/// If this is a varidic node, this is set to the number of fixed arity
/// operands in the root of the pattern. The rest are appended to this node.
int NumFixedArityOperands;
+
public:
EmitNodeMatcherCommon(const CodeGenInstruction &cgi,
ArrayRef<MVT::SimpleValueType> vts,
@@ -1061,7 +1044,6 @@ class EmitNodeMatcherCommon : public Matcher {
const SmallVectorImpl<MVT::SimpleValueType> &getVTList() const { return VTs; }
const SmallVectorImpl<unsigned> &getOperandList() const { return Operands; }
-
bool hasChain() const { return HasChain; }
bool hasInGlue() const { return HasInGlue; }
bool hasOutGlue() const { return HasOutGlue; }
@@ -1081,6 +1063,7 @@ class EmitNodeMatcherCommon : public Matcher {
class EmitNodeMatcher : public EmitNodeMatcherCommon {
void anchor() override;
unsigned FirstResultSlot;
+
public:
EmitNodeMatcher(const CodeGenInstruction &cgi,
ArrayRef<MVT::SimpleValueType> vts,
@@ -1094,15 +1077,13 @@ class EmitNodeMatcher : public EmitNodeMatcherCommon {
unsigned getFirstResultSlot() const { return FirstResultSlot; }
- static bool classof(const Matcher *N) {
- return N->getKind() == EmitNode;
- }
-
+ static bool classof(const Matcher *N) { return N->getKind() == EmitNode; }
};
class MorphNodeToMatcher : public EmitNodeMatcherCommon {
void anchor() override;
const PatternToMatch &Pattern;
+
public:
MorphNodeToMatcher(const CodeGenInstruction &cgi,
ArrayRef<MVT::SimpleValueType> vts,
@@ -1116,9 +1097,7 @@ class MorphNodeToMatcher : public EmitNodeMatcherCommon {
const PatternToMatch &getPattern() const { return Pattern; }
- static bool classof(const Matcher *N) {
- return N->getKind() == MorphNodeTo;
- }
+ static bool classof(const Matcher *N) { return N->getKind() == MorphNodeTo; }
};
/// CompleteMatchMatcher - Complete a match by replacing the results of the
@@ -1127,11 +1106,12 @@ class MorphNodeToMatcher : public EmitNodeMatcherCommon {
class CompleteMatchMatcher : public Matcher {
SmallVector<unsigned, 2> Results;
const PatternToMatch &Pattern;
+
public:
CompleteMatchMatcher(ArrayRef<unsigned> results,
const PatternToMatch &pattern)
- : Matcher(CompleteMatch), Results(results.begin(), results.end()),
- Pattern(pattern) {}
+ : Matcher(CompleteMatch), Results(results.begin(), results.end()),
+ Pattern(pattern) {}
unsigned getNumResults() const { return Results.size(); }
unsigned getResult(unsigned R) const { return Results[R]; }
@@ -1145,7 +1125,7 @@ class CompleteMatchMatcher : public Matcher {
void printImpl(raw_ostream &OS, unsigned indent) const override;
bool isEqualImpl(const Matcher *M) const override {
return cast<CompleteMatchMatcher>(M)->Results == Results &&
- &cast<CompleteMatchMatcher>(M)->Pattern == &Pattern;
+ &cast<CompleteMatchMatcher>(M)->Pattern == &Pattern;
}
};
diff --git a/llvm/utils/TableGen/GlobalISel/CXXPredicates.cpp b/llvm/utils/TableGen/Common/GlobalISel/CXXPredicates.cpp
similarity index 100%
rename from llvm/utils/TableGen/GlobalISel/CXXPredicates.cpp
rename to llvm/utils/TableGen/Common/GlobalISel/CXXPredicates.cpp
diff --git a/llvm/utils/TableGen/GlobalISel/CXXPredicates.h b/llvm/utils/TableGen/Common/GlobalISel/CXXPredicates.h
similarity index 100%
rename from llvm/utils/TableGen/GlobalISel/CXXPredicates.h
rename to llvm/utils/TableGen/Common/GlobalISel/CXXPredicates.h
diff --git a/llvm/utils/TableGen/GlobalISel/CodeExpander.cpp b/llvm/utils/TableGen/Common/GlobalISel/CodeExpander.cpp
similarity index 100%
rename from llvm/utils/TableGen/GlobalISel/CodeExpander.cpp
rename to llvm/utils/TableGen/Common/GlobalISel/CodeExpander.cpp
diff --git a/llvm/utils/TableGen/GlobalISel/CodeExpander.h b/llvm/utils/TableGen/Common/GlobalISel/CodeExpander.h
similarity index 100%
rename from llvm/utils/TableGen/GlobalISel/CodeExpander.h
rename to llvm/utils/TableGen/Common/GlobalISel/CodeExpander.h
diff --git a/llvm/utils/TableGen/GlobalISel/CodeExpansions.h b/llvm/utils/TableGen/Common/GlobalISel/CodeExpansions.h
similarity index 100%
rename from llvm/utils/TableGen/GlobalISel/CodeExpansions.h
rename to llvm/utils/TableGen/Common/GlobalISel/CodeExpansions.h
diff --git a/llvm/utils/TableGen/GlobalISel/CombinerUtils.h b/llvm/utils/TableGen/Common/GlobalISel/CombinerUtils.h
similarity index 100%
rename from llvm/utils/TableGen/GlobalISel/CombinerUtils.h
rename to llvm/utils/TableGen/Common/GlobalISel/CombinerUtils.h
diff --git a/llvm/utils/TableGen/GlobalISelMatchTable.cpp b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
similarity index 99%
rename from llvm/utils/TableGen/GlobalISelMatchTable.cpp
rename to llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
index 051c536f113f7b..c21475aa1eefc7 100644
--- a/llvm/utils/TableGen/GlobalISelMatchTable.cpp
+++ b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp
@@ -7,8 +7,8 @@
//===----------------------------------------------------------------------===//
#include "GlobalISelMatchTable.h"
-#include "CodeGenInstruction.h"
-#include "CodeGenRegisters.h"
+#include "Common/CodeGenInstruction.h"
+#include "Common/CodeGenRegisters.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/LEB128.h"
diff --git a/llvm/utils/TableGen/GlobalISelMatchTable.h b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h
similarity index 99%
rename from llvm/utils/TableGen/GlobalISelMatchTable.h
rename to llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h
index 635552fc890406..1c50790a28ab02 100644
--- a/llvm/utils/TableGen/GlobalISelMatchTable.h
+++ b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h
@@ -16,7 +16,7 @@
#ifndef LLVM_UTILS_TABLEGEN_GLOBALISELMATCHTABLE_H
#define LLVM_UTILS_TABLEGEN_GLOBALISELMATCHTABLE_H
-#include "CodeGenDAGPatterns.h"
+#include "Common/CodeGenDAGPatterns.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/SmallPtrSet.h"
diff --git a/llvm/utils/TableGen/GlobalISelMatchTableExecutorEmitter.cpp b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTableExecutorEmitter.cpp
similarity index 100%
rename from llvm/utils/TableGen/GlobalISelMatchTableExecutorEmitter.cpp
rename to llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTableExecutorEmitter.cpp
diff --git a/llvm/utils/TableGen/GlobalISelMatchTableExecutorEmitter.h b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTableExecutorEmitter.h
similarity index 99%
rename from llvm/utils/TableGen/GlobalISelMatchTableExecutorEmitter.h
rename to llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTableExecutorEmitter.h
index 7e952d6df30939..d2b6a74c757713 100644
--- a/llvm/utils/TableGen/GlobalISelMatchTableExecutorEmitter.h
+++ b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTableExecutorEmitter.h
@@ -15,7 +15,7 @@
#ifndef LLVM_UTILS_TABLEGEN_GLOBALISELMATCHTABLEEXECUTOREMITTER_H
#define LLVM_UTILS_TABLEGEN_GLOBALISELMATCHTABLEEXECUTOREMITTER_H
-#include "SubtargetFeatureInfo.h"
+#include "Common/SubtargetFeatureInfo.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/Twine.h"
diff --git a/llvm/utils/TableGen/GlobalISel/MatchDataInfo.cpp b/llvm/utils/TableGen/Common/GlobalISel/MatchDataInfo.cpp
similarity index 100%
rename from llvm/utils/TableGen/GlobalISel/MatchDataInfo.cpp
rename to llvm/utils/TableGen/Common/GlobalISel/MatchDataInfo.cpp
diff --git a/llvm/utils/TableGen/GlobalISel/MatchDataInfo.h b/llvm/utils/TableGen/Common/GlobalISel/MatchDataInfo.h
similarity index 100%
rename from llvm/utils/TableGen/GlobalISel/MatchDataInfo.h
rename to llvm/utils/TableGen/Common/GlobalISel/MatchDataInfo.h
diff --git a/llvm/utils/TableGen/GlobalISel/Patterns.cpp b/llvm/utils/TableGen/Common/GlobalISel/Patterns.cpp
similarity index 99%
rename from llvm/utils/TableGen/GlobalISel/Patterns.cpp
rename to llvm/utils/TableGen/Common/GlobalISel/Patterns.cpp
index 758eac2dfebd30..388bf7e9e83344 100644
--- a/llvm/utils/TableGen/GlobalISel/Patterns.cpp
+++ b/llvm/utils/TableGen/Common/GlobalISel/Patterns.cpp
@@ -7,11 +7,11 @@
//===----------------------------------------------------------------------===//
#include "Patterns.h"
-#include "../CodeGenInstruction.h"
-#include "../CodeGenIntrinsics.h"
+#include "Basic/CodeGenIntrinsics.h"
#include "CXXPredicates.h"
#include "CodeExpander.h"
#include "CodeExpansions.h"
+#include "Common/CodeGenInstruction.h"
#include "llvm/ADT/StringSet.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
diff --git a/llvm/utils/TableGen/GlobalISel/Patterns.h b/llvm/utils/TableGen/Common/GlobalISel/Patterns.h
similarity index 100%
rename from llvm/utils/TableGen/GlobalISel/Patterns.h
rename to llvm/utils/TableGen/Common/GlobalISel/Patterns.h
diff --git a/llvm/utils/TableGen/InfoByHwMode.cpp b/llvm/utils/TableGen/Common/InfoByHwMode.cpp
similarity index 80%
rename from llvm/utils/TableGen/InfoByHwMode.cpp
rename to llvm/utils/TableGen/Common/InfoByHwMode.cpp
index 7e4ab534662187..6d9a35a68e138e 100644
--- a/llvm/utils/TableGen/InfoByHwMode.cpp
+++ b/llvm/utils/TableGen/Common/InfoByHwMode.cpp
@@ -11,8 +11,8 @@
// data).
//===----------------------------------------------------------------------===//
-#include "CodeGenTarget.h"
#include "InfoByHwMode.h"
+#include "CodeGenTarget.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/Twine.h"
#include "llvm/Support/Debug.h"
@@ -44,7 +44,7 @@ ValueTypeByHwMode::ValueTypeByHwMode(Record *R, MVT T) : ValueTypeByHwMode(T) {
PtrAddrSpace = R->getValueAsInt("AddrSpace");
}
-bool ValueTypeByHwMode::operator== (const ValueTypeByHwMode &T) const {
+bool ValueTypeByHwMode::operator==(const ValueTypeByHwMode &T) const {
assert(isValid() && T.isValid() && "Invalid type in assignment");
bool Simple = isSimple();
if (Simple != T.isSimple())
@@ -55,7 +55,7 @@ bool ValueTypeByHwMode::operator== (const ValueTypeByHwMode &T) const {
return Map == T.Map;
}
-bool ValueTypeByHwMode::operator< (const ValueTypeByHwMode &T) const {
+bool ValueTypeByHwMode::operator<(const ValueTypeByHwMode &T) const {
assert(isValid() && T.isValid() && "Invalid type in comparison");
// Default order for maps.
return Map < T.Map;
@@ -86,7 +86,7 @@ void ValueTypeByHwMode::writeToStream(raw_ostream &OS) const {
return;
}
- std::vector<const PairType*> Pairs;
+ std::vector<const PairType *> Pairs;
for (const auto &P : Map)
Pairs.push_back(&P);
llvm::sort(Pairs, deref<std::less<PairType>>());
@@ -100,9 +100,7 @@ void ValueTypeByHwMode::writeToStream(raw_ostream &OS) const {
}
LLVM_DUMP_METHOD
-void ValueTypeByHwMode::dump() const {
- dbgs() << *this << '\n';
-}
+void ValueTypeByHwMode::dump() const { dbgs() << *this << '\n'; }
ValueTypeByHwMode llvm::getValueTypeByHwMode(Record *Rec,
const CodeGenHwModes &CGH) {
@@ -123,24 +121,22 @@ RegSizeInfo::RegSizeInfo(Record *R, const CodeGenHwModes &CGH) {
SpillAlignment = R->getValueAsInt("SpillAlignment");
}
-bool RegSizeInfo::operator< (const RegSizeInfo &I) const {
+bool RegSizeInfo::operator<(const RegSizeInfo &I) const {
return std::tie(RegSize, SpillSize, SpillAlignment) <
std::tie(I.RegSize, I.SpillSize, I.SpillAlignment);
}
bool RegSizeInfo::isSubClassOf(const RegSizeInfo &I) const {
- return RegSize <= I.RegSize &&
- SpillAlignment && I.SpillAlignment % SpillAlignment == 0 &&
- SpillSize <= I.SpillSize;
+ return RegSize <= I.RegSize && SpillAlignment &&
+ I.SpillAlignment % SpillAlignment == 0 && SpillSize <= I.SpillSize;
}
void RegSizeInfo::writeToStream(raw_ostream &OS) const {
- OS << "[R=" << RegSize << ",S=" << SpillSize
- << ",A=" << SpillAlignment << ']';
+ OS << "[R=" << RegSize << ",S=" << SpillSize << ",A=" << SpillAlignment
+ << ']';
}
-RegSizeInfoByHwMode::RegSizeInfoByHwMode(Record *R,
- const CodeGenHwModes &CGH) {
+RegSizeInfoByHwMode::RegSizeInfoByHwMode(Record *R, const CodeGenHwModes &CGH) {
const HwModeSelect &MS = CGH.getHwModeSelect(R);
for (const HwModeSelect::PairType &P : MS.Items) {
auto I = Map.insert({P.first, RegSizeInfo(P.second, CGH)});
@@ -149,12 +145,12 @@ RegSizeInfoByHwMode::RegSizeInfoByHwMode(Record *R,
}
}
-bool RegSizeInfoByHwMode::operator< (const RegSizeInfoByHwMode &I) const {
+bool RegSizeInfoByHwMode::operator<(const RegSizeInfoByHwMode &I) const {
unsigned M0 = Map.begin()->first;
return get(M0) < I.get(M0);
}
-bool RegSizeInfoByHwMode::operator== (const RegSizeInfoByHwMode &I) const {
+bool RegSizeInfoByHwMode::operator==(const RegSizeInfoByHwMode &I) const {
unsigned M0 = Map.begin()->first;
return get(M0) == I.get(M0);
}
@@ -164,8 +160,8 @@ bool RegSizeInfoByHwMode::isSubClassOf(const RegSizeInfoByHwMode &I) const {
return get(M0).isSubClassOf(I.get(M0));
}
-bool RegSizeInfoByHwMode::hasStricterSpillThan(const RegSizeInfoByHwMode &I)
- const {
+bool RegSizeInfoByHwMode::hasStricterSpillThan(
+ const RegSizeInfoByHwMode &I) const {
unsigned M0 = Map.begin()->first;
const RegSizeInfo &A0 = get(M0);
const RegSizeInfo &B0 = I.get(M0);
@@ -175,7 +171,7 @@ bool RegSizeInfoByHwMode::hasStricterSpillThan(const RegSizeInfoByHwMode &I)
void RegSizeInfoByHwMode::writeToStream(raw_ostream &OS) const {
typedef typename decltype(Map)::value_type PairType;
- std::vector<const PairType*> Pairs;
+ std::vector<const PairType *> Pairs;
for (const auto &P : Map)
Pairs.push_back(&P);
llvm::sort(Pairs, deref<std::less<PairType>>());
@@ -187,7 +183,8 @@ void RegSizeInfoByHwMode::writeToStream(raw_ostream &OS) const {
OS << '}';
}
-EncodingInfoByHwMode::EncodingInfoByHwMode(Record *R, const CodeGenHwModes &CGH) {
+EncodingInfoByHwMode::EncodingInfoByHwMode(Record *R,
+ const CodeGenHwModes &CGH) {
const HwModeSelect &MS = CGH.getHwModeSelect(R);
for (const HwModeSelect::PairType &P : MS.Items) {
assert(P.second && P.second->isSubClassOf("InstructionEncoding") &&
@@ -199,18 +196,18 @@ EncodingInfoByHwMode::EncodingInfoByHwMode(Record *R, const CodeGenHwModes &CGH)
}
namespace llvm {
- raw_ostream &operator<<(raw_ostream &OS, const ValueTypeByHwMode &T) {
- T.writeToStream(OS);
- return OS;
- }
+raw_ostream &operator<<(raw_ostream &OS, const ValueTypeByHwMode &T) {
+ T.writeToStream(OS);
+ return OS;
+}
- raw_ostream &operator<<(raw_ostream &OS, const RegSizeInfo &T) {
- T.writeToStream(OS);
- return OS;
- }
+raw_ostream &operator<<(raw_ostream &OS, const RegSizeInfo &T) {
+ T.writeToStream(OS);
+ return OS;
+}
- raw_ostream &operator<<(raw_ostream &OS, const RegSizeInfoByHwMode &T) {
- T.writeToStream(OS);
- return OS;
- }
+raw_ostream &operator<<(raw_ostream &OS, const RegSizeInfoByHwMode &T) {
+ T.writeToStream(OS);
+ return OS;
}
+} // namespace llvm
diff --git a/llvm/utils/TableGen/InfoByHwMode.h b/llvm/utils/TableGen/Common/InfoByHwMode.h
similarity index 84%
rename from llvm/utils/TableGen/InfoByHwMode.h
rename to llvm/utils/TableGen/Common/InfoByHwMode.h
index 4692ab26db953b..5f532958414888 100644
--- a/llvm/utils/TableGen/InfoByHwMode.h
+++ b/llvm/utils/TableGen/Common/InfoByHwMode.h
@@ -40,8 +40,7 @@ enum : unsigned {
};
template <typename InfoT>
-void union_modes(const InfoByHwMode<InfoT> &A,
- const InfoByHwMode<InfoT> &B,
+void union_modes(const InfoByHwMode<InfoT> &A, const InfoByHwMode<InfoT> &B,
SmallVectorImpl<unsigned> &Modes) {
auto AI = A.begin();
auto BI = B.begin();
@@ -85,9 +84,8 @@ void union_modes(const InfoByHwMode<InfoT> &A,
Modes.push_back(DefaultMode);
}
-template <typename InfoT>
-struct InfoByHwMode {
- typedef std::map<unsigned,InfoT> MapType;
+template <typename InfoT> struct InfoByHwMode {
+ typedef std::map<unsigned, InfoT> MapType;
typedef typename MapType::value_type PairType;
typedef typename MapType::iterator iterator;
typedef typename MapType::const_iterator const_iterator;
@@ -98,11 +96,11 @@ struct InfoByHwMode {
LLVM_ATTRIBUTE_ALWAYS_INLINE
iterator begin() { return Map.begin(); }
LLVM_ATTRIBUTE_ALWAYS_INLINE
- iterator end() { return Map.end(); }
+ iterator end() { return Map.end(); }
LLVM_ATTRIBUTE_ALWAYS_INLINE
const_iterator begin() const { return Map.begin(); }
LLVM_ATTRIBUTE_ALWAYS_INLINE
- const_iterator end() const { return Map.end(); }
+ const_iterator end() const { return Map.end(); }
LLVM_ATTRIBUTE_ALWAYS_INLINE
bool empty() const { return Map.empty(); }
@@ -156,15 +154,13 @@ struct InfoByHwMode {
struct ValueTypeByHwMode : public InfoByHwMode<MVT> {
ValueTypeByHwMode(Record *R, const CodeGenHwModes &CGH);
ValueTypeByHwMode(Record *R, MVT T);
- ValueTypeByHwMode(MVT T) { Map.insert({DefaultMode,T}); }
+ ValueTypeByHwMode(MVT T) { Map.insert({DefaultMode, T}); }
ValueTypeByHwMode() = default;
- bool operator== (const ValueTypeByHwMode &T) const;
- bool operator< (const ValueTypeByHwMode &T) const;
+ bool operator==(const ValueTypeByHwMode &T) const;
+ bool operator<(const ValueTypeByHwMode &T) const;
- bool isValid() const {
- return !Map.empty();
- }
+ bool isValid() const { return !Map.empty(); }
MVT getType(unsigned Mode) const { return get(Mode); }
MVT &getOrCreateTypeForMode(unsigned Mode, MVT Type);
@@ -178,8 +174,7 @@ struct ValueTypeByHwMode : public InfoByHwMode<MVT> {
}
};
-ValueTypeByHwMode getValueTypeByHwMode(Record *Rec,
- const CodeGenHwModes &CGH);
+ValueTypeByHwMode getValueTypeByHwMode(Record *Rec, const CodeGenHwModes &CGH);
struct RegSizeInfo {
unsigned RegSize;
@@ -188,14 +183,12 @@ struct RegSizeInfo {
RegSizeInfo(Record *R, const CodeGenHwModes &CGH);
RegSizeInfo() = default;
- bool operator< (const RegSizeInfo &I) const;
- bool operator== (const RegSizeInfo &I) const {
+ bool operator<(const RegSizeInfo &I) const;
+ bool operator==(const RegSizeInfo &I) const {
return std::tie(RegSize, SpillSize, SpillAlignment) ==
std::tie(I.RegSize, I.SpillSize, I.SpillAlignment);
}
- bool operator!= (const RegSizeInfo &I) const {
- return !(*this == I);
- }
+ bool operator!=(const RegSizeInfo &I) const { return !(*this == I); }
bool isSubClassOf(const RegSizeInfo &I) const;
void writeToStream(raw_ostream &OS) const;
@@ -204,9 +197,9 @@ struct RegSizeInfo {
struct RegSizeInfoByHwMode : public InfoByHwMode<RegSizeInfo> {
RegSizeInfoByHwMode(Record *R, const CodeGenHwModes &CGH);
RegSizeInfoByHwMode() = default;
- bool operator< (const RegSizeInfoByHwMode &VI) const;
- bool operator== (const RegSizeInfoByHwMode &VI) const;
- bool operator!= (const RegSizeInfoByHwMode &VI) const {
+ bool operator<(const RegSizeInfoByHwMode &VI) const;
+ bool operator==(const RegSizeInfoByHwMode &VI) const;
+ bool operator!=(const RegSizeInfoByHwMode &VI) const {
return !(*this == VI);
}
@@ -224,7 +217,7 @@ raw_ostream &operator<<(raw_ostream &OS, const ValueTypeByHwMode &T);
raw_ostream &operator<<(raw_ostream &OS, const RegSizeInfo &T);
raw_ostream &operator<<(raw_ostream &OS, const RegSizeInfoByHwMode &T);
-struct EncodingInfoByHwMode : public InfoByHwMode<Record*> {
+struct EncodingInfoByHwMode : public InfoByHwMode<Record *> {
EncodingInfoByHwMode(Record *R, const CodeGenHwModes &CGH);
EncodingInfoByHwMode() = default;
};
diff --git a/llvm/utils/TableGen/OptEmitter.cpp b/llvm/utils/TableGen/Common/OptEmitter.cpp
similarity index 100%
rename from llvm/utils/TableGen/OptEmitter.cpp
rename to llvm/utils/TableGen/Common/OptEmitter.cpp
diff --git a/llvm/utils/TableGen/OptEmitter.h b/llvm/utils/TableGen/Common/OptEmitter.h
similarity index 100%
rename from llvm/utils/TableGen/OptEmitter.h
rename to llvm/utils/TableGen/Common/OptEmitter.h
diff --git a/llvm/utils/TableGen/PredicateExpander.cpp b/llvm/utils/TableGen/Common/PredicateExpander.cpp
similarity index 99%
rename from llvm/utils/TableGen/PredicateExpander.cpp
rename to llvm/utils/TableGen/Common/PredicateExpander.cpp
index 0b9b6389fe3817..d0a35ff82df649 100644
--- a/llvm/utils/TableGen/PredicateExpander.cpp
+++ b/llvm/utils/TableGen/Common/PredicateExpander.cpp
@@ -101,7 +101,6 @@ void PredicateExpander::expandCheckRegOperand(raw_ostream &OS, int OpIndex,
OS << Reg->getName();
}
-
void PredicateExpander::expandCheckRegOperandSimple(raw_ostream &OS,
int OpIndex,
StringRef FunctionMapper) {
@@ -487,7 +486,8 @@ void STIPredicateExpander::expandPrologue(raw_ostream &OS,
OS << "unsigned ProcessorID = getSchedModel().getProcessorID();\n";
}
-void STIPredicateExpander::expandOpcodeGroup(raw_ostream &OS, const OpcodeGroup &Group,
+void STIPredicateExpander::expandOpcodeGroup(raw_ostream &OS,
+ const OpcodeGroup &Group,
bool ShouldUpdateOpcodeMask) {
const OpcodeInfo &OI = Group.getOpcodeInfo();
for (const PredicateInfo &PI : OI.getPredicates()) {
diff --git a/llvm/utils/TableGen/PredicateExpander.h b/llvm/utils/TableGen/Common/PredicateExpander.h
similarity index 100%
rename from llvm/utils/TableGen/PredicateExpander.h
rename to llvm/utils/TableGen/Common/PredicateExpander.h
diff --git a/llvm/utils/TableGen/SubtargetFeatureInfo.cpp b/llvm/utils/TableGen/Common/SubtargetFeatureInfo.cpp
similarity index 99%
rename from llvm/utils/TableGen/SubtargetFeatureInfo.cpp
rename to llvm/utils/TableGen/Common/SubtargetFeatureInfo.cpp
index 52afb4d8916279..819abfa965a58c 100644
--- a/llvm/utils/TableGen/SubtargetFeatureInfo.cpp
+++ b/llvm/utils/TableGen/Common/SubtargetFeatureInfo.cpp
@@ -81,7 +81,7 @@ void SubtargetFeatureInfo::emitNameTable(
uint64_t IndexUB = 0;
for (const auto &SF : SubtargetFeatures)
if (IndexUB <= SF.second.Index)
- IndexUB = SF.second.Index+1;
+ IndexUB = SF.second.Index + 1;
std::vector<std::string> Names;
if (IndexUB > 0)
diff --git a/llvm/utils/TableGen/SubtargetFeatureInfo.h b/llvm/utils/TableGen/Common/SubtargetFeatureInfo.h
similarity index 97%
rename from llvm/utils/TableGen/SubtargetFeatureInfo.h
rename to llvm/utils/TableGen/Common/SubtargetFeatureInfo.h
index 9401004484350a..b1016ff24e88a3 100644
--- a/llvm/utils/TableGen/SubtargetFeatureInfo.h
+++ b/llvm/utils/TableGen/Common/SubtargetFeatureInfo.h
@@ -18,7 +18,8 @@
namespace llvm {
struct SubtargetFeatureInfo;
-using SubtargetFeatureInfoMap = std::map<Record *, SubtargetFeatureInfo, LessRecordByID>;
+using SubtargetFeatureInfoMap =
+ std::map<Record *, SubtargetFeatureInfo, LessRecordByID>;
/// Helper class for storing information on a subtarget feature which
/// participates in instruction matching.
diff --git a/llvm/utils/TableGen/Types.cpp b/llvm/utils/TableGen/Common/Types.cpp
similarity index 90%
rename from llvm/utils/TableGen/Types.cpp
rename to llvm/utils/TableGen/Common/Types.cpp
index aca8e36b683db1..35b79b320dc328 100644
--- a/llvm/utils/TableGen/Types.cpp
+++ b/llvm/utils/TableGen/Common/Types.cpp
@@ -15,7 +15,9 @@
using namespace llvm;
-const char *llvm::getMinimalTypeForRange(uint64_t Range, unsigned MaxSize LLVM_ATTRIBUTE_UNUSED) {
+const char *
+llvm::getMinimalTypeForRange(uint64_t Range,
+ unsigned MaxSize LLVM_ATTRIBUTE_UNUSED) {
// TODO: The original callers only used 32 and 64 so these are the only
// values permitted. Rather than widen the supported values we should
// allow 64 for the callers that currently use 32 and remove the
diff --git a/llvm/utils/TableGen/Types.h b/llvm/utils/TableGen/Common/Types.h
similarity index 97%
rename from llvm/utils/TableGen/Types.h
rename to llvm/utils/TableGen/Common/Types.h
index f369d61785c4ba..74f0f9f2792c41 100644
--- a/llvm/utils/TableGen/Types.h
+++ b/llvm/utils/TableGen/Common/Types.h
@@ -16,6 +16,6 @@ namespace llvm {
/// MaxSize indicates the largest size of integer to consider (in bits) and only
/// supports values of at least 32.
const char *getMinimalTypeForRange(uint64_t Range, unsigned MaxSize = 64);
-}
+} // namespace llvm
#endif
diff --git a/llvm/utils/TableGen/VarLenCodeEmitterGen.cpp b/llvm/utils/TableGen/Common/VarLenCodeEmitterGen.cpp
similarity index 100%
rename from llvm/utils/TableGen/VarLenCodeEmitterGen.cpp
rename to llvm/utils/TableGen/Common/VarLenCodeEmitterGen.cpp
diff --git a/llvm/utils/TableGen/VarLenCodeEmitterGen.h b/llvm/utils/TableGen/Common/VarLenCodeEmitterGen.h
similarity index 100%
rename from llvm/utils/TableGen/VarLenCodeEmitterGen.h
rename to llvm/utils/TableGen/Common/VarLenCodeEmitterGen.h
diff --git a/llvm/utils/TableGen/CompressInstEmitter.cpp b/llvm/utils/TableGen/CompressInstEmitter.cpp
index f703fff0ef3e89..fcf77934faacfd 100644
--- a/llvm/utils/TableGen/CompressInstEmitter.cpp
+++ b/llvm/utils/TableGen/CompressInstEmitter.cpp
@@ -64,9 +64,9 @@
//===----------------------------------------------------------------------===//
-#include "CodeGenInstruction.h"
-#include "CodeGenRegisters.h"
-#include "CodeGenTarget.h"
+#include "Common/CodeGenInstruction.h"
+#include "Common/CodeGenRegisters.h"
+#include "Common/CodeGenTarget.h"
#include "llvm/ADT/IndexedMap.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringMap.h"
diff --git a/llvm/utils/TableGen/DAGISelEmitter.cpp b/llvm/utils/TableGen/DAGISelEmitter.cpp
index eaf7f7f9f0a3ac..c29c15c725d90d 100644
--- a/llvm/utils/TableGen/DAGISelEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelEmitter.cpp
@@ -10,10 +10,10 @@
//
//===----------------------------------------------------------------------===//
-#include "CodeGenDAGPatterns.h"
-#include "CodeGenInstruction.h"
-#include "CodeGenTarget.h"
-#include "DAGISelMatcher.h"
+#include "Common/CodeGenDAGPatterns.h"
+#include "Common/CodeGenInstruction.h"
+#include "Common/CodeGenTarget.h"
+#include "Common/DAGISelMatcher.h"
#include "llvm/Support/Debug.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
diff --git a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
index 50156d34528c15..f8b8875fa81f40 100644
--- a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
@@ -10,12 +10,12 @@
//
//===----------------------------------------------------------------------===//
-#include "CodeGenDAGPatterns.h"
-#include "CodeGenInstruction.h"
-#include "CodeGenRegisters.h"
-#include "CodeGenTarget.h"
-#include "DAGISelMatcher.h"
-#include "SDNodeProperties.h"
+#include "Basic/SDNodeProperties.h"
+#include "Common/CodeGenDAGPatterns.h"
+#include "Common/CodeGenInstruction.h"
+#include "Common/CodeGenRegisters.h"
+#include "Common/CodeGenTarget.h"
+#include "Common/DAGISelMatcher.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/MapVector.h"
#include "llvm/ADT/StringMap.h"
diff --git a/llvm/utils/TableGen/DAGISelMatcherGen.cpp b/llvm/utils/TableGen/DAGISelMatcherGen.cpp
index 3526e97c8e08e8..f07c4d90916c36 100644
--- a/llvm/utils/TableGen/DAGISelMatcherGen.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherGen.cpp
@@ -6,13 +6,13 @@
//
//===----------------------------------------------------------------------===//
-#include "CodeGenDAGPatterns.h"
-#include "CodeGenInstruction.h"
-#include "CodeGenRegisters.h"
-#include "CodeGenTarget.h"
-#include "DAGISelMatcher.h"
-#include "InfoByHwMode.h"
-#include "SDNodeProperties.h"
+#include "Basic/SDNodeProperties.h"
+#include "Common/CodeGenDAGPatterns.h"
+#include "Common/CodeGenInstruction.h"
+#include "Common/CodeGenRegisters.h"
+#include "Common/CodeGenTarget.h"
+#include "Common/DAGISelMatcher.h"
+#include "Common/InfoByHwMode.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringMap.h"
#include "llvm/TableGen/Error.h"
diff --git a/llvm/utils/TableGen/DAGISelMatcherOpt.cpp b/llvm/utils/TableGen/DAGISelMatcherOpt.cpp
index c4c25dc1a5fdef..c7bbd83b3a3d51 100644
--- a/llvm/utils/TableGen/DAGISelMatcherOpt.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherOpt.cpp
@@ -10,9 +10,9 @@
//
//===----------------------------------------------------------------------===//
-#include "CodeGenDAGPatterns.h"
-#include "DAGISelMatcher.h"
-#include "SDNodeProperties.h"
+#include "Basic/SDNodeProperties.h"
+#include "Common/CodeGenDAGPatterns.h"
+#include "Common/DAGISelMatcher.h"
#include "llvm/ADT/StringSet.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
diff --git a/llvm/utils/TableGen/DFAEmitter.cpp b/llvm/utils/TableGen/DFAEmitter.cpp
index 54ad81cbebe81d..2f0fcb6c6124f1 100644
--- a/llvm/utils/TableGen/DFAEmitter.cpp
+++ b/llvm/utils/TableGen/DFAEmitter.cpp
@@ -21,7 +21,7 @@
//===----------------------------------------------------------------------===//
#include "DFAEmitter.h"
-#include "SequenceToOffsetTable.h"
+#include "Basic/SequenceToOffsetTable.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/UniqueVector.h"
diff --git a/llvm/utils/TableGen/DFAPacketizerEmitter.cpp b/llvm/utils/TableGen/DFAPacketizerEmitter.cpp
index 64c7884616a57f..7a8a7b6e07caef 100644
--- a/llvm/utils/TableGen/DFAPacketizerEmitter.cpp
+++ b/llvm/utils/TableGen/DFAPacketizerEmitter.cpp
@@ -14,8 +14,8 @@
//
//===----------------------------------------------------------------------===//
-#include "CodeGenSchedule.h"
-#include "CodeGenTarget.h"
+#include "Common/CodeGenSchedule.h"
+#include "Common/CodeGenTarget.h"
#include "DFAEmitter.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/Support/Debug.h"
diff --git a/llvm/utils/TableGen/DXILEmitter.cpp b/llvm/utils/TableGen/DXILEmitter.cpp
index 475a57a0cadf86..3f2a1ea292cedf 100644
--- a/llvm/utils/TableGen/DXILEmitter.cpp
+++ b/llvm/utils/TableGen/DXILEmitter.cpp
@@ -11,7 +11,7 @@
//
//===----------------------------------------------------------------------===//
-#include "SequenceToOffsetTable.h"
+#include "Basic/SequenceToOffsetTable.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringSet.h"
diff --git a/llvm/utils/TableGen/DecoderEmitter.cpp b/llvm/utils/TableGen/DecoderEmitter.cpp
index 591ee5c728874b..c604fb42584a32 100644
--- a/llvm/utils/TableGen/DecoderEmitter.cpp
+++ b/llvm/utils/TableGen/DecoderEmitter.cpp
@@ -11,12 +11,12 @@
//
//===----------------------------------------------------------------------===//
-#include "CodeGenHwModes.h"
-#include "CodeGenInstruction.h"
-#include "CodeGenTarget.h"
-#include "InfoByHwMode.h"
+#include "Common/CodeGenHwModes.h"
+#include "Common/CodeGenInstruction.h"
+#include "Common/CodeGenTarget.h"
+#include "Common/InfoByHwMode.h"
+#include "Common/VarLenCodeEmitterGen.h"
#include "TableGenBackends.h"
-#include "VarLenCodeEmitterGen.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/CachedHashString.h"
diff --git a/llvm/utils/TableGen/DisassemblerEmitter.cpp b/llvm/utils/TableGen/DisassemblerEmitter.cpp
index 92f3721507e5b7..0d786690e842c8 100644
--- a/llvm/utils/TableGen/DisassemblerEmitter.cpp
+++ b/llvm/utils/TableGen/DisassemblerEmitter.cpp
@@ -6,7 +6,7 @@
//
//===----------------------------------------------------------------------===//
-#include "CodeGenTarget.h"
+#include "Common/CodeGenTarget.h"
#include "TableGenBackends.h"
#include "WebAssemblyDisassemblerEmitter.h"
#include "X86DisassemblerTables.h"
diff --git a/llvm/utils/TableGen/FastISelEmitter.cpp b/llvm/utils/TableGen/FastISelEmitter.cpp
index b773a6b91ee2e9..15f0e7c7263ce7 100644
--- a/llvm/utils/TableGen/FastISelEmitter.cpp
+++ b/llvm/utils/TableGen/FastISelEmitter.cpp
@@ -16,11 +16,11 @@
//
//===----------------------------------------------------------------------===//
-#include "CodeGenDAGPatterns.h"
-#include "CodeGenInstruction.h"
-#include "CodeGenRegisters.h"
-#include "CodeGenTarget.h"
-#include "InfoByHwMode.h"
+#include "Common/CodeGenDAGPatterns.h"
+#include "Common/CodeGenInstruction.h"
+#include "Common/CodeGenRegisters.h"
+#include "Common/CodeGenTarget.h"
+#include "Common/InfoByHwMode.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/TableGen/Error.h"
diff --git a/llvm/utils/TableGen/GlobalISel/CMakeLists.txt b/llvm/utils/TableGen/GlobalISel/CMakeLists.txt
deleted file mode 100644
index 7262c405839934..00000000000000
--- a/llvm/utils/TableGen/GlobalISel/CMakeLists.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-set(LLVM_LINK_COMPONENTS
- Support
- TableGen
- )
-
-add_llvm_library(LLVMTableGenGlobalISel STATIC DISABLE_LLVM_LINK_LLVM_DYLIB
- CodeExpander.cpp
- CXXPredicates.cpp
- MatchDataInfo.cpp
- Patterns.cpp
-
- DEPENDS
- vt_gen
- )
-
-# Users may include its headers as "GlobalISel/*.h"
-target_include_directories(LLVMTableGenGlobalISel
- INTERFACE
- $<BUILD_INTERFACE:${CMAKE_CURRENT_SOURCE_DIR}/..>
- )
diff --git a/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp b/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
index d9249cf627f21e..6aedcbca67ab29 100644
--- a/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
@@ -26,18 +26,18 @@
///
//===----------------------------------------------------------------------===//
-#include "CodeGenInstruction.h"
-#include "CodeGenIntrinsics.h"
-#include "CodeGenTarget.h"
-#include "GlobalISel/CXXPredicates.h"
-#include "GlobalISel/CodeExpander.h"
-#include "GlobalISel/CodeExpansions.h"
-#include "GlobalISel/CombinerUtils.h"
-#include "GlobalISel/MatchDataInfo.h"
-#include "GlobalISel/Patterns.h"
-#include "GlobalISelMatchTable.h"
-#include "GlobalISelMatchTableExecutorEmitter.h"
-#include "SubtargetFeatureInfo.h"
+#include "Basic/CodeGenIntrinsics.h"
+#include "Common/CodeGenInstruction.h"
+#include "Common/CodeGenTarget.h"
+#include "Common/GlobalISel/CXXPredicates.h"
+#include "Common/GlobalISel/CodeExpander.h"
+#include "Common/GlobalISel/CodeExpansions.h"
+#include "Common/GlobalISel/CombinerUtils.h"
+#include "Common/GlobalISel/GlobalISelMatchTable.h"
+#include "Common/GlobalISel/GlobalISelMatchTableExecutorEmitter.h"
+#include "Common/GlobalISel/MatchDataInfo.h"
+#include "Common/GlobalISel/Patterns.h"
+#include "Common/SubtargetFeatureInfo.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/EquivalenceClasses.h"
#include "llvm/ADT/Hashing.h"
diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp
index 22e7785275bd70..e284e4a8d03b55 100644
--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -29,15 +29,15 @@
///
//===----------------------------------------------------------------------===//
-#include "CodeGenDAGPatterns.h"
-#include "CodeGenInstruction.h"
-#include "CodeGenIntrinsics.h"
-#include "CodeGenRegisters.h"
-#include "CodeGenTarget.h"
-#include "GlobalISelMatchTable.h"
-#include "GlobalISelMatchTableExecutorEmitter.h"
-#include "InfoByHwMode.h"
-#include "SubtargetFeatureInfo.h"
+#include "Basic/CodeGenIntrinsics.h"
+#include "Common/CodeGenDAGPatterns.h"
+#include "Common/CodeGenInstruction.h"
+#include "Common/CodeGenRegisters.h"
+#include "Common/CodeGenTarget.h"
+#include "Common/GlobalISel/GlobalISelMatchTable.h"
+#include "Common/GlobalISel/GlobalISelMatchTableExecutorEmitter.h"
+#include "Common/InfoByHwMode.h"
+#include "Common/SubtargetFeatureInfo.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGenTypes/LowLevelType.h"
#include "llvm/CodeGenTypes/MachineValueType.h"
diff --git a/llvm/utils/TableGen/InstrDocsEmitter.cpp b/llvm/utils/TableGen/InstrDocsEmitter.cpp
index 616e7b589288a2..e8f69ad03253c4 100644
--- a/llvm/utils/TableGen/InstrDocsEmitter.cpp
+++ b/llvm/utils/TableGen/InstrDocsEmitter.cpp
@@ -18,9 +18,9 @@
//
//===----------------------------------------------------------------------===//
-#include "CodeGenDAGPatterns.h"
-#include "CodeGenInstruction.h"
-#include "CodeGenTarget.h"
+#include "Common/CodeGenDAGPatterns.h"
+#include "Common/CodeGenInstruction.h"
+#include "Common/CodeGenTarget.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
#include <string>
diff --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp
index b2250c0cf9897c..0813b7a89c0534 100644
--- a/llvm/utils/TableGen/InstrInfoEmitter.cpp
+++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp
@@ -11,15 +11,15 @@
//
//===----------------------------------------------------------------------===//
-#include "CodeGenDAGPatterns.h"
-#include "CodeGenInstruction.h"
-#include "CodeGenSchedule.h"
-#include "CodeGenTarget.h"
-#include "PredicateExpander.h"
-#include "SequenceToOffsetTable.h"
-#include "SubtargetFeatureInfo.h"
+#include "Basic/SequenceToOffsetTable.h"
+#include "Common/CodeGenDAGPatterns.h"
+#include "Common/CodeGenInstruction.h"
+#include "Common/CodeGenSchedule.h"
+#include "Common/CodeGenTarget.h"
+#include "Common/PredicateExpander.h"
+#include "Common/SubtargetFeatureInfo.h"
+#include "Common/Types.h"
#include "TableGenBackends.h"
-#include "Types.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
diff --git a/llvm/utils/TableGen/IntrinsicEmitter.cpp b/llvm/utils/TableGen/IntrinsicEmitter.cpp
index 28604c5600bf4e..0c7e49dc9ae454 100644
--- a/llvm/utils/TableGen/IntrinsicEmitter.cpp
+++ b/llvm/utils/TableGen/IntrinsicEmitter.cpp
@@ -10,8 +10,8 @@
//
//===----------------------------------------------------------------------===//
-#include "CodeGenIntrinsics.h"
-#include "SequenceToOffsetTable.h"
+#include "Basic/CodeGenIntrinsics.h"
+#include "Basic/SequenceToOffsetTable.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringExtras.h"
diff --git a/llvm/utils/TableGen/MacroFusionPredicatorEmitter.cpp b/llvm/utils/TableGen/MacroFusionPredicatorEmitter.cpp
index 78dcd4471ae747..eb18599eebaff4 100644
--- a/llvm/utils/TableGen/MacroFusionPredicatorEmitter.cpp
+++ b/llvm/utils/TableGen/MacroFusionPredicatorEmitter.cpp
@@ -38,8 +38,8 @@
//
//===---------------------------------------------------------------------===//
-#include "CodeGenTarget.h"
-#include "PredicateExpander.h"
+#include "Common/CodeGenTarget.h"
+#include "Common/PredicateExpander.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/Support/Debug.h"
#include "llvm/TableGen/Error.h"
diff --git a/llvm/utils/TableGen/OptParserEmitter.cpp b/llvm/utils/TableGen/OptParserEmitter.cpp
index 257cd44d9e8045..5a9dc257bb3372 100644
--- a/llvm/utils/TableGen/OptParserEmitter.cpp
+++ b/llvm/utils/TableGen/OptParserEmitter.cpp
@@ -6,7 +6,7 @@
//
//===----------------------------------------------------------------------===//
-#include "OptEmitter.h"
+#include "Common/OptEmitter.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallString.h"
#include "llvm/ADT/Twine.h"
diff --git a/llvm/utils/TableGen/OptRSTEmitter.cpp b/llvm/utils/TableGen/OptRSTEmitter.cpp
index 5a7f079dc1681c..75b7cbdf298879 100644
--- a/llvm/utils/TableGen/OptRSTEmitter.cpp
+++ b/llvm/utils/TableGen/OptRSTEmitter.cpp
@@ -6,7 +6,7 @@
//
//===----------------------------------------------------------------------===//
-#include "OptEmitter.h"
+#include "Common/OptEmitter.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/StringMap.h"
#include "llvm/TableGen/Record.h"
diff --git a/llvm/utils/TableGen/PseudoLoweringEmitter.cpp b/llvm/utils/TableGen/PseudoLoweringEmitter.cpp
index e07fb91880980c..52cc365125eb5e 100644
--- a/llvm/utils/TableGen/PseudoLoweringEmitter.cpp
+++ b/llvm/utils/TableGen/PseudoLoweringEmitter.cpp
@@ -6,8 +6,8 @@
//
//===----------------------------------------------------------------------===//
-#include "CodeGenInstruction.h"
-#include "CodeGenTarget.h"
+#include "Common/CodeGenInstruction.h"
+#include "Common/CodeGenTarget.h"
#include "llvm/ADT/IndexedMap.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringMap.h"
diff --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp
index f851d9a79870b4..6e9080b8f4a974 100644
--- a/llvm/utils/TableGen/RegisterBankEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp
@@ -11,9 +11,9 @@
//
//===----------------------------------------------------------------------===//
-#include "CodeGenRegisters.h"
-#include "CodeGenTarget.h"
-#include "InfoByHwMode.h"
+#include "Common/CodeGenRegisters.h"
+#include "Common/CodeGenTarget.h"
+#include "Common/InfoByHwMode.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/Support/Debug.h"
#include "llvm/TableGen/Error.h"
diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index cff97771b7a87b..4df45109efd3de 100644
--- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -12,12 +12,12 @@
//
//===----------------------------------------------------------------------===//
-#include "CodeGenHwModes.h"
-#include "CodeGenRegisters.h"
-#include "CodeGenTarget.h"
-#include "InfoByHwMode.h"
-#include "SequenceToOffsetTable.h"
-#include "Types.h"
+#include "Basic/SequenceToOffsetTable.h"
+#include "Common/CodeGenHwModes.h"
+#include "Common/CodeGenRegisters.h"
+#include "Common/CodeGenTarget.h"
+#include "Common/InfoByHwMode.h"
+#include "Common/Types.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
diff --git a/llvm/utils/TableGen/SearchableTableEmitter.cpp b/llvm/utils/TableGen/SearchableTableEmitter.cpp
index 9987d1ec73d9f4..59114d599b474f 100644
--- a/llvm/utils/TableGen/SearchableTableEmitter.cpp
+++ b/llvm/utils/TableGen/SearchableTableEmitter.cpp
@@ -12,7 +12,7 @@
//
//===----------------------------------------------------------------------===//
-#include "CodeGenIntrinsics.h"
+#include "Basic/CodeGenIntrinsics.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/STLExtras.h"
@@ -131,7 +131,7 @@ class SearchableTableEmitter {
Twine("Entry for field '") + Field.Name + "' is null");
return std::string(Entry->first);
}
- PrintFatalError(Loc, Twine("invalid field type for field '") + Field.Name +
+ PrintFatalError(Loc, Twine("invalid field type for field '") + Field.Name +
"'; expected: bit, bits, string, or code");
}
@@ -170,7 +170,7 @@ class SearchableTableEmitter {
return "uint32_t";
if (NumBits <= 64)
return "uint64_t";
- PrintFatalError(Index.Loc, Twine("In table '") + Table.Name +
+ PrintFatalError(Index.Loc, Twine("In table '") + Table.Name +
"' lookup method '" + Index.Name +
"', key field '" + Field.Name +
"' of type bits is too large");
@@ -406,7 +406,7 @@ void SearchableTableEmitter::emitLookupFunction(const GenericTable &Table,
OS << " struct KeyType {\n";
for (const auto &Field : Index.Fields) {
- OS << " " << searchableFieldType(Table, Index, Field, TypeInTempStruct)
+ OS << " " << searchableFieldType(Table, Index, Field, TypeInTempStruct)
<< " " << Field.Name << ";\n";
}
OS << " };\n";
@@ -417,7 +417,7 @@ void SearchableTableEmitter::emitLookupFunction(const GenericTable &Table,
if (isa<StringRecTy>(Field.RecType)) {
OS << ".upper()";
if (IsPrimary)
- PrintFatalError(Index.Loc,
+ PrintFatalError(Index.Loc,
Twine("In table '") + Table.Name +
"', use a secondary lookup method for "
"case-insensitive comparison of field '" +
@@ -561,7 +561,7 @@ std::unique_ptr<SearchIndex> SearchableTableEmitter::parseSearchIndex(
Twine("In table '") + Table.Name +
"', 'PrimaryKey' or 'Key' refers to nonexistent field '" +
FieldName + "'");
-
+
Index->Fields.push_back(*Field);
}
@@ -624,11 +624,11 @@ void SearchableTableEmitter::collectTableEntries(
} else {
RecTy *Ty = resolveTypes(Field.RecType, TI->getType());
if (!Ty)
- PrintFatalError(EntryRec->getValue(Field.Name),
+ PrintFatalError(EntryRec->getValue(Field.Name),
Twine("Field '") + Field.Name + "' of table '" +
- Table.Name + "' entry has incompatible type: " +
- TI->getType()->getAsString() + " vs. " +
- Field.RecType->getAsString());
+ Table.Name + "' entry has incompatible type: " +
+ TI->getType()->getAsString() + " vs. " +
+ Field.RecType->getAsString());
Field.RecType = Ty;
}
}
@@ -681,7 +681,7 @@ void SearchableTableEmitter::run(raw_ostream &OS) {
StringRef FilterClass = EnumRec->getValueAsString("FilterClass");
Enum->Class = Records.getClass(FilterClass);
if (!Enum->Class)
- PrintFatalError(EnumRec->getValue("FilterClass"),
+ PrintFatalError(EnumRec->getValue("FilterClass"),
Twine("Enum FilterClass '") + FilterClass +
"' does not exist");
@@ -704,9 +704,9 @@ void SearchableTableEmitter::run(raw_ostream &OS) {
if (auto TypeOfRecordVal = TableRec->getValue(("TypeOf_" + FieldName).str())) {
if (!parseFieldType(Table->Fields.back(), TypeOfRecordVal->getValue())) {
- PrintError(TypeOfRecordVal,
- Twine("Table '") + Table->Name +
- "' has invalid 'TypeOf_" + FieldName +
+ PrintError(TypeOfRecordVal,
+ Twine("Table '") + Table->Name + "' has invalid 'TypeOf_" +
+ FieldName +
"': " + TypeOfRecordVal->getValue()->getAsString());
PrintFatalNote("The 'TypeOf_xxx' field must be a string naming a "
"GenericEnum record, or \"code\"");
@@ -716,9 +716,9 @@ void SearchableTableEmitter::run(raw_ostream &OS) {
StringRef FilterClass = TableRec->getValueAsString("FilterClass");
if (!Records.getClass(FilterClass))
- PrintFatalError(TableRec->getValue("FilterClass"),
- Twine("Table FilterClass '") +
- FilterClass + "' does not exist");
+ PrintFatalError(TableRec->getValue("FilterClass"),
+ Twine("Table FilterClass '") + FilterClass +
+ "' does not exist");
RecordVal *FilterClassFieldVal = TableRec->getValue("FilterClassField");
std::vector<Record *> Definitions =
@@ -758,14 +758,14 @@ void SearchableTableEmitter::run(raw_ostream &OS) {
Record *TableRec = IndexRec->getValueAsDef("Table");
auto It = TableMap.find(TableRec);
if (It == TableMap.end())
- PrintFatalError(IndexRec->getValue("Table"),
+ PrintFatalError(IndexRec->getValue("Table"),
Twine("SearchIndex '") + IndexRec->getName() +
"' refers to nonexistent table '" +
TableRec->getName());
GenericTable &Table = *It->second;
Table.Indices.push_back(
- parseSearchIndex(Table, IndexRec->getValue("Key"), IndexRec->getName(),
+ parseSearchIndex(Table, IndexRec->getValue("Key"), IndexRec->getName(),
IndexRec->getValueAsListOfStrings("Key"),
IndexRec->getValueAsBit("EarlyOut")));
}
diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp b/llvm/utils/TableGen/SubtargetEmitter.cpp
index 39225182a4c255..9c4dac760b8bb2 100644
--- a/llvm/utils/TableGen/SubtargetEmitter.cpp
+++ b/llvm/utils/TableGen/SubtargetEmitter.cpp
@@ -10,10 +10,10 @@
//
//===----------------------------------------------------------------------===//
-#include "CodeGenHwModes.h"
-#include "CodeGenSchedule.h"
-#include "CodeGenTarget.h"
-#include "PredicateExpander.h"
+#include "Common/CodeGenHwModes.h"
+#include "Common/CodeGenSchedule.h"
+#include "Common/CodeGenTarget.h"
+#include "Common/PredicateExpander.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/StringExtras.h"
diff --git a/llvm/utils/TableGen/WebAssemblyDisassemblerEmitter.cpp b/llvm/utils/TableGen/WebAssemblyDisassemblerEmitter.cpp
index dc037e4409ab73..2a0095ffa6a645 100644
--- a/llvm/utils/TableGen/WebAssemblyDisassemblerEmitter.cpp
+++ b/llvm/utils/TableGen/WebAssemblyDisassemblerEmitter.cpp
@@ -14,7 +14,7 @@
//===----------------------------------------------------------------------===//
#include "WebAssemblyDisassemblerEmitter.h"
-#include "CodeGenInstruction.h"
+#include "Common/CodeGenInstruction.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/TableGen/Record.h"
diff --git a/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp b/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp
index fef8dc7236f57c..a3911030ebe6fc 100644
--- a/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp
+++ b/llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp
@@ -11,8 +11,8 @@
///
//===----------------------------------------------------------------------===//
-#include "CodeGenInstruction.h"
-#include "CodeGenTarget.h"
+#include "Common/CodeGenInstruction.h"
+#include "Common/CodeGenTarget.h"
#include "X86RecognizableInstr.h"
#include "llvm/TableGen/Error.h"
#include "llvm/TableGen/Record.h"
diff --git a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
index 44c2817e1b5d68..d9f3f8d15a077b 100644
--- a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
+++ b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp
@@ -11,8 +11,8 @@
//
//===----------------------------------------------------------------------===//
-#include "CodeGenInstruction.h"
-#include "CodeGenTarget.h"
+#include "Common/CodeGenInstruction.h"
+#include "Common/CodeGenTarget.h"
#include "X86RecognizableInstr.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/Support/FormattedStream.h"
diff --git a/llvm/utils/TableGen/X86MnemonicTables.cpp b/llvm/utils/TableGen/X86MnemonicTables.cpp
index aeafee15746235..d9ceed40f7c70d 100644
--- a/llvm/utils/TableGen/X86MnemonicTables.cpp
+++ b/llvm/utils/TableGen/X86MnemonicTables.cpp
@@ -11,8 +11,8 @@
//
//===----------------------------------------------------------------------===//
-#include "CodeGenInstruction.h"
-#include "CodeGenTarget.h"
+#include "Common/CodeGenInstruction.h"
+#include "Common/CodeGenTarget.h"
#include "X86RecognizableInstr.h"
#include "llvm/TableGen/Record.h"
#include "llvm/TableGen/TableGenBackend.h"
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.h b/llvm/utils/TableGen/X86RecognizableInstr.h
index 007c700cdfaf76..b59ab47119d933 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.h
+++ b/llvm/utils/TableGen/X86RecognizableInstr.h
@@ -16,7 +16,7 @@
#ifndef LLVM_UTILS_TABLEGEN_X86RECOGNIZABLEINSTR_H
#define LLVM_UTILS_TABLEGEN_X86RECOGNIZABLEINSTR_H
-#include "CodeGenInstruction.h"
+#include "Common/CodeGenInstruction.h"
#include "llvm/Support/X86DisassemblerDecoderCommon.h"
#include <cstdint>
#include <string>
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