[llvm] [RFC] implement convergence control in MIR using SelectionDAG (PR #71785)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 6 06:52:40 PST 2024
================
@@ -394,6 +394,16 @@ Register FunctionLoweringInfo::CreateRegs(const Value *V) {
!TLI->requiresUniformRegister(*MF, V));
}
+Register FunctionLoweringInfo::InitializeRegForValue(const Value *V) {
+ // Tokens live in vregs only when used for convergence control.
+ if (V->getType()->isTokenTy() && !isa<ConvergenceControlInst>(V))
+ return 0;
+ Register &R = ValueMap[V];
+ assert(R == 0 && "Already initialized this value register!");
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arsenm wrote:
R == Register()
https://github.com/llvm/llvm-project/pull/71785
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