[llvm] [llvm-mca] Account for AcquireAtCycles in llvm-mca (PR #80742)

[Michael Maitland via llvm-commits]

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@@ -37,13 +37,13 @@ vle64.v v1, (a1)
 
 # CHECK:      Iterations:        1
 # CHECK-NEXT: Instructions:      26
-# CHECK-NEXT: Total Cycles:      234
+# CHECK-NEXT: Total Cycles:      211
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michaelmaitland wrote:

I think the changing of the cycles makes sense since AcquireAtCycle != 0 for the SiFive7 scheduler model. You can see this [here](https://github.com/llvm/llvm-project/blob/ca1da36aec963c5504ae7ae2e834b37856c476db/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td#L617) for some of the vector alu operations. llvm-mca thought that the arithmetic/load/store sequencer (VA,VS, or VL) was used for one extra cycle than it should have been since AcquireAtCycle = 1 for those resources.

https://github.com/llvm/llvm-project/pull/80742