[llvm] [llvm-mca] Account for AcquireAtCycles in llvm-mca (PR #80742)
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llvm-commits at lists.llvm.org
Mon Feb 5 13:08:50 PST 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-tools-llvm-mca
Author: Michael Maitland (michaelmaitland)
<details>
<summary>Changes</summary>
In the past, there was a variable named ResourceCycles which modeled how long a resource was consumed. Then a variable named AcquireAtCycles was added and allowed the scheduler to specify how many cycles after "cycle 0" the resource was acquired. It was consumed from that AcquireAtCycle until the cycle ResourceCycles - AcquireAtCycle.
We decided ResourceCycles should be renamed ReleaseAtCycle, and the number of cycles a resource was consumed is ReleaseAtCycle - AcquireAtCycle. This renaming happened globally, but only the scheduler was updated to account for AcquireAtCycle.
This patch accounts for the total number of cycles to be calculated as ReleaseAtCycle - AcquireAtCycle in llvm-mca. This patch renames the class ReleaseAtCycles to NumCyclesUsed since that better describes what that class now models.
---
Patch is 263.91 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/80742.diff
37 Files Affected:
- (modified) llvm/include/llvm/MCA/HWEventListener.h (+1-1)
- (modified) llvm/include/llvm/MCA/HardwareUnits/ResourceManager.h (+1-1)
- (modified) llvm/include/llvm/MCA/HardwareUnits/Scheduler.h (+2-2)
- (modified) llvm/include/llvm/MCA/Support.h (+5-5)
- (modified) llvm/lib/MCA/HardwareUnits/ResourceManager.cpp (+4-4)
- (modified) llvm/lib/MCA/HardwareUnits/Scheduler.cpp (+2-2)
- (modified) llvm/lib/MCA/InstrBuilder.cpp (+2-2)
- (modified) llvm/lib/MCA/Stages/InstructionTables.cpp (+2-2)
- (modified) llvm/lib/MCA/Support.cpp (+5-5)
- (modified) llvm/test/tools/llvm-mca/RISCV/SiFive7/reductions.s (+106-106)
- (modified) llvm/test/tools/llvm-mca/RISCV/SiFive7/strided-load-store.s (+81-81)
- (modified) llvm/test/tools/llvm-mca/RISCV/SiFive7/strided-load-x0.s (+29-29)
- (modified) llvm/test/tools/llvm-mca/RISCV/SiFive7/vector-integer-arithmetic.s (+373-373)
- (modified) llvm/test/tools/llvm-mca/RISCV/different-lmul-instruments.s (+4-4)
- (modified) llvm/test/tools/llvm-mca/RISCV/different-sew-instruments.s (+5-5)
- (modified) llvm/test/tools/llvm-mca/RISCV/disable-im.s (+15-15)
- (modified) llvm/test/tools/llvm-mca/RISCV/fractional-lmul-data.s (+5-5)
- (modified) llvm/test/tools/llvm-mca/RISCV/lmul-instrument-at-start.s (+3-3)
- (modified) llvm/test/tools/llvm-mca/RISCV/lmul-instrument-in-middle.s (+9-9)
- (modified) llvm/test/tools/llvm-mca/RISCV/lmul-instrument-in-region.s (+3-3)
- (modified) llvm/test/tools/llvm-mca/RISCV/lmul-instrument-straddles-region.s (+3-3)
- (modified) llvm/test/tools/llvm-mca/RISCV/multiple-same-lmul-instruments.s (+19-19)
- (modified) llvm/test/tools/llvm-mca/RISCV/multiple-same-sew-instruments.s (+8-8)
- (modified) llvm/test/tools/llvm-mca/RISCV/needs-sew-but-only-lmul.s (+5-5)
- (modified) llvm/test/tools/llvm-mca/RISCV/no-vsetvli-to-start.s (+9-9)
- (modified) llvm/test/tools/llvm-mca/RISCV/sew-instrument-at-start.s (+3-3)
- (modified) llvm/test/tools/llvm-mca/RISCV/sew-instrument-in-middle.s (+5-5)
- (modified) llvm/test/tools/llvm-mca/RISCV/sew-instrument-in-region.s (+3-3)
- (modified) llvm/test/tools/llvm-mca/RISCV/sew-instrument-straddles-region.s (+3-3)
- (modified) llvm/test/tools/llvm-mca/RISCV/vle-vse.s (+205-205)
- (modified) llvm/test/tools/llvm-mca/RISCV/vsetivli-lmul-instrument.s (+4-4)
- (modified) llvm/test/tools/llvm-mca/RISCV/vsetivli-lmul-sew-instrument.s (+5-5)
- (modified) llvm/test/tools/llvm-mca/RISCV/vsetvli-lmul-instrument.s (+4-4)
- (modified) llvm/test/tools/llvm-mca/RISCV/vsetvli-lmul-sew-instrument.s (+5-5)
- (modified) llvm/tools/llvm-mca/Views/BottleneckAnalysis.cpp (+3-3)
- (modified) llvm/tools/llvm-mca/Views/ResourcePressureView.cpp (+2-2)
- (modified) llvm/tools/llvm-mca/Views/ResourcePressureView.h (+1-1)
``````````diff
diff --git a/llvm/include/llvm/MCA/HWEventListener.h b/llvm/include/llvm/MCA/HWEventListener.h
index a27b1f12e6a6e..adcf6e152d298 100644
--- a/llvm/include/llvm/MCA/HWEventListener.h
+++ b/llvm/include/llvm/MCA/HWEventListener.h
@@ -63,7 +63,7 @@ class HWInstructionEvent {
// ResourceRef::second is a bitmask of the referenced sub-unit of the resource.
using ResourceRef = std::pair<uint64_t, uint64_t>;
-using ResourceUse = std::pair<ResourceRef, ReleaseAtCycles>;
+using ResourceUse = std::pair<ResourceRef, NumCyclesUsed>;
class HWInstructionIssuedEvent : public HWInstructionEvent {
public:
diff --git a/llvm/include/llvm/MCA/HardwareUnits/ResourceManager.h b/llvm/include/llvm/MCA/HardwareUnits/ResourceManager.h
index 0e3f16d2a490b..6947b9f6ff2fd 100644
--- a/llvm/include/llvm/MCA/HardwareUnits/ResourceManager.h
+++ b/llvm/include/llvm/MCA/HardwareUnits/ResourceManager.h
@@ -430,7 +430,7 @@ class ResourceManager {
void issueInstruction(
const InstrDesc &Desc,
- SmallVectorImpl<std::pair<ResourceRef, ReleaseAtCycles>> &Pipes);
+ SmallVectorImpl<std::pair<ResourceRef, NumCyclesUsed>> &Pipes);
void cycleEvent(SmallVectorImpl<ResourceRef> &ResourcesFreed);
diff --git a/llvm/include/llvm/MCA/HardwareUnits/Scheduler.h b/llvm/include/llvm/MCA/HardwareUnits/Scheduler.h
index 272f6b197868b..3acf142fae1ab 100644
--- a/llvm/include/llvm/MCA/HardwareUnits/Scheduler.h
+++ b/llvm/include/llvm/MCA/HardwareUnits/Scheduler.h
@@ -136,7 +136,7 @@ class Scheduler : public HardwareUnit {
/// Issue an instruction without updating the ready queue.
void issueInstructionImpl(
InstRef &IR,
- SmallVectorImpl<std::pair<ResourceRef, ReleaseAtCycles>> &Pipes);
+ SmallVectorImpl<std::pair<ResourceRef, NumCyclesUsed>> &Pipes);
// Identify instructions that have finished executing, and remove them from
// the IssuedSet. References to executed instructions are added to input
@@ -202,7 +202,7 @@ class Scheduler : public HardwareUnit {
/// result of this event.
void issueInstruction(
InstRef &IR,
- SmallVectorImpl<std::pair<ResourceRef, ReleaseAtCycles>> &Used,
+ SmallVectorImpl<std::pair<ResourceRef, NumCyclesUsed>> &Used,
SmallVectorImpl<InstRef> &Pending,
SmallVectorImpl<InstRef> &Ready);
diff --git a/llvm/include/llvm/MCA/Support.h b/llvm/include/llvm/MCA/Support.h
index e3c155435e234..d93043f673b46 100644
--- a/llvm/include/llvm/MCA/Support.h
+++ b/llvm/include/llvm/MCA/Support.h
@@ -48,12 +48,12 @@ template <typename T> char InstructionError<T>::ID;
/// number of resources, are kept separate. This is used by the
/// ResourcePressureView to calculate the average resource cycles
/// per instruction/iteration.
-class ReleaseAtCycles {
+class NumCyclesUsed {
unsigned Numerator, Denominator;
public:
- ReleaseAtCycles() : Numerator(0), Denominator(1) {}
- ReleaseAtCycles(unsigned Cycles, unsigned ResourceUnits = 1)
+ NumCyclesUsed() : Numerator(0), Denominator(1) {}
+ NumCyclesUsed(unsigned Cycles, unsigned ResourceUnits = 1)
: Numerator(Cycles), Denominator(ResourceUnits) {}
operator double() const {
@@ -67,7 +67,7 @@ class ReleaseAtCycles {
// Add the components of RHS to this instance. Instead of calculating
// the final value here, we keep track of the numerator and denominator
// separately, to reduce floating point error.
- ReleaseAtCycles &operator+=(const ReleaseAtCycles &RHS);
+ NumCyclesUsed &operator+=(const NumCyclesUsed &RHS);
};
/// Populates vector Masks with processor resource masks.
@@ -105,7 +105,7 @@ inline unsigned getResourceStateIndex(uint64_t Mask) {
/// Compute the reciprocal block throughput from a set of processor resource
/// cycles. The reciprocal block throughput is computed as the MAX between:
/// - NumMicroOps / DispatchWidth
-/// - ProcReleaseAtCycles / #ProcResourceUnits (for every consumed resource).
+/// - ProcNumCyclesUsed / #ProcResourceUnits (for every consumed resource).
double computeBlockRThroughput(const MCSchedModel &SM, unsigned DispatchWidth,
unsigned NumMicroOps,
ArrayRef<unsigned> ProcResourceUsage);
diff --git a/llvm/lib/MCA/HardwareUnits/ResourceManager.cpp b/llvm/lib/MCA/HardwareUnits/ResourceManager.cpp
index 8d99695f4c29e..d58e3e68cdd32 100644
--- a/llvm/lib/MCA/HardwareUnits/ResourceManager.cpp
+++ b/llvm/lib/MCA/HardwareUnits/ResourceManager.cpp
@@ -346,7 +346,7 @@ uint64_t ResourceManager::checkAvailability(const InstrDesc &Desc) const {
void ResourceManager::issueInstruction(
const InstrDesc &Desc,
- SmallVectorImpl<std::pair<ResourceRef, ReleaseAtCycles>> &Pipes) {
+ SmallVectorImpl<std::pair<ResourceRef, NumCyclesUsed>> &Pipes) {
for (const std::pair<uint64_t, ResourceUsage> &R : Desc.Resources) {
const CycleSegment &CS = R.second.CS;
if (!CS.size()) {
@@ -354,13 +354,13 @@ void ResourceManager::issueInstruction(
continue;
}
- assert(CS.begin() == 0 && "Invalid {Start, End} cycles!");
+ assert(CS.isValid() && "Invalid {Start, End} cycles!");
if (!R.second.isReserved()) {
ResourceRef Pipe = selectPipe(R.first);
use(Pipe);
BusyResources[Pipe] += CS.size();
- Pipes.emplace_back(std::pair<ResourceRef, ReleaseAtCycles>(
- Pipe, ReleaseAtCycles(CS.size())));
+ Pipes.emplace_back(std::pair<ResourceRef, NumCyclesUsed>(
+ Pipe, NumCyclesUsed(CS.size())));
} else {
assert((llvm::popcount(R.first) > 1) && "Expected a group!");
// Mark this group as reserved.
diff --git a/llvm/lib/MCA/HardwareUnits/Scheduler.cpp b/llvm/lib/MCA/HardwareUnits/Scheduler.cpp
index a9bbf69799198..06013d4d0cfd5 100644
--- a/llvm/lib/MCA/HardwareUnits/Scheduler.cpp
+++ b/llvm/lib/MCA/HardwareUnits/Scheduler.cpp
@@ -69,7 +69,7 @@ Scheduler::Status Scheduler::isAvailable(const InstRef &IR) {
void Scheduler::issueInstructionImpl(
InstRef &IR,
- SmallVectorImpl<std::pair<ResourceRef, ReleaseAtCycles>> &UsedResources) {
+ SmallVectorImpl<std::pair<ResourceRef, NumCyclesUsed>> &UsedResources) {
Instruction *IS = IR.getInstruction();
const InstrDesc &D = IS->getDesc();
@@ -98,7 +98,7 @@ void Scheduler::issueInstructionImpl(
// Release the buffered resources and issue the instruction.
void Scheduler::issueInstruction(
InstRef &IR,
- SmallVectorImpl<std::pair<ResourceRef, ReleaseAtCycles>> &UsedResources,
+ SmallVectorImpl<std::pair<ResourceRef, NumCyclesUsed>> &UsedResources,
SmallVectorImpl<InstRef> &PendingInstructions,
SmallVectorImpl<InstRef> &ReadyInstructions) {
const Instruction &Inst = *IR.getInstruction();
diff --git a/llvm/lib/MCA/InstrBuilder.cpp b/llvm/lib/MCA/InstrBuilder.cpp
index 1a82e45763a26..f346368da5de8 100644
--- a/llvm/lib/MCA/InstrBuilder.cpp
+++ b/llvm/lib/MCA/InstrBuilder.cpp
@@ -89,11 +89,11 @@ static void initializeUsedResources(InstrDesc &ID,
AllInOrderResources &= (PR.BufferSize <= 1);
}
- CycleSegment RCy(0, PRE->ReleaseAtCycle, false);
+ CycleSegment RCy(PRE->AcquireAtCycle, PRE->ReleaseAtCycle, false);
Worklist.emplace_back(ResourcePlusCycles(Mask, ResourceUsage(RCy)));
if (PR.SuperIdx) {
uint64_t Super = ProcResourceMasks[PR.SuperIdx];
- SuperResources[Super] += PRE->ReleaseAtCycle;
+ SuperResources[Super] += PRE->ReleaseAtCycle - PRE->AcquireAtCycle;
}
}
diff --git a/llvm/lib/MCA/Stages/InstructionTables.cpp b/llvm/lib/MCA/Stages/InstructionTables.cpp
index 937cc7da8de72..c4e83d00f4769 100644
--- a/llvm/lib/MCA/Stages/InstructionTables.cpp
+++ b/llvm/lib/MCA/Stages/InstructionTables.cpp
@@ -38,7 +38,7 @@ Error InstructionTables::execute(InstRef &IR) {
for (unsigned I = 0, E = NumUnits; I < E; ++I) {
ResourceRef ResourceUnit = std::make_pair(Index, 1U << I);
UsedResources.emplace_back(
- std::make_pair(ResourceUnit, ReleaseAtCycles(Cycles, NumUnits)));
+ std::make_pair(ResourceUnit, NumCyclesUsed(Cycles, NumUnits)));
}
continue;
}
@@ -54,7 +54,7 @@ Error InstructionTables::execute(InstRef &IR) {
ResourceRef ResourceUnit = std::make_pair(SubUnitIdx, 1U << I2);
UsedResources.emplace_back(std::make_pair(
ResourceUnit,
- ReleaseAtCycles(Cycles, NumUnits * SubUnit.NumUnits)));
+ NumCyclesUsed(Cycles, NumUnits * SubUnit.NumUnits)));
}
}
}
diff --git a/llvm/lib/MCA/Support.cpp b/llvm/lib/MCA/Support.cpp
index f8b8a2d129c1c..849a0c7aa01f6 100644
--- a/llvm/lib/MCA/Support.cpp
+++ b/llvm/lib/MCA/Support.cpp
@@ -21,7 +21,7 @@ namespace mca {
#define DEBUG_TYPE "llvm-mca"
-ReleaseAtCycles &ReleaseAtCycles::operator+=(const ReleaseAtCycles &RHS) {
+NumCyclesUsed &NumCyclesUsed::operator+=(const NumCyclesUsed &RHS) {
if (Denominator == RHS.Denominator)
Numerator += RHS.Numerator;
else {
@@ -92,18 +92,18 @@ double computeBlockRThroughput(const MCSchedModel &SM, unsigned DispatchWidth,
// The number of available resource units affects the resource pressure
// distribution, as well as how many blocks can be executed every cycle.
for (unsigned I = 0, E = SM.getNumProcResourceKinds(); I < E; ++I) {
- unsigned ReleaseAtCycles = ProcResourceUsage[I];
- if (!ReleaseAtCycles)
+ unsigned NumCyclesUsed = ProcResourceUsage[I];
+ if (!NumCyclesUsed)
continue;
const MCProcResourceDesc &MCDesc = *SM.getProcResource(I);
- double Throughput = static_cast<double>(ReleaseAtCycles) / MCDesc.NumUnits;
+ double Throughput = static_cast<double>(NumCyclesUsed) / MCDesc.NumUnits;
Max = std::max(Max, Throughput);
}
// The block reciprocal throughput is computed as the MAX of:
// - (NumMicroOps / DispatchWidth)
- // - (NumUnits / ReleaseAtCycles) for every consumed processor resource.
+ // - (NumUnits / NumCyclesUsed) for every consumed processor resource.
return Max;
}
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFive7/reductions.s b/llvm/test/tools/llvm-mca/RISCV/SiFive7/reductions.s
index a6b756ba8151b..6ffb2bd1a23d1 100644
--- a/llvm/test/tools/llvm-mca/RISCV/SiFive7/reductions.s
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFive7/reductions.s
@@ -223,13 +223,13 @@ vfredmin.vs v4, v8, v12
# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 206
-# CHECK-NEXT: Total Cycles: 8746
+# CHECK-NEXT: Total Cycles: 8644
# CHECK-NEXT: Total uOps: 206
# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.02
# CHECK-NEXT: IPC: 0.02
-# CHECK-NEXT: Block RThroughput: 8743.0
+# CHECK-NEXT: Block RThroughput: 8640.0
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
@@ -459,213 +459,213 @@ vfredmin.vs v4, v8, v12
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
-# CHECK-NEXT: - - 103.00 - 8743.00 103.00 - -
+# CHECK-NEXT: - - 103.00 - 8640.00 103.00 - -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - 47.00 1.00 - - vredsum.vs v4, v8, v12
+# CHECK-NEXT: - - - - 46.00 1.00 - - vredsum.vs v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - 47.00 1.00 - - vredsum.vs v4, v8, v12
+# CHECK-NEXT: - - - - 46.00 1.00 - - vredsum.vs v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - 47.00 1.00 - - vredsum.vs v4, v8, v12
+# CHECK-NEXT: - - - - 46.00 1.00 - - vredsum.vs v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - 48.00 1.00 - - vredsum.vs v4, v8, v12
+# CHECK-NEXT: - - - - 47.00 1.00 - - vredsum.vs v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: - - - - 50.00 1.00 - - vredsum.vs v4, v8, v12
+# CHECK-NEXT: - - - - 49.00 1.00 - - vredsum.vs v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: - - - - 54.00 1.00 - - vredsum.vs v4, v8, v12
+# CHECK-NEXT: - - - - 53.00 1.00 - - vredsum.vs v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: - - - - 62.00 1.00 - - vredsum.vs v4, v8, v12
+# CHECK-NEXT: - - - - 61.00 1.00 - - vredsum.vs v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: - - - - 42.00 1.00 - - vredand.vs v4, v8, v12
+# CHECK-NEXT: - - - - 41.00 1.00 - - vredand.vs v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - 42.00 1.00 - - vredand.vs v4, v8, v12
+# CHECK-NEXT: - - - - 41.00 1.00 - - vredand.vs v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - 43.00 1.00 - - vredand.vs v4, v8, v12
+# CHECK-NEXT: - - - - 42.00 1.00 - - vredand.vs v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: - - - - 45.00 1.00 - - vredand.vs v4, v8, v12
+# CHECK-NEXT: - - - - 44.00 1.00 - - vredand.vs v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: - - - - 49.00 1.00 - - vredand.vs v4, v8, v12
+# CHECK-NEXT: - - - - 48.00 1.00 - - vredand.vs v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: - - - - 57.00 1.00 - - vredand.vs v4, v8, v12
+# CHECK-NEXT: - - - - 56.00 1.00 - - vredand.vs v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - 37.00 1.00 - - vredor.vs v4, v8, v12
+# CHECK-NEXT: - - - - 36.00 1.00 - - vredor.vs v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - 38.00 1.00 - - vredor.vs v4, v8, v12
+# CHECK-NEXT: - - - - 37.00 1.00 - - vredor.vs v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - 40.00 1.00 - - vredor.vs v4, v8, v12
+# CHECK-NEXT: - - - - 39.00 1.00 - - vredor.vs v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - - 44.00 1.00 - - vredor.vs v4, v8, v12
+# CHECK-NEXT: - - - - 43.00 1.00 - - vredor.vs v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: - - - - 52.00 1.00 - - vredor.vs v4, v8, v12
+# CHECK-NEXT: - - - - 51.00 1.00 - - vredor.vs v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - 33.00 1.00 - - vredxor.vs v4, v8, v12
+# CHECK-NEXT: - - - - 32.00 1.00 - - vredxor.vs v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: - - - - 35.00 1.00 - - vredxor.vs v4, v8, v12
+# CHECK-NEXT: - - - - 34.00 1.00 - - vredxor.vs v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: - - - - 39.00 1.00 - - vredxor.vs v4, v8, v12
+# CHECK-NEXT: - - - - 38.00 1.00 - - vredxor.vs v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: - - - - 47.00 1.00 - - vredxor.vs v4, v8, v12
+# CHECK-NEXT: - - - - 46.00 1.00 - - vredxor.vs v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - 47.00 1.00 - - vredmaxu.vs v4, v8, v12
+# CHECK-NEXT: - - - - 46.00 1.00 - - vredmaxu.vs v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - 47.00 1.00 - - vredmaxu.vs v4, v8, v12
+# CHECK-NEXT: - - - - 46.00 1.00 - - vredmaxu.vs v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - 47.00 1.00 - - vredmaxu.vs v4, v8, v12
+# CHECK-NEXT: - - - - 46.00 1.00 - - vredmaxu.vs v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - 48.00 1.00 - - vredmaxu.vs v4, v8, v12
+# CHECK-NEXT: - - - - 47.00 1.00 - - vredmaxu.vs v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: - - - - 50.00 1.00 - - vredmaxu.vs v4, v8, v12
+# CHECK-NEXT: - - - - 49.00 1.00 - - vredmaxu.vs v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: - - - - 54.00 1.00 - - vredmaxu.vs v4, v8, v12
+# CHECK-NEXT: - - - - 53.00 1.00 - - vredmaxu.vs v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: - - - - 62.00 1.00 - - vredmaxu.vs v4, v8, v12
+# CHECK-NEXT: - - - - 61.00 1.00 - - vredmaxu.vs v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: - - - - 42.00 1.00 - - vredmax.vs v4, v8, v12
+# CHECK-NEXT: - - - - 41.00 1.00 - - vredmax.vs v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - 42.00 1.00 - - vredmax.vs v4, v8, v12
+# CHECK-NEXT: - - - - 41.00 1.00 - - vredmax.vs v4, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/80742
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