[llvm] [GISel] Add support for scalable vectors in getLCMType (PR #80306)

[Thorsten Schütt via llvm-commits]

tschuett wrote:

Up to you, but to me it looks like misuse. I can unmerge  32bit into 4 8bit registers. But unmerging scalable vectors looks strange. Then you would need vector registers of different sizes. For AArch64 there are 32 scalable vector registers, Z0-Z31. They all have the same unknown scalable size.

https://github.com/llvm/llvm-project/pull/80306