[llvm] [SystemZ] Implement A, O and R inline assembly format flags (PR #80685)

[Ilya Leoshkevich via llvm-commits]

https://github.com/iii-i updated https://github.com/llvm/llvm-project/pull/80685

>From 7744e2b10fa4f1e179dabe09042be972847ce4a9 Mon Sep 17 00:00:00 2001
From: Ilya Leoshkevich <iii at linux.ibm.com>
Date: Fri, 5 Jan 2024 23:11:51 +0100
Subject: [PATCH] [SystemZ] Implement A, O and R inline assembly format flags

Implement the following assembly format flags, which are already
supported by GCC:

    'A': On z14 or higher: If operand is a mem print the alignment
         hint usable with vl/vst prefixed by a comma.
    'O': print only the displacement of a memory reference or address.
    'R': print only the base register of a memory reference or address.

Implement 'A' conservatively, since the memory operand alignment
information is not available for INLINEASM at the moment.
---
 llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp | 27 ++++++++++++++++---
 llvm/test/CodeGen/SystemZ/asm-01.ll           | 11 ++++++++
 2 files changed, 34 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
index 243461c0316e53..b68adf9386aa45 100644
--- a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
@@ -889,13 +889,17 @@ static void printFormattedRegName(const MCAsmInfo *MAI, unsigned RegNo,
     OS << '%' << RegName;
 }
 
+static void printReg(unsigned Reg, const MCAsmInfo *MAI, raw_ostream &OS) {
+  if (!Reg)
+    OS << '0';
+  else
+    printFormattedRegName(MAI, Reg, OS);
+}
+
 static void printOperand(const MCOperand &MCOp, const MCAsmInfo *MAI,
                          raw_ostream &OS) {
   if (MCOp.isReg()) {
-    if (!MCOp.getReg())
-      OS << '0';
-    else
-      printFormattedRegName(MAI, MCOp.getReg(), OS);
+    printReg(MCOp.getReg(), MAI, OS);
   } else if (MCOp.isImm())
     OS << MCOp.getImm();
   else if (MCOp.isExpr())
@@ -946,6 +950,21 @@ bool SystemZAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
                                               unsigned OpNo,
                                               const char *ExtraCode,
                                               raw_ostream &OS) {
+  if (ExtraCode && ExtraCode[0] && !ExtraCode[1]) {
+    switch (ExtraCode[0]) {
+    case 'A':
+      // Unlike EmitMachineNode(), EmitSpecialNode(INLINEASM) does not call
+      // setMemRefs(), so MI->memoperands() is empty and the alignment
+      // information is not available.
+      return false;
+    case 'O':
+      OS << MI->getOperand(OpNo + 1).getImm();
+      return false;
+    case 'R':
+      ::printReg(MI->getOperand(OpNo).getReg(), MAI, OS);
+      return false;
+    }
+  }
   printAddress(MAI, MI->getOperand(OpNo).getReg(),
                MCOperand::createImm(MI->getOperand(OpNo + 1).getImm()),
                MI->getOperand(OpNo + 2).getReg(), OS);
diff --git a/llvm/test/CodeGen/SystemZ/asm-01.ll b/llvm/test/CodeGen/SystemZ/asm-01.ll
index 2c4613cacb07c5..28278d75b4e757 100644
--- a/llvm/test/CodeGen/SystemZ/asm-01.ll
+++ b/llvm/test/CodeGen/SystemZ/asm-01.ll
@@ -59,3 +59,14 @@ define void @f5(i64 %base, i64 %index) {
   call void asm "blah $0", "=*Q" (ptr elementtype(i64) %addr)
   ret void
 }
+
+; Check A, O and R format flags.
+define void @f6(i64 %base) {
+; CHECK-LABEL: f6:
+; CHECK: blah 111,%r2
+; CHECK: br %r14
+  %add = add i64 %base, 111
+  %addr = inttoptr i64 %add to ptr
+  call void asm "blah ${0:O},${0:R}${0:A}", "=*Q" (ptr elementtype(i64) %addr)
+  ret void
+}