[llvm] 1af0536 - [X86] getShuffleComment - use MI description to determine AVX512 masked predicates instead of src index offsets.

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2024-02-05T14:22:46Z
New Revision: 1af05363d6353d7edd0d00e37ae0eb70f54b4b64

URL: https://github.com/llvm/llvm-project/commit/1af05363d6353d7edd0d00e37ae0eb70f54b4b64
DIFF: https://github.com/llvm/llvm-project/commit/1af05363d6353d7edd0d00e37ae0eb70f54b4b64.diff

LOG: [X86] getShuffleComment - use MI description to determine AVX512 masked predicates instead of src index offsets.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86MCInstLower.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp
index 31779f62547a6..aa060de3bfefd 100644
--- a/llvm/lib/Target/X86/X86MCInstLower.cpp
+++ b/llvm/lib/Target/X86/X86MCInstLower.cpp
@@ -1448,16 +1448,11 @@ static std::string getShuffleComment(const MachineInstr *MI, unsigned SrcOp1Idx,
   // Handle AVX512 MASK/MASXZ write mask comments.
   // MASK: zmmX {%kY}
   // MASKZ: zmmX {%kY} {z}
-  if (SrcOp1Idx > 1) {
-    assert((SrcOp1Idx == 2 || SrcOp1Idx == 3) && "Unexpected writemask");
-
+  if (X86II::isKMasked(MI->getDesc().TSFlags)) {
     const MachineOperand &WriteMaskOp = MI->getOperand(SrcOp1Idx - 1);
-    if (WriteMaskOp.isReg()) {
-      CS << " {%" << GetRegisterName(WriteMaskOp.getReg()) << "}";
-
-      if (SrcOp1Idx == 2) {
-        CS << " {z}";
-      }
+    CS << " {%" << GetRegisterName(WriteMaskOp.getReg()) << "}";
+    if (!X86II::isKMergeMasked(MI->getDesc().TSFlags)) {
+      CS << " {z}";
     }
   }