[llvm] AMDGPU: Set max supported div/rem size to 64 (PR #80669)

Mon Feb 5 04:01:34 PST 2024

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/80669

This enables IR expansion for i128 divisions. The vector case is still broken because ExpandLargeDivRem doesn't try to handle them.

Fixes: SWDEV-426193

>From bd26bbb33ef87ab4bbfa3430d860d1da362ea943 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Mon, 5 Feb 2024 17:23:23 +0530
Subject: [PATCH] AMDGPU: Set max supported div/rem size to 64

This enables IR expansion for i128 divisions. The vector case is
still broken because ExpandLargeDivRem doesn't try to handle them.

Fixes: SWDEV-426193
---
 llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp |    1 +
 llvm/test/CodeGen/AMDGPU/div_i128.ll          | 1647 ++++++++++++++++-
 llvm/test/CodeGen/AMDGPU/div_v2i128.ll        |   25 +
 3 files changed, 1669 insertions(+), 4 deletions(-)
 create mode 100644 llvm/test/CodeGen/AMDGPU/div_v2i128.ll

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index b420e72d87ed0..10569d97248b9 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -577,6 +577,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
                        ISD::AssertSext, ISD::INTRINSIC_WO_CHAIN});
 
   setMaxAtomicSizeInBitsSupported(64);
+  setMaxDivRemBitWidthSupported(64);
 }
 
 bool AMDGPUTargetLowering::mayIgnoreSignedZero(SDValue Op) const {
diff --git a/llvm/test/CodeGen/AMDGPU/div_i128.ll b/llvm/test/CodeGen/AMDGPU/div_i128.ll
index 4aa97c57cbd9c..c673ac8e03ff7 100644
--- a/llvm/test/CodeGen/AMDGPU/div_i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/div_i128.ll
@@ -1,9 +1,1648 @@
-; RUN: not --crash llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -o - %s 2>&1 | FileCheck -check-prefix=SDAG-ERR %s
-; RUN: not --crash llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -o - %s 2>&1 | FileCheck -check-prefix=GISEL-ERR %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
 
-; SDAG-ERR: LLVM ERROR: unsupported libcall legalization
-; GISEL-ERR: LLVM ERROR: unable to legalize instruction: %{{[0-9]+}}:_(s128) = G_SDIV %{{[0-9]+}}:_, %{{[0-9]+}}:_ (in function: v_sdiv_i128_vv)
 define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) {
+; GFX9-SDAG-LABEL: v_sdiv_i128_vv:
+; GFX9-SDAG:       ; %bb.0: ; %_udiv-special-cases
+; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT:    v_ashrrev_i32_e32 v16, 31, v3
+; GFX9-SDAG-NEXT:    v_xor_b32_e32 v0, v16, v0
+; GFX9-SDAG-NEXT:    v_xor_b32_e32 v1, v16, v1
+; GFX9-SDAG-NEXT:    v_sub_co_u32_e32 v8, vcc, v0, v16
+; GFX9-SDAG-NEXT:    v_xor_b32_e32 v2, v16, v2
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v9, vcc, v1, v16, vcc
+; GFX9-SDAG-NEXT:    v_ashrrev_i32_e32 v17, 31, v7
+; GFX9-SDAG-NEXT:    v_xor_b32_e32 v3, v16, v3
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v10, vcc, v2, v16, vcc
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v11, vcc, v3, v16, vcc
+; GFX9-SDAG-NEXT:    v_xor_b32_e32 v3, v17, v4
+; GFX9-SDAG-NEXT:    v_xor_b32_e32 v2, v17, v5
+; GFX9-SDAG-NEXT:    v_sub_co_u32_e32 v20, vcc, v3, v17
+; GFX9-SDAG-NEXT:    v_xor_b32_e32 v0, v17, v6
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v21, vcc, v2, v17, vcc
+; GFX9-SDAG-NEXT:    v_xor_b32_e32 v1, v17, v7
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v0, vcc, v0, v17, vcc
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v17, vcc
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v3, v21, v1
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v2, v20, v0
+; GFX9-SDAG-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[2:3]
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v3, v9, v11
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v2, v8, v10
+; GFX9-SDAG-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[2:3]
+; GFX9-SDAG-NEXT:    v_ffbh_u32_e32 v2, v0
+; GFX9-SDAG-NEXT:    v_add_u32_e32 v2, 32, v2
+; GFX9-SDAG-NEXT:    v_ffbh_u32_e32 v3, v1
+; GFX9-SDAG-NEXT:    v_min_u32_e32 v2, v2, v3
+; GFX9-SDAG-NEXT:    v_ffbh_u32_e32 v3, v20
+; GFX9-SDAG-NEXT:    v_add_u32_e32 v3, 32, v3
+; GFX9-SDAG-NEXT:    v_ffbh_u32_e32 v4, v21
+; GFX9-SDAG-NEXT:    v_min_u32_e32 v3, v3, v4
+; GFX9-SDAG-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
+; GFX9-SDAG-NEXT:    v_add_co_u32_e32 v3, vcc, 64, v3
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e64 v4, s[6:7], 0, 0, vcc
+; GFX9-SDAG-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[0:1]
+; GFX9-SDAG-NEXT:    v_ffbh_u32_e32 v5, v11
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
+; GFX9-SDAG-NEXT:    v_ffbh_u32_e32 v3, v10
+; GFX9-SDAG-NEXT:    v_add_u32_e32 v3, 32, v3
+; GFX9-SDAG-NEXT:    v_min_u32_e32 v3, v3, v5
+; GFX9-SDAG-NEXT:    v_ffbh_u32_e32 v5, v8
+; GFX9-SDAG-NEXT:    v_add_u32_e32 v5, 32, v5
+; GFX9-SDAG-NEXT:    v_ffbh_u32_e32 v6, v9
+; GFX9-SDAG-NEXT:    v_min_u32_e32 v5, v5, v6
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v4, v4, 0, vcc
+; GFX9-SDAG-NEXT:    v_add_co_u32_e32 v5, vcc, 64, v5
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e64 v6, s[6:7], 0, 0, vcc
+; GFX9-SDAG-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[10:11]
+; GFX9-SDAG-NEXT:    s_mov_b64 s[6:7], 0x7f
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v6, v6, 0, vcc
+; GFX9-SDAG-NEXT:    v_sub_co_u32_e32 v2, vcc, v2, v3
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v3, vcc, v4, v6, vcc
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v5, 0
+; GFX9-SDAG-NEXT:    v_subbrev_co_u32_e32 v4, vcc, 0, v5, vcc
+; GFX9-SDAG-NEXT:    v_subbrev_co_u32_e32 v5, vcc, 0, v5, vcc
+; GFX9-SDAG-NEXT:    v_cmp_lt_u64_e32 vcc, s[6:7], v[2:3]
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v18, v16
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GFX9-SDAG-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[4:5]
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v19, v17
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GFX9-SDAG-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[4:5]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc
+; GFX9-SDAG-NEXT:    v_and_b32_e32 v6, 1, v6
+; GFX9-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v6
+; GFX9-SDAG-NEXT:    v_xor_b32_e32 v6, 0x7f, v2
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v7, v3, v5
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v6, v6, v4
+; GFX9-SDAG-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
+; GFX9-SDAG-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[6:7]
+; GFX9-SDAG-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v13, v11, 0, s[4:5]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v12, v10, 0, s[4:5]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v7, v9, 0, s[4:5]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v6, v8, 0, s[4:5]
+; GFX9-SDAG-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
+; GFX9-SDAG-NEXT:    s_and_saveexec_b64 s[8:9], s[4:5]
+; GFX9-SDAG-NEXT:    s_cbranch_execz .LBB0_6
+; GFX9-SDAG-NEXT:  ; %bb.1: ; %udiv-bb1
+; GFX9-SDAG-NEXT:    v_add_co_u32_e32 v22, vcc, 1, v2
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v23, vcc, 0, v3, vcc
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v24, vcc, 0, v4, vcc
+; GFX9-SDAG-NEXT:    v_sub_u32_e32 v7, 0x7f, v2
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v25, vcc, 0, v5, vcc
+; GFX9-SDAG-NEXT:    v_sub_u32_e32 v12, 64, v7
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v4, v23, v25
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v3, v22, v24
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[5:6], v7, v[10:11]
+; GFX9-SDAG-NEXT:    v_lshrrev_b64 v[12:13], v12, v[8:9]
+; GFX9-SDAG-NEXT:    v_sub_u32_e32 v2, 63, v2
+; GFX9-SDAG-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[3:4]
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[2:3], v2, v[8:9]
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v4, v6, v13
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v5, v5, v12
+; GFX9-SDAG-NEXT:    v_cmp_gt_u32_e64 s[4:5], 64, v7
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v3, v3, v4, s[4:5]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v2, v2, v5, s[4:5]
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[4:5], v7, v[8:9]
+; GFX9-SDAG-NEXT:    v_cmp_eq_u32_e64 s[6:7], 0, v7
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v6, 0
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v12, 0
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v3, v3, v11, s[6:7]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v2, v2, v10, s[6:7]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v5, 0, v5, s[4:5]
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v7, 0
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v13, 0
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v4, 0, v4, s[4:5]
+; GFX9-SDAG-NEXT:    s_and_saveexec_b64 s[4:5], vcc
+; GFX9-SDAG-NEXT:    s_xor_b64 s[6:7], exec, s[4:5]
+; GFX9-SDAG-NEXT:    s_cbranch_execz .LBB0_5
+; GFX9-SDAG-NEXT:  ; %bb.2: ; %udiv-preheader
+; GFX9-SDAG-NEXT:    v_sub_u32_e32 v12, 64, v22
+; GFX9-SDAG-NEXT:    v_lshrrev_b64 v[6:7], v22, v[8:9]
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[12:13], v12, v[10:11]
+; GFX9-SDAG-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v22
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v12, v6, v12
+; GFX9-SDAG-NEXT:    v_subrev_u32_e32 v6, 64, v22
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v13, v7, v13
+; GFX9-SDAG-NEXT:    v_lshrrev_b64 v[6:7], v6, v[10:11]
+; GFX9-SDAG-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v22
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v7, v7, v13, vcc
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v9, v7, v9, s[4:5]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v12, v6, v12, vcc
+; GFX9-SDAG-NEXT:    v_lshrrev_b64 v[6:7], v22, v[10:11]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v8, v12, v8, s[4:5]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v11, 0, v7, vcc
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v10, 0, v6, vcc
+; GFX9-SDAG-NEXT:    v_add_co_u32_e32 v26, vcc, -1, v20
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v27, vcc, -1, v21, vcc
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v28, vcc, -1, v0, vcc
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v14, 0
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v12, 0
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v29, vcc, -1, v1, vcc
+; GFX9-SDAG-NEXT:    s_mov_b64 s[4:5], 0
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v15, 0
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v13, 0
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v7, 0
+; GFX9-SDAG-NEXT:  .LBB0_3: ; %udiv-do-while
+; GFX9-SDAG-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX9-SDAG-NEXT:    v_lshrrev_b32_e32 v6, 31, v5
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[4:5], 1, v[4:5]
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[10:11], 1, v[10:11]
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v4, v14, v4
+; GFX9-SDAG-NEXT:    v_lshrrev_b32_e32 v14, 31, v9
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[8:9], 1, v[8:9]
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v10, v10, v14
+; GFX9-SDAG-NEXT:    v_lshrrev_b32_e32 v14, 31, v3
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v8, v8, v14
+; GFX9-SDAG-NEXT:    v_sub_co_u32_e32 v14, vcc, v26, v8
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v14, vcc, v27, v9, vcc
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v14, vcc, v28, v10, vcc
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v14, vcc, v29, v11, vcc
+; GFX9-SDAG-NEXT:    v_ashrrev_i32_e32 v30, 31, v14
+; GFX9-SDAG-NEXT:    v_and_b32_e32 v14, v30, v20
+; GFX9-SDAG-NEXT:    v_sub_co_u32_e32 v8, vcc, v8, v14
+; GFX9-SDAG-NEXT:    v_and_b32_e32 v14, v30, v21
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v9, vcc, v9, v14, vcc
+; GFX9-SDAG-NEXT:    v_and_b32_e32 v14, v30, v0
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v10, vcc, v10, v14, vcc
+; GFX9-SDAG-NEXT:    v_and_b32_e32 v14, v30, v1
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v11, vcc, v11, v14, vcc
+; GFX9-SDAG-NEXT:    v_add_co_u32_e32 v22, vcc, -1, v22
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v23, vcc, -1, v23, vcc
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v24, vcc, -1, v24, vcc
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v25, vcc, -1, v25, vcc
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v5, v15, v5
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[2:3], 1, v[2:3]
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v14, v22, v24
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v15, v23, v25
+; GFX9-SDAG-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[14:15]
+; GFX9-SDAG-NEXT:    v_or3_b32 v2, v2, v6, v12
+; GFX9-SDAG-NEXT:    v_and_b32_e32 v6, 1, v30
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v15, v7
+; GFX9-SDAG-NEXT:    v_or3_b32 v3, v3, 0, v13
+; GFX9-SDAG-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v14, v6
+; GFX9-SDAG-NEXT:    s_andn2_b64 exec, exec, s[4:5]
+; GFX9-SDAG-NEXT:    s_cbranch_execnz .LBB0_3
+; GFX9-SDAG-NEXT:  ; %bb.4: ; %Flow
+; GFX9-SDAG-NEXT:    s_or_b64 exec, exec, s[4:5]
+; GFX9-SDAG-NEXT:  .LBB0_5: ; %Flow2
+; GFX9-SDAG-NEXT:    s_or_b64 exec, exec, s[6:7]
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[0:1], 1, v[4:5]
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[2:3], 1, v[2:3]
+; GFX9-SDAG-NEXT:    v_lshrrev_b32_e32 v4, 31, v5
+; GFX9-SDAG-NEXT:    v_or3_b32 v13, v3, 0, v13
+; GFX9-SDAG-NEXT:    v_or3_b32 v12, v2, v4, v12
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v7, v7, v1
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v6, v6, v0
+; GFX9-SDAG-NEXT:  .LBB0_6: ; %Flow3
+; GFX9-SDAG-NEXT:    s_or_b64 exec, exec, s[8:9]
+; GFX9-SDAG-NEXT:    v_xor_b32_e32 v2, v17, v16
+; GFX9-SDAG-NEXT:    v_xor_b32_e32 v3, v19, v18
+; GFX9-SDAG-NEXT:    v_xor_b32_e32 v0, v6, v2
+; GFX9-SDAG-NEXT:    v_xor_b32_e32 v1, v7, v3
+; GFX9-SDAG-NEXT:    v_sub_co_u32_e32 v0, vcc, v0, v2
+; GFX9-SDAG-NEXT:    v_xor_b32_e32 v5, v12, v2
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v3, vcc
+; GFX9-SDAG-NEXT:    v_xor_b32_e32 v4, v13, v3
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v2, vcc, v5, v2, vcc
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v3, vcc, v4, v3, vcc
+; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-GISEL-LABEL: v_sdiv_i128_vv:
+; GFX9-GISEL:       ; %bb.0: ; %_udiv-special-cases
+; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT:    v_ashrrev_i32_e32 v16, 31, v3
+; GFX9-GISEL-NEXT:    v_xor_b32_e32 v0, v16, v0
+; GFX9-GISEL-NEXT:    v_xor_b32_e32 v1, v16, v1
+; GFX9-GISEL-NEXT:    v_sub_co_u32_e32 v10, vcc, v0, v16
+; GFX9-GISEL-NEXT:    v_xor_b32_e32 v2, v16, v2
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v11, vcc, v1, v16, vcc
+; GFX9-GISEL-NEXT:    v_ashrrev_i32_e32 v17, 31, v7
+; GFX9-GISEL-NEXT:    v_xor_b32_e32 v3, v16, v3
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v12, vcc, v2, v16, vcc
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v13, vcc, v3, v16, vcc
+; GFX9-GISEL-NEXT:    v_xor_b32_e32 v0, v17, v4
+; GFX9-GISEL-NEXT:    v_xor_b32_e32 v1, v17, v5
+; GFX9-GISEL-NEXT:    v_sub_co_u32_e32 v18, vcc, v0, v17
+; GFX9-GISEL-NEXT:    v_xor_b32_e32 v2, v17, v6
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v19, vcc, v1, v17, vcc
+; GFX9-GISEL-NEXT:    v_xor_b32_e32 v3, v17, v7
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v4, vcc, v2, v17, vcc
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v5, vcc, v3, v17, vcc
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v0, v18, v4
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v1, v19, v5
+; GFX9-GISEL-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[0:1]
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v0, v10, v12
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v1, v11, v13
+; GFX9-GISEL-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
+; GFX9-GISEL-NEXT:    v_ffbh_u32_e32 v1, v18
+; GFX9-GISEL-NEXT:    v_ffbh_u32_e32 v0, v19
+; GFX9-GISEL-NEXT:    v_add_u32_e32 v1, 32, v1
+; GFX9-GISEL-NEXT:    v_ffbh_u32_e32 v2, v4
+; GFX9-GISEL-NEXT:    v_min_u32_e32 v0, v0, v1
+; GFX9-GISEL-NEXT:    v_ffbh_u32_e32 v1, v5
+; GFX9-GISEL-NEXT:    v_add_u32_e32 v2, 32, v2
+; GFX9-GISEL-NEXT:    v_cmp_eq_u64_e64 s[6:7], 0, v[4:5]
+; GFX9-GISEL-NEXT:    v_add_u32_e32 v0, 64, v0
+; GFX9-GISEL-NEXT:    v_min_u32_e32 v1, v1, v2
+; GFX9-GISEL-NEXT:    v_ffbh_u32_e32 v2, v10
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v0, v1, v0, s[6:7]
+; GFX9-GISEL-NEXT:    v_ffbh_u32_e32 v1, v11
+; GFX9-GISEL-NEXT:    v_add_u32_e32 v2, 32, v2
+; GFX9-GISEL-NEXT:    v_ffbh_u32_e32 v3, v12
+; GFX9-GISEL-NEXT:    v_min_u32_e32 v1, v1, v2
+; GFX9-GISEL-NEXT:    v_ffbh_u32_e32 v2, v13
+; GFX9-GISEL-NEXT:    v_add_u32_e32 v3, 32, v3
+; GFX9-GISEL-NEXT:    v_cmp_eq_u64_e64 s[6:7], 0, v[12:13]
+; GFX9-GISEL-NEXT:    v_add_u32_e32 v1, 64, v1
+; GFX9-GISEL-NEXT:    v_min_u32_e32 v2, v2, v3
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v1, v2, v1, s[6:7]
+; GFX9-GISEL-NEXT:    v_sub_co_u32_e64 v0, s[6:7], v0, v1
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e64 v1, s[6:7], 0, 0, s[6:7]
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v6, 0x7f
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e64 v2, s[6:7], 0, 0, s[6:7]
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v7, 0
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e64 v3, s[6:7], 0, 0, s[6:7]
+; GFX9-GISEL-NEXT:    v_cmp_gt_u64_e64 s[6:7], v[0:1], v[6:7]
+; GFX9-GISEL-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[6:7]
+; GFX9-GISEL-NEXT:    v_cmp_lt_u64_e64 s[6:7], 0, v[2:3]
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v15, v1, v3
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, s[6:7]
+; GFX9-GISEL-NEXT:    v_cmp_eq_u64_e64 s[6:7], 0, v[2:3]
+; GFX9-GISEL-NEXT:    s_mov_b64 s[8:9], 0
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v6, v7, v6, s[6:7]
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, s[4:5]
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v20, v7, v6
+; GFX9-GISEL-NEXT:    v_xor_b32_e32 v6, 0x7f, v0
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v14, v6, v2
+; GFX9-GISEL-NEXT:    v_and_b32_e32 v6, 1, v20
+; GFX9-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v6, v10, 0, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v7, v11, 0, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v8, v12, 0, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v9, v13, 0, vcc
+; GFX9-GISEL-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[14:15]
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v14, v20, v14
+; GFX9-GISEL-NEXT:    v_and_b32_e32 v14, 1, v14
+; GFX9-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v14
+; GFX9-GISEL-NEXT:    s_xor_b64 s[4:5], vcc, -1
+; GFX9-GISEL-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
+; GFX9-GISEL-NEXT:    s_cbranch_execz .LBB0_6
+; GFX9-GISEL-NEXT:  ; %bb.1: ; %udiv-bb1
+; GFX9-GISEL-NEXT:    v_add_co_u32_e32 v20, vcc, 1, v0
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v21, vcc, 0, v1, vcc
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v22, vcc, 0, v2, vcc
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v23, vcc, 0, v3, vcc
+; GFX9-GISEL-NEXT:    s_xor_b64 s[4:5], vcc, -1
+; GFX9-GISEL-NEXT:    v_sub_co_u32_e32 v8, vcc, 0x7f, v0
+; GFX9-GISEL-NEXT:    v_sub_u32_e32 v0, 64, v8
+; GFX9-GISEL-NEXT:    v_lshrrev_b64 v[0:1], v0, v[10:11]
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[2:3], v8, v[12:13]
+; GFX9-GISEL-NEXT:    v_subrev_u32_e32 v9, 64, v8
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[6:7], v8, v[10:11]
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v2, v0, v2
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v3, v1, v3
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[0:1], v9, v[10:11]
+; GFX9-GISEL-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v8
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v6, 0, v6, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v7, 0, v7, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX9-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v8
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v8, v0, v12, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v9, v1, v13, vcc
+; GFX9-GISEL-NEXT:    s_mov_b64 s[10:11], s[8:9]
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v0, s8
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v1, s9
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v2, s10
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v3, s11
+; GFX9-GISEL-NEXT:    s_and_saveexec_b64 s[8:9], s[4:5]
+; GFX9-GISEL-NEXT:    s_xor_b64 s[12:13], exec, s[8:9]
+; GFX9-GISEL-NEXT:    s_cbranch_execz .LBB0_5
+; GFX9-GISEL-NEXT:  ; %bb.2: ; %udiv-preheader
+; GFX9-GISEL-NEXT:    v_sub_u32_e32 v2, 64, v20
+; GFX9-GISEL-NEXT:    v_lshrrev_b64 v[0:1], v20, v[10:11]
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[2:3], v2, v[12:13]
+; GFX9-GISEL-NEXT:    v_subrev_u32_e32 v24, 64, v20
+; GFX9-GISEL-NEXT:    v_lshrrev_b64 v[14:15], v20, v[12:13]
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v2, v0, v2
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v3, v1, v3
+; GFX9-GISEL-NEXT:    v_lshrrev_b64 v[0:1], v24, v[12:13]
+; GFX9-GISEL-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v20
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v14, 0, v14, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v15, 0, v15, vcc
+; GFX9-GISEL-NEXT:    v_add_co_u32_e32 v24, vcc, -1, v18
+; GFX9-GISEL-NEXT:    s_mov_b64 s[8:9], 0
+; GFX9-GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v20
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v25, vcc, -1, v19, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v12, v0, v10, s[4:5]
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v13, v1, v11, s[4:5]
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v26, vcc, -1, v4, vcc
+; GFX9-GISEL-NEXT:    s_mov_b64 s[10:11], s[8:9]
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v0, s8
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v27, vcc, -1, v5, vcc
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v11, 0
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v1, s9
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v2, s10
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v3, s11
+; GFX9-GISEL-NEXT:  .LBB0_3: ; %udiv-do-while
+; GFX9-GISEL-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[2:3], 1, v[6:7]
+; GFX9-GISEL-NEXT:    v_lshrrev_b32_e32 v10, 31, v7
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v6, v0, v2
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v7, v1, v3
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[2:3], 1, v[12:13]
+; GFX9-GISEL-NEXT:    v_lshrrev_b32_e32 v12, 31, v9
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[0:1], 1, v[14:15]
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v2, v2, v12
+; GFX9-GISEL-NEXT:    v_lshrrev_b32_e32 v14, 31, v13
+; GFX9-GISEL-NEXT:    v_sub_co_u32_e32 v12, vcc, v24, v2
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v0, v0, v14
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v12, vcc, v25, v3, vcc
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v12, vcc, v26, v0, vcc
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v12, vcc, v27, v1, vcc
+; GFX9-GISEL-NEXT:    v_ashrrev_i32_e32 v28, 31, v12
+; GFX9-GISEL-NEXT:    v_and_b32_e32 v12, v28, v18
+; GFX9-GISEL-NEXT:    v_sub_co_u32_e32 v12, vcc, v2, v12
+; GFX9-GISEL-NEXT:    v_and_b32_e32 v2, v28, v19
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v13, vcc, v3, v2, vcc
+; GFX9-GISEL-NEXT:    v_and_b32_e32 v2, v28, v4
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v14, vcc, v0, v2, vcc
+; GFX9-GISEL-NEXT:    v_and_b32_e32 v0, v28, v5
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v15, vcc, v1, v0, vcc
+; GFX9-GISEL-NEXT:    v_add_co_u32_e32 v20, vcc, -1, v20
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v21, vcc, -1, v21, vcc
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v22, vcc, -1, v22, vcc
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v23, vcc, -1, v23, vcc
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[8:9], 1, v[8:9]
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v0, v20, v22
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v1, v21, v23
+; GFX9-GISEL-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[0:1]
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v8, v8, v10
+; GFX9-GISEL-NEXT:    v_and_b32_e32 v10, 1, v28
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v0, v10
+; GFX9-GISEL-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v1, v11
+; GFX9-GISEL-NEXT:    s_andn2_b64 exec, exec, s[8:9]
+; GFX9-GISEL-NEXT:    s_cbranch_execnz .LBB0_3
+; GFX9-GISEL-NEXT:  ; %bb.4: ; %Flow
+; GFX9-GISEL-NEXT:    s_or_b64 exec, exec, s[8:9]
+; GFX9-GISEL-NEXT:  .LBB0_5: ; %Flow2
+; GFX9-GISEL-NEXT:    s_or_b64 exec, exec, s[12:13]
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[2:3], 1, v[6:7]
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[8:9], 1, v[8:9]
+; GFX9-GISEL-NEXT:    v_lshrrev_b32_e32 v4, 31, v7
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v8, v8, v4
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v6, v0, v2
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v7, v1, v3
+; GFX9-GISEL-NEXT:  .LBB0_6: ; %Flow3
+; GFX9-GISEL-NEXT:    s_or_b64 exec, exec, s[6:7]
+; GFX9-GISEL-NEXT:    v_xor_b32_e32 v3, v17, v16
+; GFX9-GISEL-NEXT:    v_xor_b32_e32 v0, v6, v3
+; GFX9-GISEL-NEXT:    v_xor_b32_e32 v1, v7, v3
+; GFX9-GISEL-NEXT:    v_sub_co_u32_e32 v0, vcc, v0, v3
+; GFX9-GISEL-NEXT:    v_xor_b32_e32 v2, v8, v3
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v3, vcc
+; GFX9-GISEL-NEXT:    v_xor_b32_e32 v4, v9, v3
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v2, vcc, v2, v3, vcc
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v3, vcc, v4, v3, vcc
+; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
   %shl = sdiv i128 %lhs, %rhs
   ret i128 %shl
 }
+
+define i128 @v_udiv_i128_vv(i128 %lhs, i128 %rhs) {
+; GFX9-SDAG-LABEL: v_udiv_i128_vv:
+; GFX9-SDAG:       ; %bb.0: ; %_udiv-special-cases
+; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v9, v5, v7
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v8, v4, v6
+; GFX9-SDAG-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[8:9]
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v9, v1, v3
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v8, v0, v2
+; GFX9-SDAG-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[8:9]
+; GFX9-SDAG-NEXT:    v_ffbh_u32_e32 v8, v6
+; GFX9-SDAG-NEXT:    v_add_u32_e32 v8, 32, v8
+; GFX9-SDAG-NEXT:    v_ffbh_u32_e32 v9, v7
+; GFX9-SDAG-NEXT:    v_min_u32_e32 v8, v8, v9
+; GFX9-SDAG-NEXT:    v_ffbh_u32_e32 v9, v4
+; GFX9-SDAG-NEXT:    v_add_u32_e32 v9, 32, v9
+; GFX9-SDAG-NEXT:    v_ffbh_u32_e32 v10, v5
+; GFX9-SDAG-NEXT:    v_min_u32_e32 v9, v9, v10
+; GFX9-SDAG-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
+; GFX9-SDAG-NEXT:    v_add_co_u32_e32 v9, vcc, 64, v9
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e64 v10, s[6:7], 0, 0, vcc
+; GFX9-SDAG-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[6:7]
+; GFX9-SDAG-NEXT:    v_ffbh_u32_e32 v11, v3
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v8, v9, v8, vcc
+; GFX9-SDAG-NEXT:    v_ffbh_u32_e32 v9, v2
+; GFX9-SDAG-NEXT:    v_add_u32_e32 v9, 32, v9
+; GFX9-SDAG-NEXT:    v_min_u32_e32 v9, v9, v11
+; GFX9-SDAG-NEXT:    v_ffbh_u32_e32 v11, v0
+; GFX9-SDAG-NEXT:    v_add_u32_e32 v11, 32, v11
+; GFX9-SDAG-NEXT:    v_ffbh_u32_e32 v12, v1
+; GFX9-SDAG-NEXT:    v_min_u32_e32 v11, v11, v12
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v10, v10, 0, vcc
+; GFX9-SDAG-NEXT:    v_add_co_u32_e32 v11, vcc, 64, v11
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e64 v12, s[6:7], 0, 0, vcc
+; GFX9-SDAG-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[2:3]
+; GFX9-SDAG-NEXT:    s_mov_b64 s[6:7], 0x7f
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v9, v11, v9, vcc
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v13, v12, 0, vcc
+; GFX9-SDAG-NEXT:    v_sub_co_u32_e32 v12, vcc, v8, v9
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v13, vcc, v10, v13, vcc
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v8, 0
+; GFX9-SDAG-NEXT:    v_subbrev_co_u32_e32 v14, vcc, 0, v8, vcc
+; GFX9-SDAG-NEXT:    v_subbrev_co_u32_e32 v15, vcc, 0, v8, vcc
+; GFX9-SDAG-NEXT:    v_cmp_lt_u64_e32 vcc, s[6:7], v[12:13]
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v10, v13, v15
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GFX9-SDAG-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[14:15]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; GFX9-SDAG-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[14:15]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v8, v9, v8, vcc
+; GFX9-SDAG-NEXT:    v_and_b32_e32 v8, 1, v8
+; GFX9-SDAG-NEXT:    v_xor_b32_e32 v9, 0x7f, v12
+; GFX9-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v8
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v9, v9, v14
+; GFX9-SDAG-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
+; GFX9-SDAG-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[9:10]
+; GFX9-SDAG-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v8, v3, 0, s[4:5]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v9, v2, 0, s[4:5]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v10, v1, 0, s[4:5]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v11, v0, 0, s[4:5]
+; GFX9-SDAG-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
+; GFX9-SDAG-NEXT:    s_and_saveexec_b64 s[8:9], s[4:5]
+; GFX9-SDAG-NEXT:    s_cbranch_execz .LBB1_6
+; GFX9-SDAG-NEXT:  ; %bb.1: ; %udiv-bb1
+; GFX9-SDAG-NEXT:    v_add_co_u32_e32 v18, vcc, 1, v12
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v19, vcc, 0, v13, vcc
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v20, vcc, 0, v14, vcc
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v21, vcc, 0, v15, vcc
+; GFX9-SDAG-NEXT:    v_sub_u32_e32 v15, 0x7f, v12
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v9, v19, v21
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v8, v18, v20
+; GFX9-SDAG-NEXT:    v_sub_u32_e32 v13, 64, v15
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[10:11], v15, v[2:3]
+; GFX9-SDAG-NEXT:    v_lshrrev_b64 v[13:14], v13, v[0:1]
+; GFX9-SDAG-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[8:9]
+; GFX9-SDAG-NEXT:    v_sub_u32_e32 v8, 63, v12
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[8:9], v8, v[0:1]
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v11, v11, v14
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v10, v10, v13
+; GFX9-SDAG-NEXT:    v_cmp_gt_u32_e64 s[4:5], 64, v15
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v9, v9, v11, s[4:5]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v8, v8, v10, s[4:5]
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[10:11], v15, v[0:1]
+; GFX9-SDAG-NEXT:    v_cmp_eq_u32_e64 s[6:7], 0, v15
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v12, 0
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v14, 0
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v9, v9, v3, s[6:7]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v8, v8, v2, s[6:7]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v11, 0, v11, s[4:5]
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v13, 0
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v15, 0
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v10, 0, v10, s[4:5]
+; GFX9-SDAG-NEXT:    s_and_saveexec_b64 s[4:5], vcc
+; GFX9-SDAG-NEXT:    s_xor_b64 s[6:7], exec, s[4:5]
+; GFX9-SDAG-NEXT:    s_cbranch_execz .LBB1_5
+; GFX9-SDAG-NEXT:  ; %bb.2: ; %udiv-preheader
+; GFX9-SDAG-NEXT:    v_sub_u32_e32 v14, 64, v18
+; GFX9-SDAG-NEXT:    v_lshrrev_b64 v[12:13], v18, v[0:1]
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[14:15], v14, v[2:3]
+; GFX9-SDAG-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v18
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v14, v12, v14
+; GFX9-SDAG-NEXT:    v_subrev_u32_e32 v12, 64, v18
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v15, v13, v15
+; GFX9-SDAG-NEXT:    v_lshrrev_b64 v[12:13], v12, v[2:3]
+; GFX9-SDAG-NEXT:    v_lshrrev_b64 v[2:3], v18, v[2:3]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v13, v13, v15, vcc
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v12, v12, v14, vcc
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v3, 0, v3, vcc
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v2, 0, v2, vcc
+; GFX9-SDAG-NEXT:    v_add_co_u32_e32 v22, vcc, -1, v4
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v23, vcc, -1, v5, vcc
+; GFX9-SDAG-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v18
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v24, vcc, -1, v6, vcc
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v16, 0
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v14, 0
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v1, v13, v1, s[4:5]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v0, v12, v0, s[4:5]
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v25, vcc, -1, v7, vcc
+; GFX9-SDAG-NEXT:    s_mov_b64 s[4:5], 0
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v17, 0
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v15, 0
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v13, 0
+; GFX9-SDAG-NEXT:  .LBB1_3: ; %udiv-do-while
+; GFX9-SDAG-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[26:27], 1, v[10:11]
+; GFX9-SDAG-NEXT:    v_lshrrev_b32_e32 v12, 31, v11
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v10, v16, v26
+; GFX9-SDAG-NEXT:    v_lshrrev_b32_e32 v16, 31, v1
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[0:1], 1, v[0:1]
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v11, v17, v27
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[2:3], 1, v[2:3]
+; GFX9-SDAG-NEXT:    v_lshrrev_b32_e32 v17, 31, v9
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v0, v0, v17
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v2, v2, v16
+; GFX9-SDAG-NEXT:    v_sub_co_u32_e32 v16, vcc, v22, v0
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v16, vcc, v23, v1, vcc
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v16, vcc, v24, v2, vcc
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v16, vcc, v25, v3, vcc
+; GFX9-SDAG-NEXT:    v_ashrrev_i32_e32 v26, 31, v16
+; GFX9-SDAG-NEXT:    v_and_b32_e32 v16, v26, v4
+; GFX9-SDAG-NEXT:    v_sub_co_u32_e32 v0, vcc, v0, v16
+; GFX9-SDAG-NEXT:    v_and_b32_e32 v16, v26, v5
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[8:9], 1, v[8:9]
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v16, vcc
+; GFX9-SDAG-NEXT:    v_and_b32_e32 v16, v26, v6
+; GFX9-SDAG-NEXT:    v_or3_b32 v8, v8, v12, v14
+; GFX9-SDAG-NEXT:    v_and_b32_e32 v12, v26, v7
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v2, vcc, v2, v16, vcc
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v3, vcc, v3, v12, vcc
+; GFX9-SDAG-NEXT:    v_add_co_u32_e32 v18, vcc, -1, v18
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v19, vcc, -1, v19, vcc
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v20, vcc, -1, v20, vcc
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v21, vcc, -1, v21, vcc
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v16, v18, v20
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v17, v19, v21
+; GFX9-SDAG-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[16:17]
+; GFX9-SDAG-NEXT:    v_and_b32_e32 v12, 1, v26
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v17, v13
+; GFX9-SDAG-NEXT:    v_or3_b32 v9, v9, 0, v15
+; GFX9-SDAG-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v16, v12
+; GFX9-SDAG-NEXT:    s_andn2_b64 exec, exec, s[4:5]
+; GFX9-SDAG-NEXT:    s_cbranch_execnz .LBB1_3
+; GFX9-SDAG-NEXT:  ; %bb.4: ; %Flow
+; GFX9-SDAG-NEXT:    s_or_b64 exec, exec, s[4:5]
+; GFX9-SDAG-NEXT:  .LBB1_5: ; %Flow2
+; GFX9-SDAG-NEXT:    s_or_b64 exec, exec, s[6:7]
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[0:1], 1, v[10:11]
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[2:3], 1, v[8:9]
+; GFX9-SDAG-NEXT:    v_lshrrev_b32_e32 v4, 31, v11
+; GFX9-SDAG-NEXT:    v_or3_b32 v8, v3, 0, v15
+; GFX9-SDAG-NEXT:    v_or3_b32 v9, v2, v4, v14
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v10, v13, v1
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v11, v12, v0
+; GFX9-SDAG-NEXT:  .LBB1_6: ; %Flow3
+; GFX9-SDAG-NEXT:    s_or_b64 exec, exec, s[8:9]
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v0, v11
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v1, v10
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v2, v9
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v3, v8
+; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-GISEL-LABEL: v_udiv_i128_vv:
+; GFX9-GISEL:       ; %bb.0: ; %_udiv-special-cases
+; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v8, v4, v6
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v9, v5, v7
+; GFX9-GISEL-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[8:9]
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v8, v0, v2
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v9, v1, v3
+; GFX9-GISEL-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[8:9]
+; GFX9-GISEL-NEXT:    v_ffbh_u32_e32 v9, v4
+; GFX9-GISEL-NEXT:    v_ffbh_u32_e32 v8, v5
+; GFX9-GISEL-NEXT:    v_add_u32_e32 v9, 32, v9
+; GFX9-GISEL-NEXT:    v_ffbh_u32_e32 v10, v6
+; GFX9-GISEL-NEXT:    v_min_u32_e32 v8, v8, v9
+; GFX9-GISEL-NEXT:    v_ffbh_u32_e32 v9, v7
+; GFX9-GISEL-NEXT:    v_add_u32_e32 v10, 32, v10
+; GFX9-GISEL-NEXT:    v_cmp_eq_u64_e64 s[6:7], 0, v[6:7]
+; GFX9-GISEL-NEXT:    v_add_u32_e32 v8, 64, v8
+; GFX9-GISEL-NEXT:    v_min_u32_e32 v9, v9, v10
+; GFX9-GISEL-NEXT:    v_ffbh_u32_e32 v10, v0
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v8, v9, v8, s[6:7]
+; GFX9-GISEL-NEXT:    v_ffbh_u32_e32 v9, v1
+; GFX9-GISEL-NEXT:    v_add_u32_e32 v10, 32, v10
+; GFX9-GISEL-NEXT:    v_ffbh_u32_e32 v11, v2
+; GFX9-GISEL-NEXT:    v_min_u32_e32 v9, v9, v10
+; GFX9-GISEL-NEXT:    v_ffbh_u32_e32 v10, v3
+; GFX9-GISEL-NEXT:    v_add_u32_e32 v11, 32, v11
+; GFX9-GISEL-NEXT:    v_cmp_eq_u64_e64 s[6:7], 0, v[2:3]
+; GFX9-GISEL-NEXT:    v_add_u32_e32 v9, 64, v9
+; GFX9-GISEL-NEXT:    v_min_u32_e32 v10, v10, v11
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v9, v10, v9, s[6:7]
+; GFX9-GISEL-NEXT:    v_sub_co_u32_e64 v12, s[6:7], v8, v9
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e64 v13, s[6:7], 0, 0, s[6:7]
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v8, 0x7f
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e64 v14, s[6:7], 0, 0, s[6:7]
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v9, 0
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e64 v15, s[6:7], 0, 0, s[6:7]
+; GFX9-GISEL-NEXT:    v_cmp_gt_u64_e64 s[6:7], v[12:13], v[8:9]
+; GFX9-GISEL-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[6:7]
+; GFX9-GISEL-NEXT:    v_cmp_lt_u64_e64 s[6:7], 0, v[14:15]
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v17, v13, v15
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[6:7]
+; GFX9-GISEL-NEXT:    v_cmp_eq_u64_e64 s[6:7], 0, v[14:15]
+; GFX9-GISEL-NEXT:    s_mov_b64 s[8:9], 0
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v8, v9, v8, s[6:7]
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v18, v9, v8
+; GFX9-GISEL-NEXT:    v_xor_b32_e32 v8, 0x7f, v12
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v16, v8, v14
+; GFX9-GISEL-NEXT:    v_and_b32_e32 v8, 1, v18
+; GFX9-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v10, v0, 0, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v11, v1, 0, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v8, v2, 0, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v9, v3, 0, vcc
+; GFX9-GISEL-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[16:17]
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v16, v18, v16
+; GFX9-GISEL-NEXT:    v_and_b32_e32 v16, 1, v16
+; GFX9-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v16
+; GFX9-GISEL-NEXT:    s_xor_b64 s[4:5], vcc, -1
+; GFX9-GISEL-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
+; GFX9-GISEL-NEXT:    s_cbranch_execz .LBB1_6
+; GFX9-GISEL-NEXT:  ; %bb.1: ; %udiv-bb1
+; GFX9-GISEL-NEXT:    v_add_co_u32_e32 v18, vcc, 1, v12
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v19, vcc, 0, v13, vcc
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v20, vcc, 0, v14, vcc
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v21, vcc, 0, v15, vcc
+; GFX9-GISEL-NEXT:    s_xor_b64 s[4:5], vcc, -1
+; GFX9-GISEL-NEXT:    v_sub_co_u32_e32 v16, vcc, 0x7f, v12
+; GFX9-GISEL-NEXT:    v_sub_u32_e32 v8, 64, v16
+; GFX9-GISEL-NEXT:    v_lshrrev_b64 v[8:9], v8, v[0:1]
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[10:11], v16, v[2:3]
+; GFX9-GISEL-NEXT:    v_subrev_u32_e32 v14, 64, v16
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[12:13], v16, v[0:1]
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v10, v8, v10
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v11, v9, v11
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[8:9], v14, v[0:1]
+; GFX9-GISEL-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v16
+; GFX9-GISEL-NEXT:    s_mov_b64 s[10:11], s[8:9]
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v14, 0, v12, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v15, 0, v13, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v8, v8, v10, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v9, v9, v11, vcc
+; GFX9-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v16
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v13, s11
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v8, v8, v2, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v9, v9, v3, vcc
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v11, s9
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v10, s8
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v12, s10
+; GFX9-GISEL-NEXT:    s_and_saveexec_b64 s[8:9], s[4:5]
+; GFX9-GISEL-NEXT:    s_xor_b64 s[12:13], exec, s[8:9]
+; GFX9-GISEL-NEXT:    s_cbranch_execz .LBB1_5
+; GFX9-GISEL-NEXT:  ; %bb.2: ; %udiv-preheader
+; GFX9-GISEL-NEXT:    v_sub_u32_e32 v12, 64, v18
+; GFX9-GISEL-NEXT:    v_subrev_u32_e32 v22, 64, v18
+; GFX9-GISEL-NEXT:    v_lshrrev_b64 v[10:11], v18, v[0:1]
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[12:13], v12, v[2:3]
+; GFX9-GISEL-NEXT:    v_lshrrev_b64 v[16:17], v18, v[2:3]
+; GFX9-GISEL-NEXT:    v_lshrrev_b64 v[2:3], v22, v[2:3]
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v10, v10, v12
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v11, v11, v13
+; GFX9-GISEL-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v18
+; GFX9-GISEL-NEXT:    s_mov_b64 s[8:9], 0
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v2, v2, v10, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v3, v3, v11, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v16, 0, v16, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v17, 0, v17, vcc
+; GFX9-GISEL-NEXT:    v_add_co_u32_e32 v22, vcc, -1, v4
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v23, vcc, -1, v5, vcc
+; GFX9-GISEL-NEXT:    s_mov_b64 s[10:11], s[8:9]
+; GFX9-GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v18
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v24, vcc, -1, v6, vcc
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v13, s11
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v2, v2, v0, s[4:5]
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v3, v3, v1, s[4:5]
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v25, vcc, -1, v7, vcc
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v1, 0
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v11, s9
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v10, s8
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v12, s10
+; GFX9-GISEL-NEXT:  .LBB1_3: ; %udiv-do-while
+; GFX9-GISEL-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[12:13], 1, v[14:15]
+; GFX9-GISEL-NEXT:    v_lshrrev_b32_e32 v0, 31, v15
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v14, v10, v12
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v15, v11, v13
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[12:13], 1, v[16:17]
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[10:11], 1, v[2:3]
+; GFX9-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 31, v3
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v12, v12, v2
+; GFX9-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 31, v9
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[8:9], 1, v[8:9]
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v2, v10, v2
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v8, v8, v0
+; GFX9-GISEL-NEXT:    v_sub_co_u32_e32 v0, vcc, v22, v2
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v0, vcc, v23, v11, vcc
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v0, vcc, v24, v12, vcc
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v0, vcc, v25, v13, vcc
+; GFX9-GISEL-NEXT:    v_add_co_u32_e64 v18, s[4:5], -1, v18
+; GFX9-GISEL-NEXT:    v_ashrrev_i32_e32 v3, 31, v0
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e64 v19, s[4:5], -1, v19, s[4:5]
+; GFX9-GISEL-NEXT:    v_and_b32_e32 v10, v3, v4
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e64 v20, s[4:5], -1, v20, s[4:5]
+; GFX9-GISEL-NEXT:    v_and_b32_e32 v16, v3, v5
+; GFX9-GISEL-NEXT:    v_sub_co_u32_e32 v2, vcc, v2, v10
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e64 v21, s[4:5], -1, v21, s[4:5]
+; GFX9-GISEL-NEXT:    v_and_b32_e32 v0, 1, v3
+; GFX9-GISEL-NEXT:    v_and_b32_e32 v17, v3, v6
+; GFX9-GISEL-NEXT:    v_and_b32_e32 v26, v3, v7
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v3, vcc, v11, v16, vcc
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v10, v18, v20
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v11, v19, v21
+; GFX9-GISEL-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[10:11]
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v16, vcc, v12, v17, vcc
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v11, v1
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v17, vcc, v13, v26, vcc
+; GFX9-GISEL-NEXT:    s_or_b64 s[8:9], s[4:5], s[8:9]
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v10, v0
+; GFX9-GISEL-NEXT:    s_andn2_b64 exec, exec, s[8:9]
+; GFX9-GISEL-NEXT:    s_cbranch_execnz .LBB1_3
+; GFX9-GISEL-NEXT:  ; %bb.4: ; %Flow
+; GFX9-GISEL-NEXT:    s_or_b64 exec, exec, s[8:9]
+; GFX9-GISEL-NEXT:  .LBB1_5: ; %Flow2
+; GFX9-GISEL-NEXT:    s_or_b64 exec, exec, s[12:13]
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[0:1], 1, v[14:15]
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[8:9], 1, v[8:9]
+; GFX9-GISEL-NEXT:    v_lshrrev_b32_e32 v2, 31, v15
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v8, v8, v2
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v10, v10, v0
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v11, v11, v1
+; GFX9-GISEL-NEXT:  .LBB1_6: ; %Flow3
+; GFX9-GISEL-NEXT:    s_or_b64 exec, exec, s[6:7]
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v0, v10
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v1, v11
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v2, v8
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v3, v9
+; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
+  %shl = udiv i128 %lhs, %rhs
+  ret i128 %shl
+}
+
+define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) {
+; GFX9-SDAG-LABEL: v_srem_i128_vv:
+; GFX9-SDAG:       ; %bb.0: ; %_udiv-special-cases
+; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT:    v_ashrrev_i32_e32 v20, 31, v3
+; GFX9-SDAG-NEXT:    v_xor_b32_e32 v0, v0, v20
+; GFX9-SDAG-NEXT:    v_xor_b32_e32 v10, v2, v20
+; GFX9-SDAG-NEXT:    v_xor_b32_e32 v1, v1, v20
+; GFX9-SDAG-NEXT:    v_sub_co_u32_e32 v2, vcc, v0, v20
+; GFX9-SDAG-NEXT:    v_xor_b32_e32 v9, v3, v20
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v3, vcc, v1, v20, vcc
+; GFX9-SDAG-NEXT:    v_ashrrev_i32_e32 v8, 31, v7
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v0, vcc, v10, v20, vcc
+; GFX9-SDAG-NEXT:    v_xor_b32_e32 v4, v4, v8
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v1, vcc, v9, v20, vcc
+; GFX9-SDAG-NEXT:    v_xor_b32_e32 v5, v5, v8
+; GFX9-SDAG-NEXT:    v_sub_co_u32_e32 v23, vcc, v4, v8
+; GFX9-SDAG-NEXT:    v_xor_b32_e32 v6, v6, v8
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v21, vcc, v5, v8, vcc
+; GFX9-SDAG-NEXT:    v_xor_b32_e32 v7, v7, v8
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v4, vcc, v6, v8, vcc
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v5, vcc, v7, v8, vcc
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v7, v21, v5
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v6, v23, v4
+; GFX9-SDAG-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[6:7]
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v7, v3, v1
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v6, v2, v0
+; GFX9-SDAG-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[6:7]
+; GFX9-SDAG-NEXT:    v_ffbh_u32_e32 v6, v4
+; GFX9-SDAG-NEXT:    v_add_u32_e32 v6, 32, v6
+; GFX9-SDAG-NEXT:    v_ffbh_u32_e32 v7, v5
+; GFX9-SDAG-NEXT:    v_min_u32_e32 v6, v6, v7
+; GFX9-SDAG-NEXT:    v_ffbh_u32_e32 v7, v23
+; GFX9-SDAG-NEXT:    v_add_u32_e32 v7, 32, v7
+; GFX9-SDAG-NEXT:    v_ffbh_u32_e32 v8, v21
+; GFX9-SDAG-NEXT:    v_min_u32_e32 v7, v7, v8
+; GFX9-SDAG-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
+; GFX9-SDAG-NEXT:    v_add_co_u32_e32 v7, vcc, 64, v7
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e64 v8, s[6:7], 0, 0, vcc
+; GFX9-SDAG-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[4:5]
+; GFX9-SDAG-NEXT:    v_ffbh_u32_e32 v9, v1
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc
+; GFX9-SDAG-NEXT:    v_ffbh_u32_e32 v7, v0
+; GFX9-SDAG-NEXT:    v_add_u32_e32 v7, 32, v7
+; GFX9-SDAG-NEXT:    v_min_u32_e32 v7, v7, v9
+; GFX9-SDAG-NEXT:    v_ffbh_u32_e32 v9, v2
+; GFX9-SDAG-NEXT:    v_add_u32_e32 v9, 32, v9
+; GFX9-SDAG-NEXT:    v_ffbh_u32_e32 v10, v3
+; GFX9-SDAG-NEXT:    v_min_u32_e32 v9, v9, v10
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v8, v8, 0, vcc
+; GFX9-SDAG-NEXT:    v_add_co_u32_e32 v9, vcc, 64, v9
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e64 v10, s[6:7], 0, 0, vcc
+; GFX9-SDAG-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[0:1]
+; GFX9-SDAG-NEXT:    s_mov_b64 s[6:7], 0x7f
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v7, v9, v7, vcc
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v10, v10, 0, vcc
+; GFX9-SDAG-NEXT:    v_sub_co_u32_e32 v6, vcc, v6, v7
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v7, vcc, v8, v10, vcc
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v9, 0
+; GFX9-SDAG-NEXT:    v_subbrev_co_u32_e32 v8, vcc, 0, v9, vcc
+; GFX9-SDAG-NEXT:    v_subbrev_co_u32_e32 v9, vcc, 0, v9, vcc
+; GFX9-SDAG-NEXT:    v_cmp_lt_u64_e32 vcc, s[6:7], v[6:7]
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v13, v7, v9
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GFX9-SDAG-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[8:9]
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v22, v20
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GFX9-SDAG-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[8:9]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v10, v11, v10, vcc
+; GFX9-SDAG-NEXT:    v_and_b32_e32 v10, 1, v10
+; GFX9-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v10
+; GFX9-SDAG-NEXT:    v_xor_b32_e32 v10, 0x7f, v6
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v12, v10, v8
+; GFX9-SDAG-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
+; GFX9-SDAG-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[12:13]
+; GFX9-SDAG-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v11, v1, 0, s[4:5]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v12, v0, 0, s[4:5]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v10, v3, 0, s[4:5]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v13, v2, 0, s[4:5]
+; GFX9-SDAG-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
+; GFX9-SDAG-NEXT:    s_and_saveexec_b64 s[8:9], s[4:5]
+; GFX9-SDAG-NEXT:    s_cbranch_execz .LBB2_6
+; GFX9-SDAG-NEXT:  ; %bb.1: ; %udiv-bb1
+; GFX9-SDAG-NEXT:    v_add_co_u32_e32 v24, vcc, 1, v6
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v25, vcc, 0, v7, vcc
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v26, vcc, 0, v8, vcc
+; GFX9-SDAG-NEXT:    v_sub_u32_e32 v13, 0x7f, v6
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v27, vcc, 0, v9, vcc
+; GFX9-SDAG-NEXT:    v_sub_u32_e32 v11, 64, v13
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v8, v25, v27
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v7, v24, v26
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[9:10], v13, v[0:1]
+; GFX9-SDAG-NEXT:    v_lshrrev_b64 v[11:12], v11, v[2:3]
+; GFX9-SDAG-NEXT:    v_sub_u32_e32 v6, 63, v6
+; GFX9-SDAG-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[7:8]
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[6:7], v6, v[2:3]
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v8, v10, v12
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v9, v9, v11
+; GFX9-SDAG-NEXT:    v_cmp_gt_u32_e64 s[4:5], 64, v13
+; GFX9-SDAG-NEXT:    v_cmp_eq_u32_e64 s[6:7], 0, v13
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[12:13], v13, v[2:3]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[4:5]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v6, v6, v9, s[4:5]
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v8, 0
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v10, 0
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v7, v7, v1, s[6:7]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v6, v6, v0, s[6:7]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v13, 0, v13, s[4:5]
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v9, 0
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v11, 0
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v12, 0, v12, s[4:5]
+; GFX9-SDAG-NEXT:    s_and_saveexec_b64 s[4:5], vcc
+; GFX9-SDAG-NEXT:    s_xor_b64 s[6:7], exec, s[4:5]
+; GFX9-SDAG-NEXT:    s_cbranch_execz .LBB2_5
+; GFX9-SDAG-NEXT:  ; %bb.2: ; %udiv-preheader
+; GFX9-SDAG-NEXT:    v_sub_u32_e32 v10, 64, v24
+; GFX9-SDAG-NEXT:    v_lshrrev_b64 v[8:9], v24, v[2:3]
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[10:11], v10, v[0:1]
+; GFX9-SDAG-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v24
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v10, v8, v10
+; GFX9-SDAG-NEXT:    v_subrev_u32_e32 v8, 64, v24
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v11, v9, v11
+; GFX9-SDAG-NEXT:    v_lshrrev_b64 v[8:9], v8, v[0:1]
+; GFX9-SDAG-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v24
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v9, v9, v11, vcc
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v15, v9, v3, s[4:5]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v10, v8, v10, vcc
+; GFX9-SDAG-NEXT:    v_lshrrev_b64 v[8:9], v24, v[0:1]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v14, v10, v2, s[4:5]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v17, 0, v9, vcc
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v16, 0, v8, vcc
+; GFX9-SDAG-NEXT:    v_add_co_u32_e32 v28, vcc, -1, v23
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v29, vcc, -1, v21, vcc
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v30, vcc, -1, v4, vcc
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v18, 0
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v10, 0
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v31, vcc, -1, v5, vcc
+; GFX9-SDAG-NEXT:    s_mov_b64 s[4:5], 0
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v19, 0
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v11, 0
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v9, 0
+; GFX9-SDAG-NEXT:  .LBB2_3: ; %udiv-do-while
+; GFX9-SDAG-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX9-SDAG-NEXT:    v_lshrrev_b32_e32 v32, 31, v15
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[14:15], 1, v[14:15]
+; GFX9-SDAG-NEXT:    v_lshrrev_b32_e32 v33, 31, v7
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[6:7], 1, v[6:7]
+; GFX9-SDAG-NEXT:    v_lshrrev_b32_e32 v8, 31, v13
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[16:17], 1, v[16:17]
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v14, v14, v33
+; GFX9-SDAG-NEXT:    v_or3_b32 v6, v6, v8, v10
+; GFX9-SDAG-NEXT:    v_sub_co_u32_e32 v8, vcc, v28, v14
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v16, v16, v32
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v8, vcc, v29, v15, vcc
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v8, vcc, v30, v16, vcc
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[12:13], 1, v[12:13]
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v8, vcc, v31, v17, vcc
+; GFX9-SDAG-NEXT:    v_ashrrev_i32_e32 v8, 31, v8
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v12, v18, v12
+; GFX9-SDAG-NEXT:    v_and_b32_e32 v18, v8, v23
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v13, v19, v13
+; GFX9-SDAG-NEXT:    v_and_b32_e32 v19, v8, v21
+; GFX9-SDAG-NEXT:    v_sub_co_u32_e32 v14, vcc, v14, v18
+; GFX9-SDAG-NEXT:    v_and_b32_e32 v32, v8, v4
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v15, vcc, v15, v19, vcc
+; GFX9-SDAG-NEXT:    v_and_b32_e32 v33, v8, v5
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v16, vcc, v16, v32, vcc
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v17, vcc, v17, v33, vcc
+; GFX9-SDAG-NEXT:    v_add_co_u32_e32 v24, vcc, -1, v24
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v25, vcc, -1, v25, vcc
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v26, vcc, -1, v26, vcc
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v27, vcc, -1, v27, vcc
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v18, v24, v26
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v19, v25, v27
+; GFX9-SDAG-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[18:19]
+; GFX9-SDAG-NEXT:    v_and_b32_e32 v8, 1, v8
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v19, v9
+; GFX9-SDAG-NEXT:    v_or3_b32 v7, v7, 0, v11
+; GFX9-SDAG-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v18, v8
+; GFX9-SDAG-NEXT:    s_andn2_b64 exec, exec, s[4:5]
+; GFX9-SDAG-NEXT:    s_cbranch_execnz .LBB2_3
+; GFX9-SDAG-NEXT:  ; %bb.4: ; %Flow
+; GFX9-SDAG-NEXT:    s_or_b64 exec, exec, s[4:5]
+; GFX9-SDAG-NEXT:  .LBB2_5: ; %Flow2
+; GFX9-SDAG-NEXT:    s_or_b64 exec, exec, s[6:7]
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[14:15], 1, v[12:13]
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[6:7], 1, v[6:7]
+; GFX9-SDAG-NEXT:    v_lshrrev_b32_e32 v12, 31, v13
+; GFX9-SDAG-NEXT:    v_or3_b32 v11, v7, 0, v11
+; GFX9-SDAG-NEXT:    v_or3_b32 v12, v6, v12, v10
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v10, v9, v15
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v13, v8, v14
+; GFX9-SDAG-NEXT:  .LBB2_6: ; %Flow3
+; GFX9-SDAG-NEXT:    s_or_b64 exec, exec, s[8:9]
+; GFX9-SDAG-NEXT:    v_mul_lo_u32 v16, v13, v5
+; GFX9-SDAG-NEXT:    v_mad_u64_u32 v[5:6], s[4:5], v23, v13, 0
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v15, 0
+; GFX9-SDAG-NEXT:    v_mad_u64_u32 v[7:8], s[4:5], v13, v4, 0
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v14, v6
+; GFX9-SDAG-NEXT:    v_mad_u64_u32 v[13:14], s[4:5], v21, v13, v[14:15]
+; GFX9-SDAG-NEXT:    v_mul_lo_u32 v9, v10, v4
+; GFX9-SDAG-NEXT:    v_mul_lo_u32 v11, v11, v23
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v4, v14
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v14, v15
+; GFX9-SDAG-NEXT:    v_mad_u64_u32 v[13:14], s[4:5], v23, v10, v[13:14]
+; GFX9-SDAG-NEXT:    v_add3_u32 v8, v8, v16, v9
+; GFX9-SDAG-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], v12, v23, v[7:8]
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v8, v14
+; GFX9-SDAG-NEXT:    v_add_co_u32_e32 v8, vcc, v4, v8
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e64 v9, s[4:5], 0, 0, vcc
+; GFX9-SDAG-NEXT:    v_mul_lo_u32 v12, v12, v21
+; GFX9-SDAG-NEXT:    v_mad_u64_u32 v[8:9], s[4:5], v21, v10, v[8:9]
+; GFX9-SDAG-NEXT:    v_add3_u32 v4, v11, v7, v12
+; GFX9-SDAG-NEXT:    v_add_co_u32_e32 v6, vcc, v8, v6
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v4, vcc, v9, v4, vcc
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v7, v13
+; GFX9-SDAG-NEXT:    v_sub_co_u32_e32 v2, vcc, v2, v5
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v3, vcc, v3, v7, vcc
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v0, vcc, v0, v6, vcc
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v4, vcc
+; GFX9-SDAG-NEXT:    v_xor_b32_e32 v5, v0, v20
+; GFX9-SDAG-NEXT:    v_xor_b32_e32 v0, v2, v20
+; GFX9-SDAG-NEXT:    v_xor_b32_e32 v4, v1, v22
+; GFX9-SDAG-NEXT:    v_xor_b32_e32 v1, v3, v22
+; GFX9-SDAG-NEXT:    v_sub_co_u32_e32 v0, vcc, v0, v20
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v22, vcc
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v2, vcc, v5, v20, vcc
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v3, vcc, v4, v22, vcc
+; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-GISEL-LABEL: v_srem_i128_vv:
+; GFX9-GISEL:       ; %bb.0: ; %_udiv-special-cases
+; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT:    v_ashrrev_i32_e32 v20, 31, v3
+; GFX9-GISEL-NEXT:    v_ashrrev_i32_e32 v9, 31, v7
+; GFX9-GISEL-NEXT:    v_xor_b32_e32 v0, v0, v20
+; GFX9-GISEL-NEXT:    v_xor_b32_e32 v1, v1, v20
+; GFX9-GISEL-NEXT:    v_xor_b32_e32 v11, v6, v9
+; GFX9-GISEL-NEXT:    v_sub_co_u32_e32 v6, vcc, v0, v20
+; GFX9-GISEL-NEXT:    v_xor_b32_e32 v2, v2, v20
+; GFX9-GISEL-NEXT:    v_xor_b32_e32 v12, v7, v9
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v7, vcc, v1, v20, vcc
+; GFX9-GISEL-NEXT:    v_xor_b32_e32 v3, v3, v20
+; GFX9-GISEL-NEXT:    v_xor_b32_e32 v8, v4, v9
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v4, vcc, v2, v20, vcc
+; GFX9-GISEL-NEXT:    v_xor_b32_e32 v10, v5, v9
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v5, vcc, v3, v20, vcc
+; GFX9-GISEL-NEXT:    v_sub_co_u32_e32 v21, vcc, v8, v9
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v22, vcc, v10, v9, vcc
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v8, vcc, v11, v9, vcc
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v9, vcc, v12, v9, vcc
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v0, v21, v8
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v1, v22, v9
+; GFX9-GISEL-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[0:1]
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v0, v6, v4
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v1, v7, v5
+; GFX9-GISEL-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
+; GFX9-GISEL-NEXT:    v_ffbh_u32_e32 v1, v21
+; GFX9-GISEL-NEXT:    v_ffbh_u32_e32 v0, v22
+; GFX9-GISEL-NEXT:    v_add_u32_e32 v1, 32, v1
+; GFX9-GISEL-NEXT:    v_ffbh_u32_e32 v2, v8
+; GFX9-GISEL-NEXT:    v_min_u32_e32 v0, v0, v1
+; GFX9-GISEL-NEXT:    v_ffbh_u32_e32 v1, v9
+; GFX9-GISEL-NEXT:    v_add_u32_e32 v2, 32, v2
+; GFX9-GISEL-NEXT:    v_cmp_eq_u64_e64 s[6:7], 0, v[8:9]
+; GFX9-GISEL-NEXT:    v_add_u32_e32 v0, 64, v0
+; GFX9-GISEL-NEXT:    v_min_u32_e32 v1, v1, v2
+; GFX9-GISEL-NEXT:    v_ffbh_u32_e32 v2, v6
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v0, v1, v0, s[6:7]
+; GFX9-GISEL-NEXT:    v_ffbh_u32_e32 v1, v7
+; GFX9-GISEL-NEXT:    v_add_u32_e32 v2, 32, v2
+; GFX9-GISEL-NEXT:    v_ffbh_u32_e32 v3, v4
+; GFX9-GISEL-NEXT:    v_min_u32_e32 v1, v1, v2
+; GFX9-GISEL-NEXT:    v_ffbh_u32_e32 v2, v5
+; GFX9-GISEL-NEXT:    v_add_u32_e32 v3, 32, v3
+; GFX9-GISEL-NEXT:    v_cmp_eq_u64_e64 s[6:7], 0, v[4:5]
+; GFX9-GISEL-NEXT:    v_add_u32_e32 v1, 64, v1
+; GFX9-GISEL-NEXT:    v_min_u32_e32 v2, v2, v3
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v1, v2, v1, s[6:7]
+; GFX9-GISEL-NEXT:    v_sub_co_u32_e64 v0, s[6:7], v0, v1
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e64 v1, s[6:7], 0, 0, s[6:7]
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v2, 0x7f
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e64 v10, s[6:7], 0, 0, s[6:7]
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v3, 0
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e64 v11, s[6:7], 0, 0, s[6:7]
+; GFX9-GISEL-NEXT:    v_cmp_gt_u64_e64 s[6:7], v[0:1], v[2:3]
+; GFX9-GISEL-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s[6:7]
+; GFX9-GISEL-NEXT:    v_cmp_lt_u64_e64 s[6:7], 0, v[10:11]
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v15, v1, v11
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v3, 0, 1, s[6:7]
+; GFX9-GISEL-NEXT:    v_cmp_eq_u64_e64 s[6:7], 0, v[10:11]
+; GFX9-GISEL-NEXT:    s_mov_b64 s[8:9], 0
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v2, v3, v2, s[6:7]
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v3, 0, 1, s[4:5]
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v16, v3, v2
+; GFX9-GISEL-NEXT:    v_xor_b32_e32 v2, 0x7f, v0
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v14, v2, v10
+; GFX9-GISEL-NEXT:    v_and_b32_e32 v2, 1, v16
+; GFX9-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v12, v6, 0, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v13, v7, 0, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v2, v4, 0, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v3, v5, 0, vcc
+; GFX9-GISEL-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[14:15]
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v14, v16, v14
+; GFX9-GISEL-NEXT:    v_and_b32_e32 v14, 1, v14
+; GFX9-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v14
+; GFX9-GISEL-NEXT:    s_xor_b64 s[4:5], vcc, -1
+; GFX9-GISEL-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
+; GFX9-GISEL-NEXT:    s_cbranch_execz .LBB2_6
+; GFX9-GISEL-NEXT:  ; %bb.1: ; %udiv-bb1
+; GFX9-GISEL-NEXT:    v_add_co_u32_e32 v23, vcc, 1, v0
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v24, vcc, 0, v1, vcc
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v25, vcc, 0, v10, vcc
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v26, vcc, 0, v11, vcc
+; GFX9-GISEL-NEXT:    s_xor_b64 s[4:5], vcc, -1
+; GFX9-GISEL-NEXT:    v_sub_co_u32_e32 v12, vcc, 0x7f, v0
+; GFX9-GISEL-NEXT:    v_sub_u32_e32 v0, 64, v12
+; GFX9-GISEL-NEXT:    v_lshrrev_b64 v[0:1], v0, v[6:7]
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[2:3], v12, v[4:5]
+; GFX9-GISEL-NEXT:    v_subrev_u32_e32 v13, 64, v12
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[10:11], v12, v[6:7]
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v2, v0, v2
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v3, v1, v3
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[0:1], v13, v[6:7]
+; GFX9-GISEL-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v12
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v10, 0, v10, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v11, 0, v11, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX9-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v12
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v12, v0, v4, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v13, v1, v5, vcc
+; GFX9-GISEL-NEXT:    s_mov_b64 s[10:11], s[8:9]
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v0, s8
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v1, s9
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v2, s10
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v3, s11
+; GFX9-GISEL-NEXT:    s_and_saveexec_b64 s[8:9], s[4:5]
+; GFX9-GISEL-NEXT:    s_xor_b64 s[12:13], exec, s[8:9]
+; GFX9-GISEL-NEXT:    s_cbranch_execz .LBB2_5
+; GFX9-GISEL-NEXT:  ; %bb.2: ; %udiv-preheader
+; GFX9-GISEL-NEXT:    v_sub_u32_e32 v2, 64, v23
+; GFX9-GISEL-NEXT:    v_lshrrev_b64 v[0:1], v23, v[6:7]
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[2:3], v2, v[4:5]
+; GFX9-GISEL-NEXT:    v_subrev_u32_e32 v16, 64, v23
+; GFX9-GISEL-NEXT:    v_lshrrev_b64 v[14:15], v23, v[4:5]
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v2, v0, v2
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v3, v1, v3
+; GFX9-GISEL-NEXT:    v_lshrrev_b64 v[0:1], v16, v[4:5]
+; GFX9-GISEL-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v23
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v18, 0, v14, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v19, 0, v15, vcc
+; GFX9-GISEL-NEXT:    v_add_co_u32_e32 v27, vcc, -1, v21
+; GFX9-GISEL-NEXT:    s_mov_b64 s[8:9], 0
+; GFX9-GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v23
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v28, vcc, -1, v22, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v16, v0, v6, s[4:5]
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v17, v1, v7, s[4:5]
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v29, vcc, -1, v8, vcc
+; GFX9-GISEL-NEXT:    s_mov_b64 s[10:11], s[8:9]
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v0, s8
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v30, vcc, -1, v9, vcc
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v15, 0
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v1, s9
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v2, s10
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v3, s11
+; GFX9-GISEL-NEXT:  .LBB2_3: ; %udiv-do-while
+; GFX9-GISEL-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[2:3], 1, v[10:11]
+; GFX9-GISEL-NEXT:    v_lshrrev_b32_e32 v14, 31, v11
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v10, v0, v2
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v11, v1, v3
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[2:3], 1, v[16:17]
+; GFX9-GISEL-NEXT:    v_lshrrev_b32_e32 v16, 31, v13
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[0:1], 1, v[18:19]
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v2, v2, v16
+; GFX9-GISEL-NEXT:    v_lshrrev_b32_e32 v18, 31, v17
+; GFX9-GISEL-NEXT:    v_sub_co_u32_e32 v16, vcc, v27, v2
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v0, v0, v18
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v16, vcc, v28, v3, vcc
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v16, vcc, v29, v0, vcc
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v16, vcc, v30, v1, vcc
+; GFX9-GISEL-NEXT:    v_ashrrev_i32_e32 v31, 31, v16
+; GFX9-GISEL-NEXT:    v_and_b32_e32 v16, v31, v21
+; GFX9-GISEL-NEXT:    v_sub_co_u32_e32 v16, vcc, v2, v16
+; GFX9-GISEL-NEXT:    v_and_b32_e32 v2, v31, v22
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v17, vcc, v3, v2, vcc
+; GFX9-GISEL-NEXT:    v_and_b32_e32 v2, v31, v8
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v18, vcc, v0, v2, vcc
+; GFX9-GISEL-NEXT:    v_and_b32_e32 v0, v31, v9
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v19, vcc, v1, v0, vcc
+; GFX9-GISEL-NEXT:    v_add_co_u32_e32 v23, vcc, -1, v23
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v24, vcc, -1, v24, vcc
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v25, vcc, -1, v25, vcc
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v26, vcc, -1, v26, vcc
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[12:13], 1, v[12:13]
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v0, v23, v25
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v1, v24, v26
+; GFX9-GISEL-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[0:1]
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v12, v12, v14
+; GFX9-GISEL-NEXT:    v_and_b32_e32 v14, 1, v31
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v0, v14
+; GFX9-GISEL-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v1, v15
+; GFX9-GISEL-NEXT:    s_andn2_b64 exec, exec, s[8:9]
+; GFX9-GISEL-NEXT:    s_cbranch_execnz .LBB2_3
+; GFX9-GISEL-NEXT:  ; %bb.4: ; %Flow
+; GFX9-GISEL-NEXT:    s_or_b64 exec, exec, s[8:9]
+; GFX9-GISEL-NEXT:  .LBB2_5: ; %Flow2
+; GFX9-GISEL-NEXT:    s_or_b64 exec, exec, s[12:13]
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[14:15], 1, v[10:11]
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[2:3], 1, v[12:13]
+; GFX9-GISEL-NEXT:    v_lshrrev_b32_e32 v10, 31, v11
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v2, v2, v10
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v12, v0, v14
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v13, v1, v15
+; GFX9-GISEL-NEXT:  .LBB2_6: ; %Flow3
+; GFX9-GISEL-NEXT:    s_or_b64 exec, exec, s[6:7]
+; GFX9-GISEL-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], v21, v2, 0
+; GFX9-GISEL-NEXT:    v_mad_u64_u32 v[10:11], s[4:5], v21, v12, 0
+; GFX9-GISEL-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], v22, v13, v[0:1]
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v14, v11
+; GFX9-GISEL-NEXT:    v_mul_lo_u32 v16, v22, v2
+; GFX9-GISEL-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], v8, v12, v[0:1]
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v15, v0
+; GFX9-GISEL-NEXT:    v_mad_u64_u32 v[14:15], vcc, v21, v13, v[14:15]
+; GFX9-GISEL-NEXT:    v_mul_lo_u32 v0, v21, v3
+; GFX9-GISEL-NEXT:    v_mad_u64_u32 v[2:3], s[4:5], v22, v12, v[14:15]
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e64 v0, s[4:5], v1, v0, s[4:5]
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v0, vcc, v0, v16, vcc
+; GFX9-GISEL-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], v8, v13, v[0:1]
+; GFX9-GISEL-NEXT:    v_mad_u64_u32 v[0:1], s[4:5], v9, v12, v[0:1]
+; GFX9-GISEL-NEXT:    v_sub_co_u32_e32 v1, vcc, v6, v10
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v2, vcc, v7, v2, vcc
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v3, vcc, v4, v3, vcc
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v0, vcc, v5, v0, vcc
+; GFX9-GISEL-NEXT:    v_xor_b32_e32 v1, v1, v20
+; GFX9-GISEL-NEXT:    v_xor_b32_e32 v2, v2, v20
+; GFX9-GISEL-NEXT:    v_xor_b32_e32 v4, v0, v20
+; GFX9-GISEL-NEXT:    v_sub_co_u32_e32 v0, vcc, v1, v20
+; GFX9-GISEL-NEXT:    v_xor_b32_e32 v3, v3, v20
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v1, vcc, v2, v20, vcc
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v2, vcc, v3, v20, vcc
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v3, vcc, v4, v20, vcc
+; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
+  %shl = srem i128 %lhs, %rhs
+  ret i128 %shl
+}
+
+define i128 @v_urem_i128_vv(i128 %lhs, i128 %rhs) {
+; GFX9-SDAG-LABEL: v_urem_i128_vv:
+; GFX9-SDAG:       ; %bb.0: ; %_udiv-special-cases
+; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v9, v5, v7
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v8, v4, v6
+; GFX9-SDAG-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[8:9]
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v9, v1, v3
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v8, v0, v2
+; GFX9-SDAG-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[8:9]
+; GFX9-SDAG-NEXT:    v_ffbh_u32_e32 v8, v6
+; GFX9-SDAG-NEXT:    v_add_u32_e32 v8, 32, v8
+; GFX9-SDAG-NEXT:    v_ffbh_u32_e32 v9, v7
+; GFX9-SDAG-NEXT:    v_min_u32_e32 v8, v8, v9
+; GFX9-SDAG-NEXT:    v_ffbh_u32_e32 v9, v4
+; GFX9-SDAG-NEXT:    v_add_u32_e32 v9, 32, v9
+; GFX9-SDAG-NEXT:    v_ffbh_u32_e32 v10, v5
+; GFX9-SDAG-NEXT:    v_min_u32_e32 v9, v9, v10
+; GFX9-SDAG-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
+; GFX9-SDAG-NEXT:    v_add_co_u32_e32 v9, vcc, 64, v9
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e64 v10, s[6:7], 0, 0, vcc
+; GFX9-SDAG-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[6:7]
+; GFX9-SDAG-NEXT:    v_ffbh_u32_e32 v11, v3
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v8, v9, v8, vcc
+; GFX9-SDAG-NEXT:    v_ffbh_u32_e32 v9, v2
+; GFX9-SDAG-NEXT:    v_add_u32_e32 v9, 32, v9
+; GFX9-SDAG-NEXT:    v_min_u32_e32 v9, v9, v11
+; GFX9-SDAG-NEXT:    v_ffbh_u32_e32 v11, v0
+; GFX9-SDAG-NEXT:    v_add_u32_e32 v11, 32, v11
+; GFX9-SDAG-NEXT:    v_ffbh_u32_e32 v12, v1
+; GFX9-SDAG-NEXT:    v_min_u32_e32 v11, v11, v12
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v10, v10, 0, vcc
+; GFX9-SDAG-NEXT:    v_add_co_u32_e32 v11, vcc, 64, v11
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e64 v12, s[6:7], 0, 0, vcc
+; GFX9-SDAG-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[2:3]
+; GFX9-SDAG-NEXT:    s_mov_b64 s[6:7], 0x7f
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v9, v11, v9, vcc
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v12, v12, 0, vcc
+; GFX9-SDAG-NEXT:    v_sub_co_u32_e32 v8, vcc, v8, v9
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v9, vcc, v10, v12, vcc
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v11, 0
+; GFX9-SDAG-NEXT:    v_subbrev_co_u32_e32 v10, vcc, 0, v11, vcc
+; GFX9-SDAG-NEXT:    v_subbrev_co_u32_e32 v11, vcc, 0, v11, vcc
+; GFX9-SDAG-NEXT:    v_cmp_lt_u64_e32 vcc, s[6:7], v[8:9]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; GFX9-SDAG-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[10:11]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; GFX9-SDAG-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[10:11]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v12, v13, v12, vcc
+; GFX9-SDAG-NEXT:    v_and_b32_e32 v12, 1, v12
+; GFX9-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v12
+; GFX9-SDAG-NEXT:    v_xor_b32_e32 v12, 0x7f, v8
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v13, v9, v11
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v12, v12, v10
+; GFX9-SDAG-NEXT:    s_or_b64 s[4:5], s[4:5], vcc
+; GFX9-SDAG-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[12:13]
+; GFX9-SDAG-NEXT:    s_xor_b64 s[6:7], s[4:5], -1
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v15, v3, 0, s[4:5]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v14, v2, 0, s[4:5]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v13, v1, 0, s[4:5]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v12, v0, 0, s[4:5]
+; GFX9-SDAG-NEXT:    s_and_b64 s[4:5], s[6:7], vcc
+; GFX9-SDAG-NEXT:    s_and_saveexec_b64 s[8:9], s[4:5]
+; GFX9-SDAG-NEXT:    s_cbranch_execz .LBB3_6
+; GFX9-SDAG-NEXT:  ; %bb.1: ; %udiv-bb1
+; GFX9-SDAG-NEXT:    v_add_co_u32_e32 v22, vcc, 1, v8
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v23, vcc, 0, v9, vcc
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v24, vcc, 0, v10, vcc
+; GFX9-SDAG-NEXT:    v_sub_u32_e32 v15, 0x7f, v8
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v25, vcc, 0, v11, vcc
+; GFX9-SDAG-NEXT:    v_sub_u32_e32 v13, 64, v15
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v10, v23, v25
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v9, v22, v24
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[11:12], v15, v[2:3]
+; GFX9-SDAG-NEXT:    v_lshrrev_b64 v[13:14], v13, v[0:1]
+; GFX9-SDAG-NEXT:    v_sub_u32_e32 v8, 63, v8
+; GFX9-SDAG-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[9:10]
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[8:9], v8, v[0:1]
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v10, v12, v14
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v11, v11, v13
+; GFX9-SDAG-NEXT:    v_cmp_gt_u32_e64 s[4:5], 64, v15
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v9, v9, v10, s[4:5]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v8, v8, v11, s[4:5]
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[10:11], v15, v[0:1]
+; GFX9-SDAG-NEXT:    v_cmp_eq_u32_e64 s[6:7], 0, v15
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v12, 0
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v14, 0
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v9, v9, v3, s[6:7]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v8, v8, v2, s[6:7]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v11, 0, v11, s[4:5]
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v13, 0
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v15, 0
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v10, 0, v10, s[4:5]
+; GFX9-SDAG-NEXT:    s_and_saveexec_b64 s[4:5], vcc
+; GFX9-SDAG-NEXT:    s_xor_b64 s[6:7], exec, s[4:5]
+; GFX9-SDAG-NEXT:    s_cbranch_execz .LBB3_5
+; GFX9-SDAG-NEXT:  ; %bb.2: ; %udiv-preheader
+; GFX9-SDAG-NEXT:    v_sub_u32_e32 v14, 64, v22
+; GFX9-SDAG-NEXT:    v_lshrrev_b64 v[12:13], v22, v[0:1]
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[14:15], v14, v[2:3]
+; GFX9-SDAG-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v22
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v14, v12, v14
+; GFX9-SDAG-NEXT:    v_subrev_u32_e32 v12, 64, v22
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v15, v13, v15
+; GFX9-SDAG-NEXT:    v_lshrrev_b64 v[12:13], v12, v[2:3]
+; GFX9-SDAG-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v22
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v13, v13, v15, vcc
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v17, v13, v1, s[4:5]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v14, v12, v14, vcc
+; GFX9-SDAG-NEXT:    v_lshrrev_b64 v[12:13], v22, v[2:3]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e64 v16, v14, v0, s[4:5]
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v19, 0, v13, vcc
+; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v18, 0, v12, vcc
+; GFX9-SDAG-NEXT:    v_add_co_u32_e32 v26, vcc, -1, v4
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v27, vcc, -1, v5, vcc
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v28, vcc, -1, v6, vcc
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v20, 0
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v14, 0
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v29, vcc, -1, v7, vcc
+; GFX9-SDAG-NEXT:    s_mov_b64 s[4:5], 0
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v21, 0
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v15, 0
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v13, 0
+; GFX9-SDAG-NEXT:  .LBB3_3: ; %udiv-do-while
+; GFX9-SDAG-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX9-SDAG-NEXT:    v_lshrrev_b32_e32 v12, 31, v11
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[10:11], 1, v[10:11]
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[18:19], 1, v[18:19]
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v10, v20, v10
+; GFX9-SDAG-NEXT:    v_lshrrev_b32_e32 v20, 31, v17
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[16:17], 1, v[16:17]
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v18, v18, v20
+; GFX9-SDAG-NEXT:    v_lshrrev_b32_e32 v20, 31, v9
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v16, v16, v20
+; GFX9-SDAG-NEXT:    v_sub_co_u32_e32 v20, vcc, v26, v16
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v20, vcc, v27, v17, vcc
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v20, vcc, v28, v18, vcc
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v20, vcc, v29, v19, vcc
+; GFX9-SDAG-NEXT:    v_ashrrev_i32_e32 v30, 31, v20
+; GFX9-SDAG-NEXT:    v_and_b32_e32 v20, v30, v4
+; GFX9-SDAG-NEXT:    v_sub_co_u32_e32 v16, vcc, v16, v20
+; GFX9-SDAG-NEXT:    v_and_b32_e32 v20, v30, v5
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v17, vcc, v17, v20, vcc
+; GFX9-SDAG-NEXT:    v_and_b32_e32 v20, v30, v6
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v18, vcc, v18, v20, vcc
+; GFX9-SDAG-NEXT:    v_and_b32_e32 v20, v30, v7
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v19, vcc, v19, v20, vcc
+; GFX9-SDAG-NEXT:    v_add_co_u32_e32 v22, vcc, -1, v22
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v23, vcc, -1, v23, vcc
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v24, vcc, -1, v24, vcc
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v25, vcc, -1, v25, vcc
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v11, v21, v11
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[8:9], 1, v[8:9]
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v20, v22, v24
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v21, v23, v25
+; GFX9-SDAG-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[20:21]
+; GFX9-SDAG-NEXT:    v_or3_b32 v8, v8, v12, v14
+; GFX9-SDAG-NEXT:    v_and_b32_e32 v12, 1, v30
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v21, v13
+; GFX9-SDAG-NEXT:    v_or3_b32 v9, v9, 0, v15
+; GFX9-SDAG-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v20, v12
+; GFX9-SDAG-NEXT:    s_andn2_b64 exec, exec, s[4:5]
+; GFX9-SDAG-NEXT:    s_cbranch_execnz .LBB3_3
+; GFX9-SDAG-NEXT:  ; %bb.4: ; %Flow
+; GFX9-SDAG-NEXT:    s_or_b64 exec, exec, s[4:5]
+; GFX9-SDAG-NEXT:  .LBB3_5: ; %Flow2
+; GFX9-SDAG-NEXT:    s_or_b64 exec, exec, s[6:7]
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[16:17], 1, v[10:11]
+; GFX9-SDAG-NEXT:    v_lshlrev_b64 v[8:9], 1, v[8:9]
+; GFX9-SDAG-NEXT:    v_lshrrev_b32_e32 v10, 31, v11
+; GFX9-SDAG-NEXT:    v_or3_b32 v15, v9, 0, v15
+; GFX9-SDAG-NEXT:    v_or3_b32 v14, v8, v10, v14
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v13, v13, v17
+; GFX9-SDAG-NEXT:    v_or_b32_e32 v12, v12, v16
+; GFX9-SDAG-NEXT:  .LBB3_6: ; %Flow3
+; GFX9-SDAG-NEXT:    s_or_b64 exec, exec, s[8:9]
+; GFX9-SDAG-NEXT:    v_mul_lo_u32 v19, v12, v7
+; GFX9-SDAG-NEXT:    v_mad_u64_u32 v[7:8], s[4:5], v4, v12, 0
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v17, 0
+; GFX9-SDAG-NEXT:    v_mad_u64_u32 v[9:10], s[4:5], v12, v6, 0
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v16, v8
+; GFX9-SDAG-NEXT:    v_mad_u64_u32 v[11:12], s[4:5], v5, v12, v[16:17]
+; GFX9-SDAG-NEXT:    v_mul_lo_u32 v18, v13, v6
+; GFX9-SDAG-NEXT:    v_mul_lo_u32 v16, v15, v4
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v6, v12
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v12, v17
+; GFX9-SDAG-NEXT:    v_mad_u64_u32 v[11:12], s[4:5], v4, v13, v[11:12]
+; GFX9-SDAG-NEXT:    v_add3_u32 v10, v10, v19, v18
+; GFX9-SDAG-NEXT:    v_mad_u64_u32 v[8:9], s[4:5], v14, v4, v[9:10]
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v4, v12
+; GFX9-SDAG-NEXT:    v_mul_lo_u32 v10, v14, v5
+; GFX9-SDAG-NEXT:    v_add_co_u32_e32 v14, vcc, v6, v4
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e64 v15, s[4:5], 0, 0, vcc
+; GFX9-SDAG-NEXT:    v_mad_u64_u32 v[4:5], s[4:5], v5, v13, v[14:15]
+; GFX9-SDAG-NEXT:    v_add3_u32 v6, v16, v9, v10
+; GFX9-SDAG-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v8
+; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v5, vcc, v5, v6, vcc
+; GFX9-SDAG-NEXT:    v_mov_b32_e32 v6, v11
+; GFX9-SDAG-NEXT:    v_sub_co_u32_e32 v0, vcc, v0, v7
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v6, vcc
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v2, vcc, v2, v4, vcc
+; GFX9-SDAG-NEXT:    v_subb_co_u32_e32 v3, vcc, v3, v5, vcc
+; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-GISEL-LABEL: v_urem_i128_vv:
+; GFX9-GISEL:       ; %bb.0: ; %_udiv-special-cases
+; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v8, v4, v6
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v9, v5, v7
+; GFX9-GISEL-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[8:9]
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v8, v0, v2
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v9, v1, v3
+; GFX9-GISEL-NEXT:    v_cmp_eq_u64_e64 s[4:5], 0, v[8:9]
+; GFX9-GISEL-NEXT:    v_ffbh_u32_e32 v9, v4
+; GFX9-GISEL-NEXT:    v_ffbh_u32_e32 v8, v5
+; GFX9-GISEL-NEXT:    v_add_u32_e32 v9, 32, v9
+; GFX9-GISEL-NEXT:    v_ffbh_u32_e32 v10, v6
+; GFX9-GISEL-NEXT:    v_min_u32_e32 v8, v8, v9
+; GFX9-GISEL-NEXT:    v_ffbh_u32_e32 v9, v7
+; GFX9-GISEL-NEXT:    v_add_u32_e32 v10, 32, v10
+; GFX9-GISEL-NEXT:    v_cmp_eq_u64_e64 s[6:7], 0, v[6:7]
+; GFX9-GISEL-NEXT:    v_add_u32_e32 v8, 64, v8
+; GFX9-GISEL-NEXT:    v_min_u32_e32 v9, v9, v10
+; GFX9-GISEL-NEXT:    v_ffbh_u32_e32 v10, v0
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v8, v9, v8, s[6:7]
+; GFX9-GISEL-NEXT:    v_ffbh_u32_e32 v9, v1
+; GFX9-GISEL-NEXT:    v_add_u32_e32 v10, 32, v10
+; GFX9-GISEL-NEXT:    v_ffbh_u32_e32 v11, v2
+; GFX9-GISEL-NEXT:    v_min_u32_e32 v9, v9, v10
+; GFX9-GISEL-NEXT:    v_ffbh_u32_e32 v10, v3
+; GFX9-GISEL-NEXT:    v_add_u32_e32 v11, 32, v11
+; GFX9-GISEL-NEXT:    v_cmp_eq_u64_e64 s[6:7], 0, v[2:3]
+; GFX9-GISEL-NEXT:    v_add_u32_e32 v9, 64, v9
+; GFX9-GISEL-NEXT:    v_min_u32_e32 v10, v10, v11
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v9, v10, v9, s[6:7]
+; GFX9-GISEL-NEXT:    v_sub_co_u32_e64 v8, s[6:7], v8, v9
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e64 v9, s[6:7], 0, 0, s[6:7]
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v10, 0x7f
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e64 v12, s[6:7], 0, 0, s[6:7]
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v11, 0
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e64 v13, s[6:7], 0, 0, s[6:7]
+; GFX9-GISEL-NEXT:    v_cmp_gt_u64_e64 s[6:7], v[8:9], v[10:11]
+; GFX9-GISEL-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[6:7]
+; GFX9-GISEL-NEXT:    v_cmp_lt_u64_e64 s[6:7], 0, v[12:13]
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v17, v9, v13
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[6:7]
+; GFX9-GISEL-NEXT:    v_cmp_eq_u64_e64 s[6:7], 0, v[12:13]
+; GFX9-GISEL-NEXT:    s_mov_b64 s[8:9], 0
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v10, v11, v10, s[6:7]
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v18, v11, v10
+; GFX9-GISEL-NEXT:    v_xor_b32_e32 v10, 0x7f, v8
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v16, v10, v12
+; GFX9-GISEL-NEXT:    v_and_b32_e32 v10, 1, v18
+; GFX9-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v14, v0, 0, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v15, v1, 0, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v10, v2, 0, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v11, v3, 0, vcc
+; GFX9-GISEL-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[16:17]
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v16, v18, v16
+; GFX9-GISEL-NEXT:    v_and_b32_e32 v16, 1, v16
+; GFX9-GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v16
+; GFX9-GISEL-NEXT:    s_xor_b64 s[4:5], vcc, -1
+; GFX9-GISEL-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
+; GFX9-GISEL-NEXT:    s_cbranch_execz .LBB3_6
+; GFX9-GISEL-NEXT:  ; %bb.1: ; %udiv-bb1
+; GFX9-GISEL-NEXT:    v_add_co_u32_e32 v22, vcc, 1, v8
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v23, vcc, 0, v9, vcc
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v24, vcc, 0, v12, vcc
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v25, vcc, 0, v13, vcc
+; GFX9-GISEL-NEXT:    s_xor_b64 s[4:5], vcc, -1
+; GFX9-GISEL-NEXT:    v_sub_co_u32_e32 v14, vcc, 0x7f, v8
+; GFX9-GISEL-NEXT:    v_sub_u32_e32 v8, 64, v14
+; GFX9-GISEL-NEXT:    v_lshrrev_b64 v[8:9], v8, v[0:1]
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[10:11], v14, v[2:3]
+; GFX9-GISEL-NEXT:    v_subrev_u32_e32 v15, 64, v14
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[12:13], v14, v[0:1]
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v10, v8, v10
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v11, v9, v11
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[8:9], v15, v[0:1]
+; GFX9-GISEL-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v14
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v12, 0, v12, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v13, 0, v13, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v8, v8, v10, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v9, v9, v11, vcc
+; GFX9-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v14
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v14, v8, v2, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v15, v9, v3, vcc
+; GFX9-GISEL-NEXT:    s_mov_b64 s[10:11], s[8:9]
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v8, s8
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v9, s9
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v10, s10
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v11, s11
+; GFX9-GISEL-NEXT:    s_and_saveexec_b64 s[8:9], s[4:5]
+; GFX9-GISEL-NEXT:    s_xor_b64 s[12:13], exec, s[8:9]
+; GFX9-GISEL-NEXT:    s_cbranch_execz .LBB3_5
+; GFX9-GISEL-NEXT:  ; %bb.2: ; %udiv-preheader
+; GFX9-GISEL-NEXT:    v_sub_u32_e32 v10, 64, v22
+; GFX9-GISEL-NEXT:    v_lshrrev_b64 v[8:9], v22, v[0:1]
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[10:11], v10, v[2:3]
+; GFX9-GISEL-NEXT:    v_subrev_u32_e32 v18, 64, v22
+; GFX9-GISEL-NEXT:    v_lshrrev_b64 v[16:17], v22, v[2:3]
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v10, v8, v10
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v11, v9, v11
+; GFX9-GISEL-NEXT:    v_lshrrev_b64 v[8:9], v18, v[2:3]
+; GFX9-GISEL-NEXT:    v_cmp_gt_u32_e32 vcc, 64, v22
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v8, v8, v10, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v9, v9, v11, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v20, 0, v16, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v21, 0, v17, vcc
+; GFX9-GISEL-NEXT:    v_add_co_u32_e32 v26, vcc, -1, v4
+; GFX9-GISEL-NEXT:    s_mov_b64 s[8:9], 0
+; GFX9-GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v22
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v27, vcc, -1, v5, vcc
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v18, v8, v0, s[4:5]
+; GFX9-GISEL-NEXT:    v_cndmask_b32_e64 v19, v9, v1, s[4:5]
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v28, vcc, -1, v6, vcc
+; GFX9-GISEL-NEXT:    s_mov_b64 s[10:11], s[8:9]
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v8, s8
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v29, vcc, -1, v7, vcc
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v17, 0
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v9, s9
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v10, s10
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v11, s11
+; GFX9-GISEL-NEXT:  .LBB3_3: ; %udiv-do-while
+; GFX9-GISEL-NEXT:    ; =>This Inner Loop Header: Depth=1
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[10:11], 1, v[12:13]
+; GFX9-GISEL-NEXT:    v_lshrrev_b32_e32 v16, 31, v13
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v12, v8, v10
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v13, v9, v11
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[10:11], 1, v[18:19]
+; GFX9-GISEL-NEXT:    v_lshrrev_b32_e32 v18, 31, v15
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[8:9], 1, v[20:21]
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v10, v10, v18
+; GFX9-GISEL-NEXT:    v_lshrrev_b32_e32 v20, 31, v19
+; GFX9-GISEL-NEXT:    v_sub_co_u32_e32 v18, vcc, v26, v10
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v8, v8, v20
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v18, vcc, v27, v11, vcc
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v18, vcc, v28, v8, vcc
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v18, vcc, v29, v9, vcc
+; GFX9-GISEL-NEXT:    v_ashrrev_i32_e32 v30, 31, v18
+; GFX9-GISEL-NEXT:    v_and_b32_e32 v18, v30, v4
+; GFX9-GISEL-NEXT:    v_sub_co_u32_e32 v18, vcc, v10, v18
+; GFX9-GISEL-NEXT:    v_and_b32_e32 v10, v30, v5
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v19, vcc, v11, v10, vcc
+; GFX9-GISEL-NEXT:    v_and_b32_e32 v10, v30, v6
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v20, vcc, v8, v10, vcc
+; GFX9-GISEL-NEXT:    v_and_b32_e32 v8, v30, v7
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v21, vcc, v9, v8, vcc
+; GFX9-GISEL-NEXT:    v_add_co_u32_e32 v22, vcc, -1, v22
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v23, vcc, -1, v23, vcc
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v24, vcc, -1, v24, vcc
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v25, vcc, -1, v25, vcc
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[14:15], 1, v[14:15]
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v8, v22, v24
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v9, v23, v25
+; GFX9-GISEL-NEXT:    v_cmp_eq_u64_e32 vcc, 0, v[8:9]
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v14, v14, v16
+; GFX9-GISEL-NEXT:    v_and_b32_e32 v16, 1, v30
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v8, v16
+; GFX9-GISEL-NEXT:    s_or_b64 s[8:9], vcc, s[8:9]
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v9, v17
+; GFX9-GISEL-NEXT:    s_andn2_b64 exec, exec, s[8:9]
+; GFX9-GISEL-NEXT:    s_cbranch_execnz .LBB3_3
+; GFX9-GISEL-NEXT:  ; %bb.4: ; %Flow
+; GFX9-GISEL-NEXT:    s_or_b64 exec, exec, s[8:9]
+; GFX9-GISEL-NEXT:  .LBB3_5: ; %Flow2
+; GFX9-GISEL-NEXT:    s_or_b64 exec, exec, s[12:13]
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[16:17], 1, v[12:13]
+; GFX9-GISEL-NEXT:    v_lshlrev_b64 v[10:11], 1, v[14:15]
+; GFX9-GISEL-NEXT:    v_lshrrev_b32_e32 v12, 31, v13
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v10, v10, v12
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v14, v8, v16
+; GFX9-GISEL-NEXT:    v_or_b32_e32 v15, v9, v17
+; GFX9-GISEL-NEXT:  .LBB3_6: ; %Flow3
+; GFX9-GISEL-NEXT:    s_or_b64 exec, exec, s[6:7]
+; GFX9-GISEL-NEXT:    v_mad_u64_u32 v[8:9], s[4:5], v4, v10, 0
+; GFX9-GISEL-NEXT:    v_mad_u64_u32 v[12:13], s[4:5], v4, v14, 0
+; GFX9-GISEL-NEXT:    v_mad_u64_u32 v[8:9], s[4:5], v5, v15, v[8:9]
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v16, v13
+; GFX9-GISEL-NEXT:    v_mul_lo_u32 v10, v5, v10
+; GFX9-GISEL-NEXT:    v_mad_u64_u32 v[8:9], s[4:5], v6, v14, v[8:9]
+; GFX9-GISEL-NEXT:    v_mov_b32_e32 v17, v8
+; GFX9-GISEL-NEXT:    v_mad_u64_u32 v[16:17], vcc, v4, v15, v[16:17]
+; GFX9-GISEL-NEXT:    v_mul_lo_u32 v8, v4, v11
+; GFX9-GISEL-NEXT:    v_mad_u64_u32 v[4:5], s[4:5], v5, v14, v[16:17]
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e64 v8, s[4:5], v9, v8, s[4:5]
+; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v8, vcc, v8, v10, vcc
+; GFX9-GISEL-NEXT:    v_mad_u64_u32 v[8:9], s[4:5], v6, v15, v[8:9]
+; GFX9-GISEL-NEXT:    v_sub_co_u32_e32 v0, vcc, v0, v12
+; GFX9-GISEL-NEXT:    v_mad_u64_u32 v[6:7], s[4:5], v7, v14, v[8:9]
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v4, vcc
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v2, vcc, v2, v5, vcc
+; GFX9-GISEL-NEXT:    v_subb_co_u32_e32 v3, vcc, v3, v6, vcc
+; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
+  %shl = urem i128 %lhs, %rhs
+  ret i128 %shl
+}
+
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX9: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/div_v2i128.ll b/llvm/test/CodeGen/AMDGPU/div_v2i128.ll
new file mode 100644
index 0000000000000..46e2632e45a19
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/div_v2i128.ll
@@ -0,0 +1,25 @@
+; RUN: not --crash llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -o - %s 2>&1 | FileCheck -check-prefix=SDAG-ERR %s
+; RUN: not --crash llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -o - %s 2>&1 | FileCheck -check-prefix=GISEL-ERR %s
+
+; SDAG-ERR: LLVM ERROR: unsupported libcall legalization
+; GISEL-ERR: LLVM ERROR: unable to legalize instruction: %{{[0-9]+}}:_(s128) = G_SDIV %{{[0-9]+}}:_, %{{[0-9]+}}:_ (in function: v_sdiv_v2i128_vv)
+
+define <2 x i128> @v_sdiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
+  %shl = sdiv <2 x i128> %lhs, %rhs
+  ret <2 x i128> %shl
+}
+
+define <2 x i128> @v_udiv_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
+  %shl = udiv <2 x i128> %lhs, %rhs
+  ret <2 x i128> %shl
+}
+
+define <2 x i128> @v_srem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
+  %shl = srem <2 x i128> %lhs, %rhs
+  ret <2 x i128> %shl
+}
+
+define <2 x i128> @v_urem_v2i128_vv(<2 x i128> %lhs, <2 x i128> %rhs) {
+  %shl = urem <2 x i128> %lhs, %rhs
+  ret <2 x i128> %shl
+}

