[llvm] 3e230bb - [CodeGen] Return ArrayRef from TargetRegisterClass::getRegisters. NFCI. (#80411)

[via llvm-commits]

Author: Jay Foad
Date: 2024-02-05T09:39:16Z
New Revision: 3e230bb6e1a2668e920ee496121e5e40baeb4552

URL: https://github.com/llvm/llvm-project/commit/3e230bb6e1a2668e920ee496121e5e40baeb4552
DIFF: https://github.com/llvm/llvm-project/commit/3e230bb6e1a2668e920ee496121e5e40baeb4552.diff

LOG: [CodeGen] Return ArrayRef from TargetRegisterClass::getRegisters. NFCI. (#80411)

This will allow future patches to use indexing and methods like
drop_front on the result.

Added: 
    

Modified: 
    llvm/include/llvm/CodeGen/TargetRegisterInfo.h

Removed: 
    


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diff  --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
index 75c482d7bcaa9..5098fc68df3b2 100644
--- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -81,9 +81,8 @@ class TargetRegisterClass {
   /// Return the number of registers in this class.
   unsigned getNumRegs() const { return MC->getNumRegs(); }
 
-  iterator_range<SmallVectorImpl<MCPhysReg>::const_iterator>
-  getRegisters() const {
-    return make_range(MC->begin(), MC->end());
+  ArrayRef<MCPhysReg> getRegisters() const {
+    return ArrayRef(begin(), getNumRegs());
   }
 
   /// Return the specified register in the class.
@@ -203,7 +202,7 @@ class TargetRegisterClass {
   ///
   /// By default, this method returns all registers in the class.
   ArrayRef<MCPhysReg> getRawAllocationOrder(const MachineFunction &MF) const {
-    return OrderFunc ? OrderFunc(MF) : ArrayRef(begin(), getNumRegs());
+    return OrderFunc ? OrderFunc(MF) : getRegisters();
   }
 
   /// Returns the combination of all lane masks of register in this class.