[llvm] 5afeba0 - [RISCV] Custom legalize i32 UADDSAT/USUBSAT for -riscv-experimental-rv64-legal-i32 with Zbb.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Feb 4 21:48:02 PST 2024
Author: Craig Topper
Date: 2024-02-04T21:37:38-08:00
New Revision: 5afeba051e5c3ad1860cf1642a99e60452d514de
URL: https://github.com/llvm/llvm-project/commit/5afeba051e5c3ad1860cf1642a99e60452d514de
DIFF: https://github.com/llvm/llvm-project/commit/5afeba051e5c3ad1860cf1642a99e60452d514de.diff
LOG: [RISCV] Custom legalize i32 UADDSAT/USUBSAT for -riscv-experimental-rv64-legal-i32 with Zbb.
This matches the codegen we get from type legalization without
-riscv-experimental-rv64-legal-i32.
Added:
llvm/test/CodeGen/RISCV/rv64-legal-i32/sadd_sat.ll
llvm/test/CodeGen/RISCV/rv64-legal-i32/sadd_sat_plus.ll
llvm/test/CodeGen/RISCV/rv64-legal-i32/ssub_sat.ll
llvm/test/CodeGen/RISCV/rv64-legal-i32/ssub_sat_plus.ll
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 73f3d4a8641d5..0d7fdfd9b9754 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -284,8 +284,10 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
MVT::i32, Custom);
} else {
setOperationAction(ISD::SSUBO, MVT::i32, Custom);
- if (Subtarget.hasStdExtZbb())
+ if (Subtarget.hasStdExtZbb()) {
+ setOperationAction({ISD::SADDSAT, ISD::SSUBSAT}, MVT::i32, Custom);
setOperationAction({ISD::UADDSAT, ISD::USUBSAT}, MVT::i32, Custom);
+ }
}
setOperationAction(ISD::SADDO, MVT::i32, Custom);
} else {
@@ -5360,6 +5362,27 @@ static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
return Op;
}
+static SDValue lowerSADDSAT_SSUBSAT(SDValue Op, SelectionDAG &DAG) {
+ assert(Op.getValueType() == MVT::i32 && RV64LegalI32 &&
+ "Unexpected custom legalisation");
+
+ // With Zbb, we can widen to i64 and smin/smax with INT32_MAX/MIN.
+ bool IsAdd = Op.getOpcode() == ISD::SADDSAT;
+ SDLoc DL(Op);
+ SDValue LHS = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op.getOperand(0));
+ SDValue RHS = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op.getOperand(1));
+ SDValue Result =
+ DAG.getNode(IsAdd ? ISD::ADD : ISD::SUB, DL, MVT::i64, LHS, RHS);
+
+ APInt MinVal = APInt::getSignedMinValue(32).sext(64);
+ APInt MaxVal = APInt::getSignedMaxValue(32).sext(64);
+ SDValue SatMin = DAG.getConstant(MinVal, DL, MVT::i64);
+ SDValue SatMax = DAG.getConstant(MaxVal, DL, MVT::i64);
+ Result = DAG.getNode(ISD::SMIN, DL, MVT::i64, Result, SatMax);
+ Result = DAG.getNode(ISD::SMAX, DL, MVT::i64, Result, SatMin);
+ return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Result);
+}
+
static SDValue lowerUADDSAT_USUBSAT(SDValue Op, SelectionDAG &DAG) {
assert(Op.getValueType() == MVT::i32 && RV64LegalI32 &&
"Unexpected custom legalisation");
@@ -6635,8 +6658,6 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
[[fallthrough]];
case ISD::AVGFLOORU:
case ISD::AVGCEILU:
- case ISD::SADDSAT:
- case ISD::SSUBSAT:
case ISD::SMIN:
case ISD::SMAX:
case ISD::UMIN:
@@ -6647,6 +6668,11 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
if (!Op.getValueType().isVector())
return lowerUADDSAT_USUBSAT(Op, DAG);
return lowerToScalableOp(Op, DAG);
+ case ISD::SADDSAT:
+ case ISD::SSUBSAT:
+ if (!Op.getValueType().isVector())
+ return lowerSADDSAT_SSUBSAT(Op, DAG);
+ return lowerToScalableOp(Op, DAG);
case ISD::ABS:
case ISD::VP_ABS:
return lowerABS(Op, DAG);
diff --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/sadd_sat.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/sadd_sat.ll
new file mode 100644
index 0000000000000..080ac2b8fac01
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/sadd_sat.ll
@@ -0,0 +1,151 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=riscv64 -mattr=+m \
+; RUN: -riscv-experimental-rv64-legal-i32 | FileCheck %s --check-prefixes=RV64,RV64I
+; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb \
+; RUN: -riscv-experimental-rv64-legal-i32 | FileCheck %s --check-prefixes=RV64,RV64IZbb
+
+declare i4 @llvm.sadd.sat.i4(i4, i4)
+declare i8 @llvm.sadd.sat.i8(i8, i8)
+declare i16 @llvm.sadd.sat.i16(i16, i16)
+declare i32 @llvm.sadd.sat.i32(i32, i32)
+declare i64 @llvm.sadd.sat.i64(i64, i64)
+
+define signext i32 @func(i32 signext %x, i32 signext %y) nounwind {
+; RV64I-LABEL: func:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addw a2, a0, a1
+; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: beq a0, a2, .LBB0_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: sraiw a0, a0, 31
+; RV64I-NEXT: lui a1, 524288
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: .LBB0_2:
+; RV64I-NEXT: sext.w a0, a0
+; RV64I-NEXT: ret
+;
+; RV64IZbb-LABEL: func:
+; RV64IZbb: # %bb.0:
+; RV64IZbb-NEXT: add a0, a0, a1
+; RV64IZbb-NEXT: lui a1, 524288
+; RV64IZbb-NEXT: addiw a2, a1, -1
+; RV64IZbb-NEXT: min a0, a0, a2
+; RV64IZbb-NEXT: max a0, a0, a1
+; RV64IZbb-NEXT: ret
+ %tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %y);
+ ret i32 %tmp;
+}
+
+define i64 @func2(i64 %x, i64 %y) nounwind {
+; RV64-LABEL: func2:
+; RV64: # %bb.0:
+; RV64-NEXT: mv a2, a0
+; RV64-NEXT: add a0, a0, a1
+; RV64-NEXT: slt a2, a0, a2
+; RV64-NEXT: slti a1, a1, 0
+; RV64-NEXT: beq a1, a2, .LBB1_2
+; RV64-NEXT: # %bb.1:
+; RV64-NEXT: srai a0, a0, 63
+; RV64-NEXT: li a1, -1
+; RV64-NEXT: slli a1, a1, 63
+; RV64-NEXT: xor a0, a0, a1
+; RV64-NEXT: .LBB1_2:
+; RV64-NEXT: ret
+ %tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %y);
+ ret i64 %tmp;
+}
+
+define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {
+; RV64I-LABEL: func16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addw a0, a0, a1
+; RV64I-NEXT: lui a1, 8
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: bge a0, a1, .LBB2_3
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: lui a1, 1048568
+; RV64I-NEXT: bge a1, a0, .LBB2_4
+; RV64I-NEXT: .LBB2_2:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB2_3:
+; RV64I-NEXT: mv a0, a1
+; RV64I-NEXT: lui a1, 1048568
+; RV64I-NEXT: blt a1, a0, .LBB2_2
+; RV64I-NEXT: .LBB2_4:
+; RV64I-NEXT: lui a0, 1048568
+; RV64I-NEXT: ret
+;
+; RV64IZbb-LABEL: func16:
+; RV64IZbb: # %bb.0:
+; RV64IZbb-NEXT: addw a0, a0, a1
+; RV64IZbb-NEXT: lui a1, 8
+; RV64IZbb-NEXT: addiw a1, a1, -1
+; RV64IZbb-NEXT: min a0, a0, a1
+; RV64IZbb-NEXT: lui a1, 1048568
+; RV64IZbb-NEXT: max a0, a0, a1
+; RV64IZbb-NEXT: ret
+ %tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %y);
+ ret i16 %tmp;
+}
+
+define signext i8 @func8(i8 signext %x, i8 signext %y) nounwind {
+; RV64I-LABEL: func8:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addw a0, a0, a1
+; RV64I-NEXT: li a1, 127
+; RV64I-NEXT: bge a0, a1, .LBB3_3
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: li a1, -127
+; RV64I-NEXT: blt a0, a1, .LBB3_4
+; RV64I-NEXT: .LBB3_2:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB3_3:
+; RV64I-NEXT: li a0, 127
+; RV64I-NEXT: li a1, -127
+; RV64I-NEXT: bge a0, a1, .LBB3_2
+; RV64I-NEXT: .LBB3_4:
+; RV64I-NEXT: li a0, -128
+; RV64I-NEXT: ret
+;
+; RV64IZbb-LABEL: func8:
+; RV64IZbb: # %bb.0:
+; RV64IZbb-NEXT: addw a0, a0, a1
+; RV64IZbb-NEXT: li a1, 127
+; RV64IZbb-NEXT: min a0, a0, a1
+; RV64IZbb-NEXT: li a1, -128
+; RV64IZbb-NEXT: max a0, a0, a1
+; RV64IZbb-NEXT: ret
+ %tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %y);
+ ret i8 %tmp;
+}
+
+define signext i4 @func3(i4 signext %x, i4 signext %y) nounwind {
+; RV64I-LABEL: func3:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addw a0, a0, a1
+; RV64I-NEXT: li a1, 7
+; RV64I-NEXT: bge a0, a1, .LBB4_3
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: li a1, -7
+; RV64I-NEXT: blt a0, a1, .LBB4_4
+; RV64I-NEXT: .LBB4_2:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB4_3:
+; RV64I-NEXT: li a0, 7
+; RV64I-NEXT: li a1, -7
+; RV64I-NEXT: bge a0, a1, .LBB4_2
+; RV64I-NEXT: .LBB4_4:
+; RV64I-NEXT: li a0, -8
+; RV64I-NEXT: ret
+;
+; RV64IZbb-LABEL: func3:
+; RV64IZbb: # %bb.0:
+; RV64IZbb-NEXT: addw a0, a0, a1
+; RV64IZbb-NEXT: li a1, 7
+; RV64IZbb-NEXT: min a0, a0, a1
+; RV64IZbb-NEXT: li a1, -8
+; RV64IZbb-NEXT: max a0, a0, a1
+; RV64IZbb-NEXT: ret
+ %tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %y);
+ ret i4 %tmp;
+}
diff --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/sadd_sat_plus.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/sadd_sat_plus.ll
new file mode 100644
index 0000000000000..70c70d3ba9ba7
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/sadd_sat_plus.ll
@@ -0,0 +1,185 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=riscv64 -mattr=+m \
+; RUN: -riscv-experimental-rv64-legal-i32 | FileCheck %s --check-prefixes=RV64,RV64I
+; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb \
+; RUN: -riscv-experimental-rv64-legal-i32 | FileCheck %s --check-prefixes=RV64,RV64IZbb
+
+declare i4 @llvm.sadd.sat.i4(i4, i4)
+declare i8 @llvm.sadd.sat.i8(i8, i8)
+declare i16 @llvm.sadd.sat.i16(i16, i16)
+declare i32 @llvm.sadd.sat.i32(i32, i32)
+declare i64 @llvm.sadd.sat.i64(i64, i64)
+
+define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
+; RV64I-LABEL: func32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: mulw a1, a1, a2
+; RV64I-NEXT: sext.w a0, a0
+; RV64I-NEXT: addw a2, a0, a1
+; RV64I-NEXT: add a0, a0, a1
+; RV64I-NEXT: beq a0, a2, .LBB0_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: sraiw a0, a0, 31
+; RV64I-NEXT: lui a1, 524288
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: .LBB0_2:
+; RV64I-NEXT: ret
+;
+; RV64IZbb-LABEL: func32:
+; RV64IZbb: # %bb.0:
+; RV64IZbb-NEXT: mulw a1, a1, a2
+; RV64IZbb-NEXT: sext.w a0, a0
+; RV64IZbb-NEXT: add a0, a0, a1
+; RV64IZbb-NEXT: lui a1, 524288
+; RV64IZbb-NEXT: addiw a2, a1, -1
+; RV64IZbb-NEXT: min a0, a0, a2
+; RV64IZbb-NEXT: max a0, a0, a1
+; RV64IZbb-NEXT: ret
+ %a = mul i32 %y, %z
+ %tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %a)
+ ret i32 %tmp
+}
+
+define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
+; RV64-LABEL: func64:
+; RV64: # %bb.0:
+; RV64-NEXT: mv a1, a0
+; RV64-NEXT: add a0, a0, a2
+; RV64-NEXT: slt a1, a0, a1
+; RV64-NEXT: slti a2, a2, 0
+; RV64-NEXT: beq a2, a1, .LBB1_2
+; RV64-NEXT: # %bb.1:
+; RV64-NEXT: srai a0, a0, 63
+; RV64-NEXT: li a1, -1
+; RV64-NEXT: slli a1, a1, 63
+; RV64-NEXT: xor a0, a0, a1
+; RV64-NEXT: .LBB1_2:
+; RV64-NEXT: ret
+ %a = mul i64 %y, %z
+ %tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %z)
+ ret i64 %tmp
+}
+
+define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {
+; RV64I-LABEL: func16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a0, a0, 16
+; RV64I-NEXT: sraiw a0, a0, 16
+; RV64I-NEXT: mul a1, a1, a2
+; RV64I-NEXT: slli a1, a1, 16
+; RV64I-NEXT: sraiw a1, a1, 16
+; RV64I-NEXT: addw a0, a0, a1
+; RV64I-NEXT: lui a1, 8
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: bge a0, a1, .LBB2_3
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: lui a1, 1048568
+; RV64I-NEXT: bge a1, a0, .LBB2_4
+; RV64I-NEXT: .LBB2_2:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB2_3:
+; RV64I-NEXT: mv a0, a1
+; RV64I-NEXT: lui a1, 1048568
+; RV64I-NEXT: blt a1, a0, .LBB2_2
+; RV64I-NEXT: .LBB2_4:
+; RV64I-NEXT: lui a0, 1048568
+; RV64I-NEXT: ret
+;
+; RV64IZbb-LABEL: func16:
+; RV64IZbb: # %bb.0:
+; RV64IZbb-NEXT: sext.h a0, a0
+; RV64IZbb-NEXT: mul a1, a1, a2
+; RV64IZbb-NEXT: sext.h a1, a1
+; RV64IZbb-NEXT: addw a0, a0, a1
+; RV64IZbb-NEXT: lui a1, 8
+; RV64IZbb-NEXT: addiw a1, a1, -1
+; RV64IZbb-NEXT: min a0, a0, a1
+; RV64IZbb-NEXT: lui a1, 1048568
+; RV64IZbb-NEXT: max a0, a0, a1
+; RV64IZbb-NEXT: ret
+ %a = mul i16 %y, %z
+ %tmp = call i16 @llvm.sadd.sat.i16(i16 %x, i16 %a)
+ ret i16 %tmp
+}
+
+define i8 @func8(i8 %x, i8 %y, i8 %z) nounwind {
+; RV64I-LABEL: func8:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a0, a0, 24
+; RV64I-NEXT: sraiw a0, a0, 24
+; RV64I-NEXT: mul a1, a1, a2
+; RV64I-NEXT: slli a1, a1, 24
+; RV64I-NEXT: sraiw a1, a1, 24
+; RV64I-NEXT: addw a0, a0, a1
+; RV64I-NEXT: li a1, 127
+; RV64I-NEXT: bge a0, a1, .LBB3_3
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: li a1, -127
+; RV64I-NEXT: blt a0, a1, .LBB3_4
+; RV64I-NEXT: .LBB3_2:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB3_3:
+; RV64I-NEXT: li a0, 127
+; RV64I-NEXT: li a1, -127
+; RV64I-NEXT: bge a0, a1, .LBB3_2
+; RV64I-NEXT: .LBB3_4:
+; RV64I-NEXT: li a0, -128
+; RV64I-NEXT: ret
+;
+; RV64IZbb-LABEL: func8:
+; RV64IZbb: # %bb.0:
+; RV64IZbb-NEXT: sext.b a0, a0
+; RV64IZbb-NEXT: mul a1, a1, a2
+; RV64IZbb-NEXT: sext.b a1, a1
+; RV64IZbb-NEXT: addw a0, a0, a1
+; RV64IZbb-NEXT: li a1, 127
+; RV64IZbb-NEXT: min a0, a0, a1
+; RV64IZbb-NEXT: li a1, -128
+; RV64IZbb-NEXT: max a0, a0, a1
+; RV64IZbb-NEXT: ret
+ %a = mul i8 %y, %z
+ %tmp = call i8 @llvm.sadd.sat.i8(i8 %x, i8 %a)
+ ret i8 %tmp
+}
+
+define i4 @func4(i4 %x, i4 %y, i4 %z) nounwind {
+; RV64I-LABEL: func4:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a0, a0, 28
+; RV64I-NEXT: sraiw a0, a0, 28
+; RV64I-NEXT: mul a1, a1, a2
+; RV64I-NEXT: slli a1, a1, 28
+; RV64I-NEXT: sraiw a1, a1, 28
+; RV64I-NEXT: addw a0, a0, a1
+; RV64I-NEXT: li a1, 7
+; RV64I-NEXT: bge a0, a1, .LBB4_3
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: li a1, -7
+; RV64I-NEXT: blt a0, a1, .LBB4_4
+; RV64I-NEXT: .LBB4_2:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB4_3:
+; RV64I-NEXT: li a0, 7
+; RV64I-NEXT: li a1, -7
+; RV64I-NEXT: bge a0, a1, .LBB4_2
+; RV64I-NEXT: .LBB4_4:
+; RV64I-NEXT: li a0, -8
+; RV64I-NEXT: ret
+;
+; RV64IZbb-LABEL: func4:
+; RV64IZbb: # %bb.0:
+; RV64IZbb-NEXT: slli a0, a0, 28
+; RV64IZbb-NEXT: sraiw a0, a0, 28
+; RV64IZbb-NEXT: mul a1, a1, a2
+; RV64IZbb-NEXT: slli a1, a1, 28
+; RV64IZbb-NEXT: sraiw a1, a1, 28
+; RV64IZbb-NEXT: addw a0, a0, a1
+; RV64IZbb-NEXT: li a1, 7
+; RV64IZbb-NEXT: min a0, a0, a1
+; RV64IZbb-NEXT: li a1, -8
+; RV64IZbb-NEXT: max a0, a0, a1
+; RV64IZbb-NEXT: ret
+ %a = mul i4 %y, %z
+ %tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %a)
+ ret i4 %tmp
+}
diff --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/ssub_sat.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/ssub_sat.ll
new file mode 100644
index 0000000000000..0a566ee8b2120
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/ssub_sat.ll
@@ -0,0 +1,151 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=riscv64 -mattr=+m \
+; RUN: -riscv-experimental-rv64-legal-i32 | FileCheck %s --check-prefixes=RV64,RV64I
+; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb \
+; RUN: -riscv-experimental-rv64-legal-i32 | FileCheck %s --check-prefixes=RV64,RV64IZbb
+
+declare i4 @llvm.ssub.sat.i4(i4, i4)
+declare i8 @llvm.ssub.sat.i8(i8, i8)
+declare i16 @llvm.ssub.sat.i16(i16, i16)
+declare i32 @llvm.ssub.sat.i32(i32, i32)
+declare i64 @llvm.ssub.sat.i64(i64, i64)
+
+define signext i32 @func(i32 signext %x, i32 signext %y) nounwind {
+; RV64I-LABEL: func:
+; RV64I: # %bb.0:
+; RV64I-NEXT: subw a2, a0, a1
+; RV64I-NEXT: sub a0, a0, a1
+; RV64I-NEXT: beq a0, a2, .LBB0_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: sraiw a0, a0, 31
+; RV64I-NEXT: lui a1, 524288
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: .LBB0_2:
+; RV64I-NEXT: sext.w a0, a0
+; RV64I-NEXT: ret
+;
+; RV64IZbb-LABEL: func:
+; RV64IZbb: # %bb.0:
+; RV64IZbb-NEXT: sub a0, a0, a1
+; RV64IZbb-NEXT: lui a1, 524288
+; RV64IZbb-NEXT: addiw a2, a1, -1
+; RV64IZbb-NEXT: min a0, a0, a2
+; RV64IZbb-NEXT: max a0, a0, a1
+; RV64IZbb-NEXT: ret
+ %tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %y);
+ ret i32 %tmp;
+}
+
+define i64 @func2(i64 %x, i64 %y) nounwind {
+; RV64-LABEL: func2:
+; RV64: # %bb.0:
+; RV64-NEXT: mv a2, a0
+; RV64-NEXT: sgtz a3, a1
+; RV64-NEXT: sub a0, a0, a1
+; RV64-NEXT: slt a1, a0, a2
+; RV64-NEXT: beq a3, a1, .LBB1_2
+; RV64-NEXT: # %bb.1:
+; RV64-NEXT: srai a0, a0, 63
+; RV64-NEXT: li a1, -1
+; RV64-NEXT: slli a1, a1, 63
+; RV64-NEXT: xor a0, a0, a1
+; RV64-NEXT: .LBB1_2:
+; RV64-NEXT: ret
+ %tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %y);
+ ret i64 %tmp;
+}
+
+define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {
+; RV64I-LABEL: func16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: subw a0, a0, a1
+; RV64I-NEXT: lui a1, 8
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: bge a0, a1, .LBB2_3
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: lui a1, 1048568
+; RV64I-NEXT: bge a1, a0, .LBB2_4
+; RV64I-NEXT: .LBB2_2:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB2_3:
+; RV64I-NEXT: mv a0, a1
+; RV64I-NEXT: lui a1, 1048568
+; RV64I-NEXT: blt a1, a0, .LBB2_2
+; RV64I-NEXT: .LBB2_4:
+; RV64I-NEXT: lui a0, 1048568
+; RV64I-NEXT: ret
+;
+; RV64IZbb-LABEL: func16:
+; RV64IZbb: # %bb.0:
+; RV64IZbb-NEXT: subw a0, a0, a1
+; RV64IZbb-NEXT: lui a1, 8
+; RV64IZbb-NEXT: addiw a1, a1, -1
+; RV64IZbb-NEXT: min a0, a0, a1
+; RV64IZbb-NEXT: lui a1, 1048568
+; RV64IZbb-NEXT: max a0, a0, a1
+; RV64IZbb-NEXT: ret
+ %tmp = call i16 @llvm.ssub.sat.i16(i16 %x, i16 %y);
+ ret i16 %tmp;
+}
+
+define signext i8 @func8(i8 signext %x, i8 signext %y) nounwind {
+; RV64I-LABEL: func8:
+; RV64I: # %bb.0:
+; RV64I-NEXT: subw a0, a0, a1
+; RV64I-NEXT: li a1, 127
+; RV64I-NEXT: bge a0, a1, .LBB3_3
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: li a1, -127
+; RV64I-NEXT: blt a0, a1, .LBB3_4
+; RV64I-NEXT: .LBB3_2:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB3_3:
+; RV64I-NEXT: li a0, 127
+; RV64I-NEXT: li a1, -127
+; RV64I-NEXT: bge a0, a1, .LBB3_2
+; RV64I-NEXT: .LBB3_4:
+; RV64I-NEXT: li a0, -128
+; RV64I-NEXT: ret
+;
+; RV64IZbb-LABEL: func8:
+; RV64IZbb: # %bb.0:
+; RV64IZbb-NEXT: subw a0, a0, a1
+; RV64IZbb-NEXT: li a1, 127
+; RV64IZbb-NEXT: min a0, a0, a1
+; RV64IZbb-NEXT: li a1, -128
+; RV64IZbb-NEXT: max a0, a0, a1
+; RV64IZbb-NEXT: ret
+ %tmp = call i8 @llvm.ssub.sat.i8(i8 %x, i8 %y);
+ ret i8 %tmp;
+}
+
+define signext i4 @func3(i4 signext %x, i4 signext %y) nounwind {
+; RV64I-LABEL: func3:
+; RV64I: # %bb.0:
+; RV64I-NEXT: subw a0, a0, a1
+; RV64I-NEXT: li a1, 7
+; RV64I-NEXT: bge a0, a1, .LBB4_3
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: li a1, -7
+; RV64I-NEXT: blt a0, a1, .LBB4_4
+; RV64I-NEXT: .LBB4_2:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB4_3:
+; RV64I-NEXT: li a0, 7
+; RV64I-NEXT: li a1, -7
+; RV64I-NEXT: bge a0, a1, .LBB4_2
+; RV64I-NEXT: .LBB4_4:
+; RV64I-NEXT: li a0, -8
+; RV64I-NEXT: ret
+;
+; RV64IZbb-LABEL: func3:
+; RV64IZbb: # %bb.0:
+; RV64IZbb-NEXT: subw a0, a0, a1
+; RV64IZbb-NEXT: li a1, 7
+; RV64IZbb-NEXT: min a0, a0, a1
+; RV64IZbb-NEXT: li a1, -8
+; RV64IZbb-NEXT: max a0, a0, a1
+; RV64IZbb-NEXT: ret
+ %tmp = call i4 @llvm.ssub.sat.i4(i4 %x, i4 %y);
+ ret i4 %tmp;
+}
diff --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/ssub_sat_plus.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/ssub_sat_plus.ll
new file mode 100644
index 0000000000000..bc73ba7cf85ff
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/ssub_sat_plus.ll
@@ -0,0 +1,185 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=riscv64 -mattr=+m \
+; RUN: -riscv-experimental-rv64-legal-i32 | FileCheck %s --check-prefixes=RV64,RV64I
+; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+zbb \
+; RUN: -riscv-experimental-rv64-legal-i32 | FileCheck %s --check-prefixes=RV64,RV64IZbb
+
+declare i4 @llvm.ssub.sat.i4(i4, i4)
+declare i8 @llvm.ssub.sat.i8(i8, i8)
+declare i16 @llvm.ssub.sat.i16(i16, i16)
+declare i32 @llvm.ssub.sat.i32(i32, i32)
+declare i64 @llvm.ssub.sat.i64(i64, i64)
+
+define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
+; RV64I-LABEL: func32:
+; RV64I: # %bb.0:
+; RV64I-NEXT: mulw a1, a1, a2
+; RV64I-NEXT: sext.w a0, a0
+; RV64I-NEXT: subw a2, a0, a1
+; RV64I-NEXT: sub a0, a0, a1
+; RV64I-NEXT: beq a0, a2, .LBB0_2
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: sraiw a0, a0, 31
+; RV64I-NEXT: lui a1, 524288
+; RV64I-NEXT: xor a0, a0, a1
+; RV64I-NEXT: .LBB0_2:
+; RV64I-NEXT: ret
+;
+; RV64IZbb-LABEL: func32:
+; RV64IZbb: # %bb.0:
+; RV64IZbb-NEXT: mulw a1, a1, a2
+; RV64IZbb-NEXT: sext.w a0, a0
+; RV64IZbb-NEXT: sub a0, a0, a1
+; RV64IZbb-NEXT: lui a1, 524288
+; RV64IZbb-NEXT: addiw a2, a1, -1
+; RV64IZbb-NEXT: min a0, a0, a2
+; RV64IZbb-NEXT: max a0, a0, a1
+; RV64IZbb-NEXT: ret
+ %a = mul i32 %y, %z
+ %tmp = call i32 @llvm.ssub.sat.i32(i32 %x, i32 %a)
+ ret i32 %tmp
+}
+
+define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
+; RV64-LABEL: func64:
+; RV64: # %bb.0:
+; RV64-NEXT: mv a1, a0
+; RV64-NEXT: sgtz a3, a2
+; RV64-NEXT: sub a0, a0, a2
+; RV64-NEXT: slt a1, a0, a1
+; RV64-NEXT: beq a3, a1, .LBB1_2
+; RV64-NEXT: # %bb.1:
+; RV64-NEXT: srai a0, a0, 63
+; RV64-NEXT: li a1, -1
+; RV64-NEXT: slli a1, a1, 63
+; RV64-NEXT: xor a0, a0, a1
+; RV64-NEXT: .LBB1_2:
+; RV64-NEXT: ret
+ %a = mul i64 %y, %z
+ %tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %z)
+ ret i64 %tmp
+}
+
+define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {
+; RV64I-LABEL: func16:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a0, a0, 16
+; RV64I-NEXT: sraiw a0, a0, 16
+; RV64I-NEXT: mul a1, a1, a2
+; RV64I-NEXT: slli a1, a1, 16
+; RV64I-NEXT: sraiw a1, a1, 16
+; RV64I-NEXT: subw a0, a0, a1
+; RV64I-NEXT: lui a1, 8
+; RV64I-NEXT: addiw a1, a1, -1
+; RV64I-NEXT: bge a0, a1, .LBB2_3
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: lui a1, 1048568
+; RV64I-NEXT: bge a1, a0, .LBB2_4
+; RV64I-NEXT: .LBB2_2:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB2_3:
+; RV64I-NEXT: mv a0, a1
+; RV64I-NEXT: lui a1, 1048568
+; RV64I-NEXT: blt a1, a0, .LBB2_2
+; RV64I-NEXT: .LBB2_4:
+; RV64I-NEXT: lui a0, 1048568
+; RV64I-NEXT: ret
+;
+; RV64IZbb-LABEL: func16:
+; RV64IZbb: # %bb.0:
+; RV64IZbb-NEXT: sext.h a0, a0
+; RV64IZbb-NEXT: mul a1, a1, a2
+; RV64IZbb-NEXT: sext.h a1, a1
+; RV64IZbb-NEXT: subw a0, a0, a1
+; RV64IZbb-NEXT: lui a1, 8
+; RV64IZbb-NEXT: addiw a1, a1, -1
+; RV64IZbb-NEXT: min a0, a0, a1
+; RV64IZbb-NEXT: lui a1, 1048568
+; RV64IZbb-NEXT: max a0, a0, a1
+; RV64IZbb-NEXT: ret
+ %a = mul i16 %y, %z
+ %tmp = call i16 @llvm.ssub.sat.i16(i16 %x, i16 %a)
+ ret i16 %tmp
+}
+
+define i8 @func8(i8 %x, i8 %y, i8 %z) nounwind {
+; RV64I-LABEL: func8:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a0, a0, 24
+; RV64I-NEXT: sraiw a0, a0, 24
+; RV64I-NEXT: mul a1, a1, a2
+; RV64I-NEXT: slli a1, a1, 24
+; RV64I-NEXT: sraiw a1, a1, 24
+; RV64I-NEXT: subw a0, a0, a1
+; RV64I-NEXT: li a1, 127
+; RV64I-NEXT: bge a0, a1, .LBB3_3
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: li a1, -127
+; RV64I-NEXT: blt a0, a1, .LBB3_4
+; RV64I-NEXT: .LBB3_2:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB3_3:
+; RV64I-NEXT: li a0, 127
+; RV64I-NEXT: li a1, -127
+; RV64I-NEXT: bge a0, a1, .LBB3_2
+; RV64I-NEXT: .LBB3_4:
+; RV64I-NEXT: li a0, -128
+; RV64I-NEXT: ret
+;
+; RV64IZbb-LABEL: func8:
+; RV64IZbb: # %bb.0:
+; RV64IZbb-NEXT: sext.b a0, a0
+; RV64IZbb-NEXT: mul a1, a1, a2
+; RV64IZbb-NEXT: sext.b a1, a1
+; RV64IZbb-NEXT: subw a0, a0, a1
+; RV64IZbb-NEXT: li a1, 127
+; RV64IZbb-NEXT: min a0, a0, a1
+; RV64IZbb-NEXT: li a1, -128
+; RV64IZbb-NEXT: max a0, a0, a1
+; RV64IZbb-NEXT: ret
+ %a = mul i8 %y, %z
+ %tmp = call i8 @llvm.ssub.sat.i8(i8 %x, i8 %a)
+ ret i8 %tmp
+}
+
+define i4 @func4(i4 %x, i4 %y, i4 %z) nounwind {
+; RV64I-LABEL: func4:
+; RV64I: # %bb.0:
+; RV64I-NEXT: slli a0, a0, 28
+; RV64I-NEXT: sraiw a0, a0, 28
+; RV64I-NEXT: mul a1, a1, a2
+; RV64I-NEXT: slli a1, a1, 28
+; RV64I-NEXT: sraiw a1, a1, 28
+; RV64I-NEXT: subw a0, a0, a1
+; RV64I-NEXT: li a1, 7
+; RV64I-NEXT: bge a0, a1, .LBB4_3
+; RV64I-NEXT: # %bb.1:
+; RV64I-NEXT: li a1, -7
+; RV64I-NEXT: blt a0, a1, .LBB4_4
+; RV64I-NEXT: .LBB4_2:
+; RV64I-NEXT: ret
+; RV64I-NEXT: .LBB4_3:
+; RV64I-NEXT: li a0, 7
+; RV64I-NEXT: li a1, -7
+; RV64I-NEXT: bge a0, a1, .LBB4_2
+; RV64I-NEXT: .LBB4_4:
+; RV64I-NEXT: li a0, -8
+; RV64I-NEXT: ret
+;
+; RV64IZbb-LABEL: func4:
+; RV64IZbb: # %bb.0:
+; RV64IZbb-NEXT: slli a0, a0, 28
+; RV64IZbb-NEXT: sraiw a0, a0, 28
+; RV64IZbb-NEXT: mul a1, a1, a2
+; RV64IZbb-NEXT: slli a1, a1, 28
+; RV64IZbb-NEXT: sraiw a1, a1, 28
+; RV64IZbb-NEXT: subw a0, a0, a1
+; RV64IZbb-NEXT: li a1, 7
+; RV64IZbb-NEXT: min a0, a0, a1
+; RV64IZbb-NEXT: li a1, -8
+; RV64IZbb-NEXT: max a0, a0, a1
+; RV64IZbb-NEXT: ret
+ %a = mul i4 %y, %z
+ %tmp = call i4 @llvm.ssub.sat.i4(i4 %x, i4 %a)
+ ret i4 %tmp
+}
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