[llvm] [X86][test] Remove useless pattern for VDPBF16PSZmb and add a test for broadcast folding (PR #80629)

[Shengchen Kan via llvm-commits]

https://github.com/KanRobert updated https://github.com/llvm/llvm-project/pull/80629

>From ef5f4c6f58bec9524d10aced8e1f4858230676bd Mon Sep 17 00:00:00 2001
From: Shengchen Kan <shengchen.kan at intel.com>
Date: Mon, 5 Feb 2024 10:56:36 +0800
Subject: [PATCH 1/2] [X86][test] Remove useless pattern for VDPBF16PSZmb and
 add a test for broadcast folding

llvm-issue: https://github.com/llvm/llvm-project/issues/68810
---
 llvm/lib/Target/X86/X86InstrAVX512.td   |  3 +--
 llvm/test/CodeGen/X86/fold-broadcast.ll | 18 ++++++++++++++++++
 2 files changed, 19 insertions(+), 2 deletions(-)
 create mode 100644 llvm/test/CodeGen/X86/fold-broadcast.ll

diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
index b588f660e2744..70d9b437b5fa9 100644
--- a/llvm/lib/Target/X86/X86InstrAVX512.td
+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -12721,8 +12721,7 @@ multiclass avx512_dpbf16ps_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
                   OpcodeStr,
                   !strconcat("${src3}", _.BroadcastStr,", $src2"),
                   !strconcat("$src2, ${src3}", _.BroadcastStr),
-                  (_.VT (OpNode _.RC:$src1, src_v.RC:$src2,
-                  (src_v.VT (src_v.BroadcastLdFrag addr:$src3))))>,
+                  (null_frag)>,
                   EVEX_B, EVEX, VVVV, Sched<[sched.Folded, sched.ReadAfterFold]>;
 
 }
diff --git a/llvm/test/CodeGen/X86/fold-broadcast.ll b/llvm/test/CodeGen/X86/fold-broadcast.ll
new file mode 100644
index 0000000000000..02c26487136ed
--- /dev/null
+++ b/llvm/test/CodeGen/X86/fold-broadcast.ll
@@ -0,0 +1,18 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+avx512bf16 < %s | FileCheck %s
+
+define <16 x float> @mm512_dpbf16_ps_broadcast_rhs(<16 x float> noundef %acc, <32 x bfloat> noundef %lhs, ptr nocapture noundef readonly %rhs) {
+; CHECK-LABEL: mm512_dpbf16_ps_broadcast_rhs:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vdpbf16ps (%rdi){1to16}, %zmm1, %zmm0
+; CHECK-NEXT:    retq
+entry:
+  %0 = load float, ptr %rhs, align 4
+  %vecinit.i = insertelement <16 x float> poison, float %0, i64 0
+  %vecinit15.i = shufflevector <16 x float> %vecinit.i, <16 x float> poison, <16 x i32> zeroinitializer
+  %1 = bitcast <16 x float> %vecinit15.i to <32 x bfloat>
+  %2 = tail call <16 x float> @llvm.x86.avx512bf16.dpbf16ps.512(<16 x float> %acc, <32 x bfloat> %lhs, <32 x bfloat> %1)
+  ret <16 x float> %2
+}
+
+declare <16 x float> @llvm.x86.avx512bf16.dpbf16ps.512(<16 x float>, <32 x bfloat>, <32 x bfloat>)

>From 1628d1a0b21141000ad46e3f6fdac465e37381e1 Mon Sep 17 00:00:00 2001
From: Shengchen Kan <shengchen.kan at intel.com>
Date: Mon, 5 Feb 2024 12:06:58 +0800
Subject: [PATCH 2/2] fix lit test resources-avx512bf16.s

---
 llvm/lib/Target/X86/X86InstrAVX512.td | 1 +
 1 file changed, 1 insertion(+)

diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td
index 70d9b437b5fa9..b610560f7fe4f 100644
--- a/llvm/lib/Target/X86/X86InstrAVX512.td
+++ b/llvm/lib/Target/X86/X86InstrAVX512.td
@@ -12716,6 +12716,7 @@ multiclass avx512_dpbf16ps_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
                                (src_v.LdFrag addr:$src3)))>, EVEX, VVVV,
                                Sched<[sched.Folded, sched.ReadAfterFold]>;
 
+  let mayLoad = 1, hasSideEffects = 0 in
   defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
                   (ins src_v.RC:$src2, f32mem:$src3),
                   OpcodeStr,