[llvm] 146e5ce - [RISCV] Add i32 zext.h pattern for -riscv-experimental-rv64-legal-i32.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-02-04T12:39:13-08:00
New Revision: 146e5ce481f3a9232f2188cc664a65e98f8a0985

URL: https://github.com/llvm/llvm-project/commit/146e5ce481f3a9232f2188cc664a65e98f8a0985
DIFF: https://github.com/llvm/llvm-project/commit/146e5ce481f3a9232f2188cc664a65e98f8a0985.diff

LOG: [RISCV] Add i32 zext.h pattern for -riscv-experimental-rv64-legal-i32.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
    llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll
    llvm/test/CodeGen/RISCV/rv64-legal-i32/uadd_sat_plus.ll
    llvm/test/CodeGen/RISCV/rv64-legal-i32/usub_sat_plus.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index 8055473a37c34..f8938c0a98d11 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -837,6 +837,8 @@ def : PatGpr<ctpop, CPOPW, i32>;
 
 def : Pat<(i32 (sext_inreg GPR:$rs1, i8)), (SEXT_B GPR:$rs1)>;
 def : Pat<(i32 (sext_inreg GPR:$rs1, i16)), (SEXT_H GPR:$rs1)>;
+
+def : Pat<(i32 (and GPR:$rs, 0xFFFF)), (ZEXT_H_RV64 GPR:$rs)>;
 } // Predicates = [HasStdExtZbb, IsRV64]
 
 let Predicates = [HasStdExtZbbOrZbkb, IsRV64] in {

diff  --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll
index 9b3f206be4a08..68ce66cbe8537 100644
--- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll
@@ -942,8 +942,7 @@ define i32 @zexth_i32(i32 %a) nounwind {
 ;
 ; RV64ZBB-LABEL: zexth_i32:
 ; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    slli a0, a0, 48
-; RV64ZBB-NEXT:    srli a0, a0, 48
+; RV64ZBB-NEXT:    zext.h a0, a0
 ; RV64ZBB-NEXT:    ret
   %and = and i32 %a, 65535
   ret i32 %and

diff  --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/uadd_sat_plus.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/uadd_sat_plus.ll
index 7aad0c3f22c8b..db8f3e19f64c6 100644
--- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/uadd_sat_plus.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/uadd_sat_plus.ll
@@ -71,13 +71,13 @@ define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {
 ;
 ; RV64IZbb-LABEL: func16:
 ; RV64IZbb:       # %bb.0:
-; RV64IZbb-NEXT:    lui a3, 16
-; RV64IZbb-NEXT:    addiw a3, a3, -1
-; RV64IZbb-NEXT:    and a0, a0, a3
+; RV64IZbb-NEXT:    zext.h a0, a0
 ; RV64IZbb-NEXT:    mul a1, a1, a2
-; RV64IZbb-NEXT:    and a1, a1, a3
+; RV64IZbb-NEXT:    zext.h a1, a1
 ; RV64IZbb-NEXT:    addw a0, a0, a1
-; RV64IZbb-NEXT:    minu a0, a0, a3
+; RV64IZbb-NEXT:    lui a1, 16
+; RV64IZbb-NEXT:    addiw a1, a1, -1
+; RV64IZbb-NEXT:    minu a0, a0, a1
 ; RV64IZbb-NEXT:    ret
   %a = mul i16 %y, %z
   %tmp = call i16 @llvm.uadd.sat.i16(i16 %x, i16 %a)

diff  --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/usub_sat_plus.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/usub_sat_plus.ll
index b95a77dc1f6b2..b12bd501f010b 100644
--- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/usub_sat_plus.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/usub_sat_plus.ll
@@ -69,12 +69,9 @@ define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {
 ;
 ; RV64IZbb-LABEL: func16:
 ; RV64IZbb:       # %bb.0:
-; RV64IZbb-NEXT:    lui a3, 16
-; RV64IZbb-NEXT:    addiw a3, a3, -1
-; RV64IZbb-NEXT:    and a0, a0, a3
-; RV64IZbb-NEXT:    mulw a1, a1, a2
-; RV64IZbb-NEXT:    and a1, a1, a3
-; RV64IZbb-NEXT:    sext.w a0, a0
+; RV64IZbb-NEXT:    zext.h a0, a0
+; RV64IZbb-NEXT:    mul a1, a1, a2
+; RV64IZbb-NEXT:    zext.h a1, a1
 ; RV64IZbb-NEXT:    maxu a0, a0, a1
 ; RV64IZbb-NEXT:    sub a0, a0, a1
 ; RV64IZbb-NEXT:    ret