[llvm] 9dfdea6 - [RISCV] Add XTheadMac patterns for -riscv-experimental-rv64-legal-i32.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Feb 3 19:43:09 PST 2024
Author: Craig Topper
Date: 2024-02-03T19:37:46-08:00
New Revision: 9dfdea6fbddfa871dab32c3322259babcc13dcdc
URL: https://github.com/llvm/llvm-project/commit/9dfdea6fbddfa871dab32c3322259babcc13dcdc
DIFF: https://github.com/llvm/llvm-project/commit/9dfdea6fbddfa871dab32c3322259babcc13dcdc.diff
LOG: [RISCV] Add XTheadMac patterns for -riscv-experimental-rv64-legal-i32.
Added:
llvm/test/CodeGen/RISCV/rv64-legal-i32/xtheadmac.ll
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 12c18068771c5..c00dfd8937da9 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1186,6 +1186,7 @@ def assertsexti32 : PatFrag<(ops node:$src), (assertsext node:$src), [{
return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLE(MVT::i32);
}]>;
def sexti16 : ComplexPattern<XLenVT, 1, "selectSExtBits<16>">;
+def sexti16i32 : ComplexPattern<i32, 1, "selectSExtBits<16>">;
def sexti32 : ComplexPattern<i64, 1, "selectSExtBits<32>">;
def assertzexti32 : PatFrag<(ops node:$src), (assertzext node:$src), [{
return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLE(MVT::i32);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
index 20b956878eeeb..ff474e4616bdb 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
@@ -935,3 +935,20 @@ def : Pat<(select (riscv_seteq (XLenVT GPR:$cond)), (i32 0), (i32 GPR:$b)),
def : Pat<(select (riscv_setne (XLenVT GPR:$cond)), (i32 0), (i32 GPR:$b)),
(TH_MVNEZ GPR:$b, (XLenVT X0), GPR:$cond)>;
} // Predicates = [HasVendorXTHeadCondMov]
+
+let Predicates = [HasVendorXTHeadMac, IsRV64] in {
+// mulaw, mulsw are available only in RV64.
+def : Pat<(i32 (add GPR:$rd, (mul GPR:$rs1, GPR:$rs2))),
+ (TH_MULAW GPR:$rd, GPR:$rs1, GPR:$rs2)>;
+def : Pat<(i32 (sub GPR:$rd, (mul GPR:$rs1, GPR:$rs2))),
+ (TH_MULSW GPR:$rd, GPR:$rs1, GPR:$rs2)>;
+// mulah, mulsh produce a sign-extended result.
+def : Pat<(i32 (add GPR:$rd,
+ (mul (sexti16i32 (i32 GPR:$rs1)),
+ (sexti16i32 (i32 GPR:$rs2))))),
+ (TH_MULAH GPR:$rd, GPR:$rs1, GPR:$rs2)>;
+def : Pat<(i32 (sub GPR:$rd,
+ (mul (sexti16i32 (i32 GPR:$rs1)),
+ (sexti16i32 (i32 GPR:$rs2))))),
+ (TH_MULSH GPR:$rd, GPR:$rs1, GPR:$rs2)>;
+}
diff --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/xtheadmac.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/xtheadmac.ll
new file mode 100644
index 0000000000000..63d1833287d6f
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/xtheadmac.ll
@@ -0,0 +1,123 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+xtheadmac -mattr=+m -verify-machineinstrs < %s \
+; RUN: -riscv-experimental-rv64-legal-i32 | FileCheck %s -check-prefix=RV64XTHEADMAC
+
+define i32 @mula_i32(i32 %a, i32 %b, i32 %c) {
+; RV64XTHEADMAC-LABEL: mula_i32:
+; RV64XTHEADMAC: # %bb.0:
+; RV64XTHEADMAC-NEXT: th.mulaw a0, a1, a2
+; RV64XTHEADMAC-NEXT: ret
+ %d = mul i32 %b, %c
+ %e = add i32 %a, %d
+ ret i32 %e
+}
+
+define i32 @muls_i32(i32 %a, i32 %b, i32 %c) {
+; RV64XTHEADMAC-LABEL: muls_i32:
+; RV64XTHEADMAC: # %bb.0:
+; RV64XTHEADMAC-NEXT: th.mulsw a0, a1, a2
+; RV64XTHEADMAC-NEXT: ret
+ %d = mul i32 %b, %c
+ %e = sub i32 %a, %d
+ ret i32 %e
+}
+
+define i64 @mula_i64(i64 %a, i64 %b, i64 %c) {
+; RV64XTHEADMAC-LABEL: mula_i64:
+; RV64XTHEADMAC: # %bb.0:
+; RV64XTHEADMAC-NEXT: th.mula a0, a1, a2
+; RV64XTHEADMAC-NEXT: ret
+ %d = mul i64 %b, %c
+ %f = add i64 %a, %d
+ ret i64 %f
+}
+
+define i64 @mulaw_i64(i32 %a, i32 %b, i32 %c) {
+; RV64XTHEADMAC-LABEL: mulaw_i64:
+; RV64XTHEADMAC: # %bb.0:
+; RV64XTHEADMAC-NEXT: th.mulaw a0, a1, a2
+; RV64XTHEADMAC-NEXT: ret
+ %d = mul i32 %b, %c
+ %e = add i32 %a, %d
+ %f = sext i32 %e to i64
+ ret i64 %f
+}
+
+define i64 @mulah_i64(i32 %a, i16 %b, i16 %c) {
+; RV64XTHEADMAC-LABEL: mulah_i64:
+; RV64XTHEADMAC: # %bb.0:
+; RV64XTHEADMAC-NEXT: th.mulah a0, a1, a2
+; RV64XTHEADMAC-NEXT: ret
+ %d = sext i16 %b to i32
+ %e = sext i16 %c to i32
+ %f = mul i32 %d, %e
+ %g = add i32 %a, %f
+ %h = sext i32 %g to i64
+ ret i64 %h
+}
+
+define i64 @muls_i64(i64 %a, i64 %b, i64 %c) {
+; RV64XTHEADMAC-LABEL: muls_i64:
+; RV64XTHEADMAC: # %bb.0:
+; RV64XTHEADMAC-NEXT: th.muls a0, a1, a2
+; RV64XTHEADMAC-NEXT: ret
+ %d = mul i64 %b, %c
+ %f = sub i64 %a, %d
+ ret i64 %f
+}
+
+define i64 @mulsw_i64(i32 %a, i32 %b, i32 %c) {
+; RV64XTHEADMAC-LABEL: mulsw_i64:
+; RV64XTHEADMAC: # %bb.0:
+; RV64XTHEADMAC-NEXT: th.mulsw a0, a1, a2
+; RV64XTHEADMAC-NEXT: ret
+ %d = mul i32 %b, %c
+ %e = sub i32 %a, %d
+ %f = sext i32 %e to i64
+ ret i64 %f
+}
+
+define i64 @mulsh_i64(i32 %a, i16 %b, i16 %c) {
+; RV64XTHEADMAC-LABEL: mulsh_i64:
+; RV64XTHEADMAC: # %bb.0:
+; RV64XTHEADMAC-NEXT: th.mulsh a0, a1, a2
+; RV64XTHEADMAC-NEXT: ret
+ %d = sext i16 %b to i32
+ %e = sext i16 %c to i32
+ %f = mul i32 %d, %e
+ %g = sub i32 %a, %f
+ %h = sext i32 %g to i64
+ ret i64 %h
+}
+
+define i32 @commutative1(i32 %A, i32 %B, i32 %C) {
+; RV64XTHEADMAC-LABEL: commutative1:
+; RV64XTHEADMAC: # %bb.0:
+; RV64XTHEADMAC-NEXT: th.mulaw a2, a1, a0
+; RV64XTHEADMAC-NEXT: mv a0, a2
+; RV64XTHEADMAC-NEXT: ret
+ %mul = mul nsw i32 %B, %A
+ %add = add i32 %mul, %C
+ ret i32 %add
+}
+
+define i32 @commutative2(i32 %A, i32 %B, i32 %C) {
+; RV64XTHEADMAC-LABEL: commutative2:
+; RV64XTHEADMAC: # %bb.0:
+; RV64XTHEADMAC-NEXT: th.mulaw a0, a1, a2
+; RV64XTHEADMAC-NEXT: ret
+ %mul = mul nsw i32 %B, %C
+ %add = add i32 %mul, %A
+ ret i32 %add
+}
+
+define i32 @commutative3(i32 %A, i32 %B, i32 %C) {
+; RV64XTHEADMAC-LABEL: commutative3:
+; RV64XTHEADMAC: # %bb.0:
+; RV64XTHEADMAC-NEXT: th.mulaw a1, a2, a0
+; RV64XTHEADMAC-NEXT: mv a0, a1
+; RV64XTHEADMAC-NEXT: ret
+ %mul = mul nsw i32 %C, %A
+ %add = add i32 %mul, %B
+ ret i32 %add
+}
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