[llvm] [RISCV] Add tests for reduce.fmaximum/fminimum. NFC (PR #80553)
Shih-Po Hung via llvm-commits
llvm-commits at lists.llvm.org
Sat Feb 3 08:59:47 PST 2024
https://github.com/arcbbb updated https://github.com/llvm/llvm-project/pull/80553
>From 9708b3b5dae5738e243212d1425b9e2aedcd76f9 Mon Sep 17 00:00:00 2001
From: ShihPo Hung <shihpo.hung at sifive.com>
Date: Sat, 3 Feb 2024 08:43:15 -0800
Subject: [PATCH 1/2] [RISCV] Add tests for reduce.fmaximum/fminimum. NFC
This is to add test coverage for crash report in #80340
---
.../CostModel/RISCV/reduce-fmaximum.ll | 77 +++++++++++++++++++
.../CostModel/RISCV/reduce-fminimum.ll | 77 +++++++++++++++++++
2 files changed, 154 insertions(+)
create mode 100644 llvm/test/Analysis/CostModel/RISCV/reduce-fmaximum.ll
create mode 100644 llvm/test/Analysis/CostModel/RISCV/reduce-fminimum.ll
diff --git a/llvm/test/Analysis/CostModel/RISCV/reduce-fmaximum.ll b/llvm/test/Analysis/CostModel/RISCV/reduce-fmaximum.ll
new file mode 100644
index 0000000000000..1618c3833a972
--- /dev/null
+++ b/llvm/test/Analysis/CostModel/RISCV/reduce-fmaximum.ll
@@ -0,0 +1,77 @@
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 4
+; RUN: opt < %s -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=256 -passes="print<cost-model>" -cost-kind=throughput 2>&1 -disable-output | FileCheck %s
+; RUN: opt < %s -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=256 -passes="print<cost-model>" -cost-kind=throughput 2>&1 -disable-output | FileCheck %s
+; RUN: opt < %s -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=256 -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output | FileCheck %s --check-prefix=SIZE
+; RUN: opt < %s -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=256 -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output | FileCheck %s --check-prefix=SIZE
+
+define float @reduce_fmaximum_f32(float %arg) {
+; CHECK-LABEL: 'reduce_fmaximum_f32'
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call float @llvm.vector.reduce.fmaximum.v2f32(<2 x float> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call float @llvm.vector.reduce.fmaximum.v4f32(<4 x float> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call float @llvm.vector.reduce.fmaximum.v8f32(<8 x float> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call float @llvm.vector.reduce.fmaximum.v16f32(<16 x float> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call float @llvm.vector.reduce.fmaximum.v32f32(<32 x float> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V64 = call float @llvm.vector.reduce.fmaximum.v64f32(<64 x float> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V128 = call float @llvm.vector.reduce.fmaximum.v128f32(<128 x float> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret float undef
+;
+; SIZE-LABEL: 'reduce_fmaximum_f32'
+; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call float @llvm.vector.reduce.fmaximum.v2f32(<2 x float> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4 = call float @llvm.vector.reduce.fmaximum.v4f32(<4 x float> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8 = call float @llvm.vector.reduce.fmaximum.v8f32(<8 x float> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16 = call float @llvm.vector.reduce.fmaximum.v16f32(<16 x float> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32 = call float @llvm.vector.reduce.fmaximum.v32f32(<32 x float> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V64 = call float @llvm.vector.reduce.fmaximum.v64f32(<64 x float> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V128 = call float @llvm.vector.reduce.fmaximum.v128f32(<128 x float> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret float undef
+;
+%V2 = call float @llvm.vector.reduce.fmaximum.v2f32(<2 x float> undef)
+%V4 = call float @llvm.vector.reduce.fmaximum.v4f32(<4 x float> undef)
+%V8 = call float @llvm.vector.reduce.fmaximum.v8f32(<8 x float> undef)
+%V16 = call float @llvm.vector.reduce.fmaximum.v16f32(<16 x float> undef)
+%V32 = call float @llvm.vector.reduce.fmaximum.v32f32(<32 x float> undef)
+%V64 = call float @llvm.vector.reduce.fmaximum.v64f32(<64 x float> undef)
+%V128 = call float @llvm.vector.reduce.fmaximum.v128f32(<128 x float> undef)
+ret float undef
+}
+declare float @llvm.vector.reduce.fmaximum.v2f32(<2 x float>)
+declare float @llvm.vector.reduce.fmaximum.v4f32(<4 x float>)
+declare float @llvm.vector.reduce.fmaximum.v8f32(<8 x float>)
+declare float @llvm.vector.reduce.fmaximum.v16f32(<16 x float>)
+declare float @llvm.vector.reduce.fmaximum.v32f32(<32 x float>)
+declare float @llvm.vector.reduce.fmaximum.v64f32(<64 x float>)
+declare float @llvm.vector.reduce.fmaximum.v128f32(<128 x float>)
+
+define double @reduce_fmaximum_f64(double %arg) {
+; CHECK-LABEL: 'reduce_fmaximum_f64'
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call double @llvm.vector.reduce.fmaximum.v2f64(<2 x double> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call double @llvm.vector.reduce.fmaximum.v4f64(<4 x double> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call double @llvm.vector.reduce.fmaximum.v8f64(<8 x double> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call double @llvm.vector.reduce.fmaximum.v16f64(<16 x double> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call double @llvm.vector.reduce.fmaximum.v32f64(<32 x double> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64 = call double @llvm.vector.reduce.fmaximum.v64f64(<64 x double> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret double undef
+;
+; SIZE-LABEL: 'reduce_fmaximum_f64'
+; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call double @llvm.vector.reduce.fmaximum.v2f64(<2 x double> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4 = call double @llvm.vector.reduce.fmaximum.v4f64(<4 x double> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8 = call double @llvm.vector.reduce.fmaximum.v8f64(<8 x double> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16 = call double @llvm.vector.reduce.fmaximum.v16f64(<16 x double> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32 = call double @llvm.vector.reduce.fmaximum.v32f64(<32 x double> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V64 = call double @llvm.vector.reduce.fmaximum.v64f64(<64 x double> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret double undef
+;
+%V2 = call double @llvm.vector.reduce.fmaximum.v2f64(<2 x double> undef)
+%V4 = call double @llvm.vector.reduce.fmaximum.v4f64(<4 x double> undef)
+%V8 = call double @llvm.vector.reduce.fmaximum.v8f64(<8 x double> undef)
+%V16 = call double @llvm.vector.reduce.fmaximum.v16f64(<16 x double> undef)
+%V32 = call double @llvm.vector.reduce.fmaximum.v32f64(<32 x double> undef)
+%V64 = call double @llvm.vector.reduce.fmaximum.v64f64(<64 x double> undef)
+ret double undef
+}
+declare double @llvm.vector.reduce.fmaximum.v2f64(<2 x double>)
+declare double @llvm.vector.reduce.fmaximum.v4f64(<4 x double>)
+declare double @llvm.vector.reduce.fmaximum.v8f64(<8 x double>)
+declare double @llvm.vector.reduce.fmaximum.v16f64(<16 x double>)
+declare double @llvm.vector.reduce.fmaximum.v32f64(<32 x double>)
+declare double @llvm.vector.reduce.fmaximum.v64f64(<64 x double>)
diff --git a/llvm/test/Analysis/CostModel/RISCV/reduce-fminimum.ll b/llvm/test/Analysis/CostModel/RISCV/reduce-fminimum.ll
new file mode 100644
index 0000000000000..35b18645b1f2d
--- /dev/null
+++ b/llvm/test/Analysis/CostModel/RISCV/reduce-fminimum.ll
@@ -0,0 +1,77 @@
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 4
+; RUN: opt < %s -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=256 -passes="print<cost-model>" -cost-kind=throughput 2>&1 -disable-output | FileCheck %s
+; RUN: opt < %s -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=256 -passes="print<cost-model>" -cost-kind=throughput 2>&1 -disable-output | FileCheck %s
+; RUN: opt < %s -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=256 -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output | FileCheck %s --check-prefix=SIZE
+; RUN: opt < %s -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=256 -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output | FileCheck %s --check-prefix=SIZE
+
+define float @reduce_fmaximum_f32(float %arg) {
+; CHECK-LABEL: 'reduce_fmaximum_f32'
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call float @llvm.vector.reduce.fminimum.v2f32(<2 x float> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call float @llvm.vector.reduce.fminimum.v4f32(<4 x float> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call float @llvm.vector.reduce.fminimum.v8f32(<8 x float> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call float @llvm.vector.reduce.fminimum.v16f32(<16 x float> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call float @llvm.vector.reduce.fminimum.v32f32(<32 x float> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V64 = call float @llvm.vector.reduce.fminimum.v64f32(<64 x float> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %V128 = call float @llvm.vector.reduce.fminimum.v128f32(<128 x float> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret float undef
+;
+; SIZE-LABEL: 'reduce_fmaximum_f32'
+; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call float @llvm.vector.reduce.fminimum.v2f32(<2 x float> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4 = call float @llvm.vector.reduce.fminimum.v4f32(<4 x float> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8 = call float @llvm.vector.reduce.fminimum.v8f32(<8 x float> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16 = call float @llvm.vector.reduce.fminimum.v16f32(<16 x float> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32 = call float @llvm.vector.reduce.fminimum.v32f32(<32 x float> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V64 = call float @llvm.vector.reduce.fminimum.v64f32(<64 x float> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V128 = call float @llvm.vector.reduce.fminimum.v128f32(<128 x float> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret float undef
+;
+%V2 = call float @llvm.vector.reduce.fminimum.v2f32(<2 x float> undef)
+%V4 = call float @llvm.vector.reduce.fminimum.v4f32(<4 x float> undef)
+%V8 = call float @llvm.vector.reduce.fminimum.v8f32(<8 x float> undef)
+%V16 = call float @llvm.vector.reduce.fminimum.v16f32(<16 x float> undef)
+%V32 = call float @llvm.vector.reduce.fminimum.v32f32(<32 x float> undef)
+%V64 = call float @llvm.vector.reduce.fminimum.v64f32(<64 x float> undef)
+%V128 = call float @llvm.vector.reduce.fminimum.v128f32(<128 x float> undef)
+ret float undef
+}
+declare float @llvm.vector.reduce.fminimum.v2f32(<2 x float>)
+declare float @llvm.vector.reduce.fminimum.v4f32(<4 x float>)
+declare float @llvm.vector.reduce.fminimum.v8f32(<8 x float>)
+declare float @llvm.vector.reduce.fminimum.v16f32(<16 x float>)
+declare float @llvm.vector.reduce.fminimum.v32f32(<32 x float>)
+declare float @llvm.vector.reduce.fminimum.v64f32(<64 x float>)
+declare float @llvm.vector.reduce.fminimum.v128f32(<128 x float>)
+
+define double @reduce_fmaximum_f64(double %arg) {
+; CHECK-LABEL: 'reduce_fmaximum_f64'
+; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V2 = call double @llvm.vector.reduce.fminimum.v2f64(<2 x double> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4 = call double @llvm.vector.reduce.fminimum.v4f64(<4 x double> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %V8 = call double @llvm.vector.reduce.fminimum.v8f64(<8 x double> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %V16 = call double @llvm.vector.reduce.fminimum.v16f64(<16 x double> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V32 = call double @llvm.vector.reduce.fminimum.v32f64(<32 x double> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %V64 = call double @llvm.vector.reduce.fminimum.v64f64(<64 x double> undef)
+; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret double undef
+;
+; SIZE-LABEL: 'reduce_fmaximum_f64'
+; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2 = call double @llvm.vector.reduce.fminimum.v2f64(<2 x double> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4 = call double @llvm.vector.reduce.fminimum.v4f64(<4 x double> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8 = call double @llvm.vector.reduce.fminimum.v8f64(<8 x double> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16 = call double @llvm.vector.reduce.fminimum.v16f64(<16 x double> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32 = call double @llvm.vector.reduce.fminimum.v32f64(<32 x double> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V64 = call double @llvm.vector.reduce.fminimum.v64f64(<64 x double> undef)
+; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret double undef
+;
+%V2 = call double @llvm.vector.reduce.fminimum.v2f64(<2 x double> undef)
+%V4 = call double @llvm.vector.reduce.fminimum.v4f64(<4 x double> undef)
+%V8 = call double @llvm.vector.reduce.fminimum.v8f64(<8 x double> undef)
+%V16 = call double @llvm.vector.reduce.fminimum.v16f64(<16 x double> undef)
+%V32 = call double @llvm.vector.reduce.fminimum.v32f64(<32 x double> undef)
+%V64 = call double @llvm.vector.reduce.fminimum.v64f64(<64 x double> undef)
+ret double undef
+}
+declare double @llvm.vector.reduce.fminimum.v2f64(<2 x double>)
+declare double @llvm.vector.reduce.fminimum.v4f64(<4 x double>)
+declare double @llvm.vector.reduce.fminimum.v8f64(<8 x double>)
+declare double @llvm.vector.reduce.fminimum.v16f64(<16 x double>)
+declare double @llvm.vector.reduce.fminimum.v32f64(<32 x double>)
+declare double @llvm.vector.reduce.fminimum.v64f64(<64 x double>)
>From e816a5e133e0518a68886b283f8f020c9ccd9b49 Mon Sep 17 00:00:00 2001
From: ShihPo Hung <shihpo.hung at sifive.com>
Date: Sat, 3 Feb 2024 08:59:17 -0800
Subject: [PATCH 2/2] Add codegen tests for reduce.fmaximum/fminimum
---
.../RISCV/rvv/fixed-vectors-reduction-fp.ll | 2656 +++++++++++++++++
1 file changed, 2656 insertions(+)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
index 95a4c9a249e7f..d12bd651a10c0 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
@@ -1592,3 +1592,2659 @@ define float @vreduce_nsz_fadd_v4f32(ptr %x, float %s) {
%red = call reassoc nsz float @llvm.vector.reduce.fadd.v4f32(float %s, <4 x float> %v)
ret float %red
}
+
+declare float @llvm.vector.reduce.fminimum.v2f32(<2 x float>)
+
+define float @vreduce_fminimum_v2f32(ptr %x) {
+; CHECK-LABEL: vreduce_fminimum_v2f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <2 x float>, ptr %x
+ %red = call float @llvm.vector.reduce.fminimum.v2f32(<2 x float> %v)
+ ret float %red
+}
+
+define float @vreduce_fminimum_v2f32_nonans(ptr %x) {
+; CHECK-LABEL: vreduce_fminimum_v2f32_nonans:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <2 x float>, ptr %x
+ %red = call nnan float @llvm.vector.reduce.fminimum.v2f32(<2 x float> %v)
+ ret float %red
+}
+
+declare float @llvm.vector.reduce.fminimum.v4f32(<4 x float>)
+
+define float @vreduce_fminimum_v4f32(ptr %x) {
+; CHECK-LABEL: vreduce_fminimum_v4f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v9, 2
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v9, v11, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <4 x float>, ptr %x
+ %red = call float @llvm.vector.reduce.fminimum.v4f32(<4 x float> %v)
+ ret float %red
+}
+
+define float @vreduce_fminimum_v4f32_nonans(ptr %x) {
+; CHECK-LABEL: vreduce_fminimum_v4f32_nonans:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v9, 2
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v9, v11, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <4 x float>, ptr %x
+ %red = call nnan float @llvm.vector.reduce.fminimum.v4f32(<4 x float> %v)
+ ret float %red
+}
+
+declare float @llvm.vector.reduce.fminimum.v8f32(<8 x float>)
+
+define float @vreduce_fminimum_v8f32(ptr %x) {
+; CHECK-LABEL: vreduce_fminimum_v8f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vle32.v v10, (a0)
+; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 4
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmin.vv v9, v9, v8
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v9, 2
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v9, v11, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <8 x float>, ptr %x
+ %red = call float @llvm.vector.reduce.fminimum.v8f32(<8 x float> %v)
+ ret float %red
+}
+
+define float @vreduce_fminimum_v8f32_nonans(ptr %x) {
+; CHECK-LABEL: vreduce_fminimum_v8f32_nonans:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vle32.v v10, (a0)
+; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 4
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmin.vv v9, v9, v8
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v9, 2
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v9, v11, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <8 x float>, ptr %x
+ %red = call nnan float @llvm.vector.reduce.fminimum.v8f32(<8 x float> %v)
+ ret float %red
+}
+
+declare float @llvm.vector.reduce.fminimum.v16f32(<16 x float>)
+
+define float @vreduce_fminimum_v16f32(ptr %x) {
+; CHECK-LABEL: vreduce_fminimum_v16f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vle32.v v12, (a0)
+; CHECK-NEXT: vsetivli zero, 8, e32, m4, ta, ma
+; CHECK-NEXT: vslidedown.vi v16, v12, 8
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v12, v12
+; CHECK-NEXT: vmerge.vvm v10, v16, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v12, v16, v0
+; CHECK-NEXT: vfmin.vv v10, v10, v8
+; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 4
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmin.vv v9, v9, v8
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v9, 2
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v9, v11, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <16 x float>, ptr %x
+ %red = call float @llvm.vector.reduce.fminimum.v16f32(<16 x float> %v)
+ ret float %red
+}
+
+define float @vreduce_fminimum_v16f32_nonans(ptr %x) {
+; CHECK-LABEL: vreduce_fminimum_v16f32_nonans:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vle32.v v12, (a0)
+; CHECK-NEXT: vsetivli zero, 8, e32, m4, ta, ma
+; CHECK-NEXT: vslidedown.vi v16, v12, 8
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v12, v12
+; CHECK-NEXT: vmerge.vvm v10, v16, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v12, v16, v0
+; CHECK-NEXT: vfmin.vv v10, v10, v8
+; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 4
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmin.vv v9, v9, v8
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v9, 2
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v9, v11, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <16 x float>, ptr %x
+ %red = call nnan float @llvm.vector.reduce.fminimum.v16f32(<16 x float> %v)
+ ret float %red
+}
+
+declare float @llvm.vector.reduce.fminimum.v32f32(<32 x float>)
+
+define float @vreduce_fminimum_v32f32(ptr %x) {
+; CHECK-LABEL: vreduce_fminimum_v32f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a1, 32
+; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
+; CHECK-NEXT: vle32.v v16, (a0)
+; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
+; CHECK-NEXT: vslidedown.vi v24, v16, 16
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
+; CHECK-NEXT: vmfeq.vv v8, v16, v16
+; CHECK-NEXT: vmerge.vvm v12, v24, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: vfmin.vv v12, v12, v8
+; CHECK-NEXT: vsetivli zero, 8, e32, m4, ta, ma
+; CHECK-NEXT: vslidedown.vi v16, v12, 8
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v12, v12
+; CHECK-NEXT: vmerge.vvm v10, v16, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v12, v16, v0
+; CHECK-NEXT: vfmin.vv v10, v10, v8
+; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 4
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmin.vv v9, v9, v8
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v9, 2
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v9, v11, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <32 x float>, ptr %x
+ %red = call float @llvm.vector.reduce.fminimum.v32f32(<32 x float> %v)
+ ret float %red
+}
+
+define float @vreduce_fminimum_v32f32_nonans(ptr %x) {
+; CHECK-LABEL: vreduce_fminimum_v32f32_nonans:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a1, 32
+; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
+; CHECK-NEXT: vle32.v v16, (a0)
+; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
+; CHECK-NEXT: vslidedown.vi v24, v16, 16
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
+; CHECK-NEXT: vmfeq.vv v8, v16, v16
+; CHECK-NEXT: vmerge.vvm v12, v24, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: vfmin.vv v12, v12, v8
+; CHECK-NEXT: vsetivli zero, 8, e32, m4, ta, ma
+; CHECK-NEXT: vslidedown.vi v16, v12, 8
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v12, v12
+; CHECK-NEXT: vmerge.vvm v10, v16, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v12, v16, v0
+; CHECK-NEXT: vfmin.vv v10, v10, v8
+; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 4
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmin.vv v9, v9, v8
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v9, 2
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v9, v11, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <32 x float>, ptr %x
+ %red = call nnan float @llvm.vector.reduce.fminimum.v32f32(<32 x float> %v)
+ ret float %red
+}
+
+declare float @llvm.vector.reduce.fminimum.v64f32(<64 x float>)
+
+define float @vreduce_fminimum_v64f32(ptr %x) {
+; CHECK-LABEL: vreduce_fminimum_v64f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: sub sp, sp, a1
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; CHECK-NEXT: addi a1, a0, 128
+; CHECK-NEXT: li a2, 32
+; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; CHECK-NEXT: vle32.v v16, (a0)
+; CHECK-NEXT: vle32.v v24, (a1)
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v1, v24, v24
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
+; CHECK-NEXT: vmv1r.v v0, v1
+; CHECK-NEXT: vmerge.vvm v8, v24, v16, v0
+; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
+; CHECK-NEXT: vfmin.vv v16, v8, v16
+; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
+; CHECK-NEXT: vslidedown.vi v24, v16, 16
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
+; CHECK-NEXT: vmfeq.vv v8, v16, v16
+; CHECK-NEXT: vmerge.vvm v12, v24, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: vfmin.vv v12, v12, v8
+; CHECK-NEXT: vsetivli zero, 8, e32, m4, ta, ma
+; CHECK-NEXT: vslidedown.vi v16, v12, 8
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v12, v12
+; CHECK-NEXT: vmerge.vvm v10, v16, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v12, v16, v0
+; CHECK-NEXT: vfmin.vv v10, v10, v8
+; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 4
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmin.vv v9, v9, v8
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v9, 2
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v9, v11, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add sp, sp, a0
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: ret
+ %v = load <64 x float>, ptr %x
+ %red = call float @llvm.vector.reduce.fminimum.v64f32(<64 x float> %v)
+ ret float %red
+}
+
+define float @vreduce_fminimum_v64f32_nonans(ptr %x) {
+; CHECK-LABEL: vreduce_fminimum_v64f32_nonans:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a1, 32
+; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: addi a0, a0, 128
+; CHECK-NEXT: vle32.v v16, (a0)
+; CHECK-NEXT: vfmin.vv v16, v8, v16
+; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
+; CHECK-NEXT: vslidedown.vi v24, v16, 16
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
+; CHECK-NEXT: vmfeq.vv v8, v16, v16
+; CHECK-NEXT: vmerge.vvm v12, v24, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: vfmin.vv v12, v12, v8
+; CHECK-NEXT: vsetivli zero, 8, e32, m4, ta, ma
+; CHECK-NEXT: vslidedown.vi v16, v12, 8
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v12, v12
+; CHECK-NEXT: vmerge.vvm v10, v16, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v12, v16, v0
+; CHECK-NEXT: vfmin.vv v10, v10, v8
+; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 4
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmin.vv v9, v9, v8
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v9, 2
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v9, v11, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <64 x float>, ptr %x
+ %red = call nnan float @llvm.vector.reduce.fminimum.v64f32(<64 x float> %v)
+ ret float %red
+}
+
+declare float @llvm.vector.reduce.fminimum.v128f32(<128 x float>)
+
+define float @vreduce_fminimum_v128f32(ptr %x) {
+; CHECK-LABEL: vreduce_fminimum_v128f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: li a2, 0
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a1, a1, a2
+; CHECK-NEXT: sub sp, sp, a1
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
+; CHECK-NEXT: li a1, 32
+; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
+; CHECK-NEXT: addi a1, a0, 128
+; CHECK-NEXT: vle32.v v16, (a1)
+; CHECK-NEXT: addi a1, a0, 384
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: addi a1, a0, 256
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vle32.v v24, (a0)
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
+; CHECK-NEXT: vmerge.vvm v24, v16, v8, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
+; CHECK-NEXT: vmfeq.vv v0, v8, v8
+; CHECK-NEXT: vle32.v v24, (a1)
+; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
+; CHECK-NEXT: vfmin.vv v8, v8, v16
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
+; CHECK-NEXT: vmfeq.vv v0, v8, v8
+; CHECK-NEXT: vmfeq.vv v1, v24, v24
+; CHECK-NEXT: vmerge.vvm v16, v8, v24, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
+; CHECK-NEXT: vmv1r.v v0, v1
+; CHECK-NEXT: vmerge.vvm v24, v24, v8, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
+; CHECK-NEXT: vfmin.vv v24, v24, v8
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
+; CHECK-NEXT: vmfeq.vv v1, v16, v16
+; CHECK-NEXT: vmerge.vvm v8, v24, v16, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
+; CHECK-NEXT: vmv1r.v v0, v1
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
+; CHECK-NEXT: vfmin.vv v16, v8, v16
+; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
+; CHECK-NEXT: vslidedown.vi v24, v16, 16
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
+; CHECK-NEXT: vmfeq.vv v8, v16, v16
+; CHECK-NEXT: vmerge.vvm v12, v24, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: vfmin.vv v12, v12, v8
+; CHECK-NEXT: vsetivli zero, 8, e32, m4, ta, ma
+; CHECK-NEXT: vslidedown.vi v16, v12, 8
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v12, v12
+; CHECK-NEXT: vmerge.vvm v10, v16, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v12, v16, v0
+; CHECK-NEXT: vfmin.vv v10, v10, v8
+; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 4
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmin.vv v9, v9, v8
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v9, 2
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v9, v11, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a1, 0
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a1, a1, a0
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: add sp, sp, a0
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: ret
+ %v = load <128 x float>, ptr %x
+ %red = call float @llvm.vector.reduce.fminimum.v128f32(<128 x float> %v)
+ ret float %red
+}
+
+define float @vreduce_fminimum_v128f32_nonans(ptr %x) {
+; CHECK-LABEL: vreduce_fminimum_v128f32_nonans:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a1, 32
+; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: addi a1, a0, 384
+; CHECK-NEXT: vle32.v v16, (a1)
+; CHECK-NEXT: addi a1, a0, 256
+; CHECK-NEXT: addi a0, a0, 128
+; CHECK-NEXT: vle32.v v24, (a0)
+; CHECK-NEXT: vle32.v v0, (a1)
+; CHECK-NEXT: vfmin.vv v16, v24, v16
+; CHECK-NEXT: vfmin.vv v8, v8, v0
+; CHECK-NEXT: vfmin.vv v16, v8, v16
+; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
+; CHECK-NEXT: vslidedown.vi v24, v16, 16
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
+; CHECK-NEXT: vmfeq.vv v8, v16, v16
+; CHECK-NEXT: vmerge.vvm v12, v24, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: vfmin.vv v12, v12, v8
+; CHECK-NEXT: vsetivli zero, 8, e32, m4, ta, ma
+; CHECK-NEXT: vslidedown.vi v16, v12, 8
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v12, v12
+; CHECK-NEXT: vmerge.vvm v10, v16, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v12, v16, v0
+; CHECK-NEXT: vfmin.vv v10, v10, v8
+; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 4
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmin.vv v9, v9, v8
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v9, 2
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v9, v11, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <128 x float>, ptr %x
+ %red = call nnan float @llvm.vector.reduce.fminimum.v128f32(<128 x float> %v)
+ ret float %red
+}
+
+declare double @llvm.vector.reduce.fminimum.v2f64(<2 x double>)
+
+define double @vreduce_fminimum_v2f64(ptr %x) {
+; CHECK-LABEL: vreduce_fminimum_v2f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vle64.v v9, (a0)
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <2 x double>, ptr %x
+ %red = call double @llvm.vector.reduce.fminimum.v2f64(<2 x double> %v)
+ ret double %red
+}
+
+define double @vreduce_fminimum_v2f64_nonans(ptr %x) {
+; CHECK-LABEL: vreduce_fminimum_v2f64_nonans:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vle64.v v9, (a0)
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <2 x double>, ptr %x
+ %red = call nnan double @llvm.vector.reduce.fminimum.v2f64(<2 x double> %v)
+ ret double %red
+}
+
+declare double @llvm.vector.reduce.fminimum.v4f64(<4 x double>)
+
+define double @vreduce_fminimum_v4f64(ptr %x) {
+; CHECK-LABEL: vreduce_fminimum_v4f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vle64.v v10, (a0)
+; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 2
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmin.vv v9, v9, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <4 x double>, ptr %x
+ %red = call double @llvm.vector.reduce.fminimum.v4f64(<4 x double> %v)
+ ret double %red
+}
+
+define double @vreduce_fminimum_v4f64_nonans(ptr %x) {
+; CHECK-LABEL: vreduce_fminimum_v4f64_nonans:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vle64.v v10, (a0)
+; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 2
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmin.vv v9, v9, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <4 x double>, ptr %x
+ %red = call nnan double @llvm.vector.reduce.fminimum.v4f64(<4 x double> %v)
+ ret double %red
+}
+
+declare double @llvm.vector.reduce.fminimum.v8f64(<8 x double>)
+
+define double @vreduce_fminimum_v8f64(ptr %x) {
+; CHECK-LABEL: vreduce_fminimum_v8f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; CHECK-NEXT: vle64.v v12, (a0)
+; CHECK-NEXT: vsetivli zero, 4, e64, m4, ta, ma
+; CHECK-NEXT: vslidedown.vi v16, v12, 4
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v12, v12
+; CHECK-NEXT: vmerge.vvm v10, v16, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v12, v16, v0
+; CHECK-NEXT: vfmin.vv v10, v10, v8
+; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 2
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmin.vv v9, v9, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <8 x double>, ptr %x
+ %red = call double @llvm.vector.reduce.fminimum.v8f64(<8 x double> %v)
+ ret double %red
+}
+
+define double @vreduce_fminimum_v8f64_nonans(ptr %x) {
+; CHECK-LABEL: vreduce_fminimum_v8f64_nonans:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; CHECK-NEXT: vle64.v v12, (a0)
+; CHECK-NEXT: vsetivli zero, 4, e64, m4, ta, ma
+; CHECK-NEXT: vslidedown.vi v16, v12, 4
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v12, v12
+; CHECK-NEXT: vmerge.vvm v10, v16, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v12, v16, v0
+; CHECK-NEXT: vfmin.vv v10, v10, v8
+; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 2
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmin.vv v9, v9, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <8 x double>, ptr %x
+ %red = call nnan double @llvm.vector.reduce.fminimum.v8f64(<8 x double> %v)
+ ret double %red
+}
+
+declare double @llvm.vector.reduce.fminimum.v16f64(<16 x double>)
+
+define double @vreduce_fminimum_v16f64(ptr %x) {
+; CHECK-LABEL: vreduce_fminimum_v16f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; CHECK-NEXT: vle64.v v16, (a0)
+; CHECK-NEXT: vsetivli zero, 8, e64, m8, ta, ma
+; CHECK-NEXT: vslidedown.vi v24, v16, 8
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
+; CHECK-NEXT: vmfeq.vv v8, v16, v16
+; CHECK-NEXT: vmerge.vvm v12, v24, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: vfmin.vv v12, v12, v8
+; CHECK-NEXT: vsetivli zero, 4, e64, m4, ta, ma
+; CHECK-NEXT: vslidedown.vi v16, v12, 4
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v12, v12
+; CHECK-NEXT: vmerge.vvm v10, v16, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v12, v16, v0
+; CHECK-NEXT: vfmin.vv v10, v10, v8
+; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 2
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmin.vv v9, v9, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <16 x double>, ptr %x
+ %red = call double @llvm.vector.reduce.fminimum.v16f64(<16 x double> %v)
+ ret double %red
+}
+
+define double @vreduce_fminimum_v16f64_nonans(ptr %x) {
+; CHECK-LABEL: vreduce_fminimum_v16f64_nonans:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; CHECK-NEXT: vle64.v v16, (a0)
+; CHECK-NEXT: vsetivli zero, 8, e64, m8, ta, ma
+; CHECK-NEXT: vslidedown.vi v24, v16, 8
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
+; CHECK-NEXT: vmfeq.vv v8, v16, v16
+; CHECK-NEXT: vmerge.vvm v12, v24, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: vfmin.vv v12, v12, v8
+; CHECK-NEXT: vsetivli zero, 4, e64, m4, ta, ma
+; CHECK-NEXT: vslidedown.vi v16, v12, 4
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v12, v12
+; CHECK-NEXT: vmerge.vvm v10, v16, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v12, v16, v0
+; CHECK-NEXT: vfmin.vv v10, v10, v8
+; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 2
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmin.vv v9, v9, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <16 x double>, ptr %x
+ %red = call nnan double @llvm.vector.reduce.fminimum.v16f64(<16 x double> %v)
+ ret double %red
+}
+
+declare double @llvm.vector.reduce.fminimum.v32f64(<32 x double>)
+
+define double @vreduce_fminimum_v32f64(ptr %x) {
+; CHECK-LABEL: vreduce_fminimum_v32f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: sub sp, sp, a1
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; CHECK-NEXT: addi a1, a0, 128
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; CHECK-NEXT: vle64.v v16, (a0)
+; CHECK-NEXT: vle64.v v24, (a1)
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v1, v24, v24
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
+; CHECK-NEXT: vmv1r.v v0, v1
+; CHECK-NEXT: vmerge.vvm v8, v24, v16, v0
+; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
+; CHECK-NEXT: vfmin.vv v16, v8, v16
+; CHECK-NEXT: vsetivli zero, 8, e64, m8, ta, ma
+; CHECK-NEXT: vslidedown.vi v24, v16, 8
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
+; CHECK-NEXT: vmfeq.vv v8, v16, v16
+; CHECK-NEXT: vmerge.vvm v12, v24, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: vfmin.vv v12, v12, v8
+; CHECK-NEXT: vsetivli zero, 4, e64, m4, ta, ma
+; CHECK-NEXT: vslidedown.vi v16, v12, 4
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v12, v12
+; CHECK-NEXT: vmerge.vvm v10, v16, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v12, v16, v0
+; CHECK-NEXT: vfmin.vv v10, v10, v8
+; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 2
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmin.vv v9, v9, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add sp, sp, a0
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: ret
+ %v = load <32 x double>, ptr %x
+ %red = call double @llvm.vector.reduce.fminimum.v32f64(<32 x double> %v)
+ ret double %red
+}
+
+define double @vreduce_fminimum_v32f64_nonans(ptr %x) {
+; CHECK-LABEL: vreduce_fminimum_v32f64_nonans:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: addi a0, a0, 128
+; CHECK-NEXT: vle64.v v16, (a0)
+; CHECK-NEXT: vfmin.vv v16, v8, v16
+; CHECK-NEXT: vsetivli zero, 8, e64, m8, ta, ma
+; CHECK-NEXT: vslidedown.vi v24, v16, 8
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
+; CHECK-NEXT: vmfeq.vv v8, v16, v16
+; CHECK-NEXT: vmerge.vvm v12, v24, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: vfmin.vv v12, v12, v8
+; CHECK-NEXT: vsetivli zero, 4, e64, m4, ta, ma
+; CHECK-NEXT: vslidedown.vi v16, v12, 4
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v12, v12
+; CHECK-NEXT: vmerge.vvm v10, v16, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v12, v16, v0
+; CHECK-NEXT: vfmin.vv v10, v10, v8
+; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 2
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmin.vv v9, v9, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <32 x double>, ptr %x
+ %red = call nnan double @llvm.vector.reduce.fminimum.v32f64(<32 x double> %v)
+ ret double %red
+}
+
+declare double @llvm.vector.reduce.fminimum.v64f64(<64 x double>)
+
+define double @vreduce_fminimum_v64f64(ptr %x) {
+; CHECK-LABEL: vreduce_fminimum_v64f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: li a2, 0
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a1, a1, a2
+; CHECK-NEXT: sub sp, sp, a1
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; CHECK-NEXT: addi a1, a0, 128
+; CHECK-NEXT: vle64.v v16, (a1)
+; CHECK-NEXT: addi a1, a0, 384
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: addi a1, a0, 256
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vle64.v v24, (a0)
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
+; CHECK-NEXT: vmerge.vvm v24, v16, v8, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
+; CHECK-NEXT: vmfeq.vv v0, v8, v8
+; CHECK-NEXT: vle64.v v24, (a1)
+; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
+; CHECK-NEXT: vfmin.vv v8, v8, v16
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
+; CHECK-NEXT: vmfeq.vv v0, v8, v8
+; CHECK-NEXT: vmfeq.vv v1, v24, v24
+; CHECK-NEXT: vmerge.vvm v16, v8, v24, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
+; CHECK-NEXT: vmv1r.v v0, v1
+; CHECK-NEXT: vmerge.vvm v24, v24, v8, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
+; CHECK-NEXT: vfmin.vv v24, v24, v8
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
+; CHECK-NEXT: vmfeq.vv v1, v16, v16
+; CHECK-NEXT: vmerge.vvm v8, v24, v16, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
+; CHECK-NEXT: vmv1r.v v0, v1
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
+; CHECK-NEXT: vfmin.vv v16, v8, v16
+; CHECK-NEXT: vsetivli zero, 8, e64, m8, ta, ma
+; CHECK-NEXT: vslidedown.vi v24, v16, 8
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
+; CHECK-NEXT: vmfeq.vv v8, v16, v16
+; CHECK-NEXT: vmerge.vvm v12, v24, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: vfmin.vv v12, v12, v8
+; CHECK-NEXT: vsetivli zero, 4, e64, m4, ta, ma
+; CHECK-NEXT: vslidedown.vi v16, v12, 4
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v12, v12
+; CHECK-NEXT: vmerge.vvm v10, v16, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v12, v16, v0
+; CHECK-NEXT: vfmin.vv v10, v10, v8
+; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 2
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmin.vv v9, v9, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a1, 0
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a1, a1, a0
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: add sp, sp, a0
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: ret
+ %v = load <64 x double>, ptr %x
+ %red = call double @llvm.vector.reduce.fminimum.v64f64(<64 x double> %v)
+ ret double %red
+}
+
+define double @vreduce_fminimum_v64f64_nonans(ptr %x) {
+; CHECK-LABEL: vreduce_fminimum_v64f64_nonans:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: addi a1, a0, 384
+; CHECK-NEXT: vle64.v v16, (a1)
+; CHECK-NEXT: addi a1, a0, 256
+; CHECK-NEXT: addi a0, a0, 128
+; CHECK-NEXT: vle64.v v24, (a0)
+; CHECK-NEXT: vle64.v v0, (a1)
+; CHECK-NEXT: vfmin.vv v16, v24, v16
+; CHECK-NEXT: vfmin.vv v8, v8, v0
+; CHECK-NEXT: vfmin.vv v16, v8, v16
+; CHECK-NEXT: vsetivli zero, 8, e64, m8, ta, ma
+; CHECK-NEXT: vslidedown.vi v24, v16, 8
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
+; CHECK-NEXT: vmfeq.vv v8, v16, v16
+; CHECK-NEXT: vmerge.vvm v12, v24, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: vfmin.vv v12, v12, v8
+; CHECK-NEXT: vsetivli zero, 4, e64, m4, ta, ma
+; CHECK-NEXT: vslidedown.vi v16, v12, 4
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v12, v12
+; CHECK-NEXT: vmerge.vvm v10, v16, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v12, v16, v0
+; CHECK-NEXT: vfmin.vv v10, v10, v8
+; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 2
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmin.vv v9, v9, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmin.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <64 x double>, ptr %x
+ %red = call nnan double @llvm.vector.reduce.fminimum.v64f64(<64 x double> %v)
+ ret double %red
+}
+
+declare float @llvm.vector.reduce.fmaximum.v2f32(<2 x float>)
+
+define float @vreduce_fmaximum_v2f32(ptr %x) {
+; CHECK-LABEL: vreduce_fmaximum_v2f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <2 x float>, ptr %x
+ %red = call float @llvm.vector.reduce.fmaximum.v2f32(<2 x float> %v)
+ ret float %red
+}
+
+define float @vreduce_fmaximum_v2f32_nonans(ptr %x) {
+; CHECK-LABEL: vreduce_fmaximum_v2f32_nonans:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <2 x float>, ptr %x
+ %red = call nnan float @llvm.vector.reduce.fmaximum.v2f32(<2 x float> %v)
+ ret float %red
+}
+
+declare float @llvm.vector.reduce.fmaximum.v4f32(<4 x float>)
+
+define float @vreduce_fmaximum_v4f32(ptr %x) {
+; CHECK-LABEL: vreduce_fmaximum_v4f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v9, 2
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v9, v11, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <4 x float>, ptr %x
+ %red = call float @llvm.vector.reduce.fmaximum.v4f32(<4 x float> %v)
+ ret float %red
+}
+
+define float @vreduce_fmaximum_v4f32_nonans(ptr %x) {
+; CHECK-LABEL: vreduce_fmaximum_v4f32_nonans:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v9, 2
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v9, v11, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <4 x float>, ptr %x
+ %red = call nnan float @llvm.vector.reduce.fmaximum.v4f32(<4 x float> %v)
+ ret float %red
+}
+
+declare float @llvm.vector.reduce.fmaximum.v8f32(<8 x float>)
+
+define float @vreduce_fmaximum_v8f32(ptr %x) {
+; CHECK-LABEL: vreduce_fmaximum_v8f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vle32.v v10, (a0)
+; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 4
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmax.vv v9, v9, v8
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v9, 2
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v9, v11, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <8 x float>, ptr %x
+ %red = call float @llvm.vector.reduce.fmaximum.v8f32(<8 x float> %v)
+ ret float %red
+}
+
+define float @vreduce_fmaximum_v8f32_nonans(ptr %x) {
+; CHECK-LABEL: vreduce_fmaximum_v8f32_nonans:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vle32.v v10, (a0)
+; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 4
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmax.vv v9, v9, v8
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v9, 2
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v9, v11, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <8 x float>, ptr %x
+ %red = call nnan float @llvm.vector.reduce.fmaximum.v8f32(<8 x float> %v)
+ ret float %red
+}
+
+declare float @llvm.vector.reduce.fmaximum.v16f32(<16 x float>)
+
+define float @vreduce_fmaximum_v16f32(ptr %x) {
+; CHECK-LABEL: vreduce_fmaximum_v16f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vle32.v v12, (a0)
+; CHECK-NEXT: vsetivli zero, 8, e32, m4, ta, ma
+; CHECK-NEXT: vslidedown.vi v16, v12, 8
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v12, v12
+; CHECK-NEXT: vmerge.vvm v10, v16, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v12, v16, v0
+; CHECK-NEXT: vfmax.vv v10, v10, v8
+; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 4
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmax.vv v9, v9, v8
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v9, 2
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v9, v11, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <16 x float>, ptr %x
+ %red = call float @llvm.vector.reduce.fmaximum.v16f32(<16 x float> %v)
+ ret float %red
+}
+
+define float @vreduce_fmaximum_v16f32_nonans(ptr %x) {
+; CHECK-LABEL: vreduce_fmaximum_v16f32_nonans:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vle32.v v12, (a0)
+; CHECK-NEXT: vsetivli zero, 8, e32, m4, ta, ma
+; CHECK-NEXT: vslidedown.vi v16, v12, 8
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v12, v12
+; CHECK-NEXT: vmerge.vvm v10, v16, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v12, v16, v0
+; CHECK-NEXT: vfmax.vv v10, v10, v8
+; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 4
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmax.vv v9, v9, v8
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v9, 2
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v9, v11, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <16 x float>, ptr %x
+ %red = call nnan float @llvm.vector.reduce.fmaximum.v16f32(<16 x float> %v)
+ ret float %red
+}
+
+declare float @llvm.vector.reduce.fmaximum.v32f32(<32 x float>)
+
+define float @vreduce_fmaximum_v32f32(ptr %x) {
+; CHECK-LABEL: vreduce_fmaximum_v32f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a1, 32
+; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
+; CHECK-NEXT: vle32.v v16, (a0)
+; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
+; CHECK-NEXT: vslidedown.vi v24, v16, 16
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
+; CHECK-NEXT: vmfeq.vv v8, v16, v16
+; CHECK-NEXT: vmerge.vvm v12, v24, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: vfmax.vv v12, v12, v8
+; CHECK-NEXT: vsetivli zero, 8, e32, m4, ta, ma
+; CHECK-NEXT: vslidedown.vi v16, v12, 8
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v12, v12
+; CHECK-NEXT: vmerge.vvm v10, v16, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v12, v16, v0
+; CHECK-NEXT: vfmax.vv v10, v10, v8
+; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 4
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmax.vv v9, v9, v8
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v9, 2
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v9, v11, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <32 x float>, ptr %x
+ %red = call float @llvm.vector.reduce.fmaximum.v32f32(<32 x float> %v)
+ ret float %red
+}
+
+define float @vreduce_fmaximum_v32f32_nonans(ptr %x) {
+; CHECK-LABEL: vreduce_fmaximum_v32f32_nonans:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a1, 32
+; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
+; CHECK-NEXT: vle32.v v16, (a0)
+; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
+; CHECK-NEXT: vslidedown.vi v24, v16, 16
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
+; CHECK-NEXT: vmfeq.vv v8, v16, v16
+; CHECK-NEXT: vmerge.vvm v12, v24, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: vfmax.vv v12, v12, v8
+; CHECK-NEXT: vsetivli zero, 8, e32, m4, ta, ma
+; CHECK-NEXT: vslidedown.vi v16, v12, 8
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v12, v12
+; CHECK-NEXT: vmerge.vvm v10, v16, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v12, v16, v0
+; CHECK-NEXT: vfmax.vv v10, v10, v8
+; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 4
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmax.vv v9, v9, v8
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v9, 2
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v9, v11, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <32 x float>, ptr %x
+ %red = call nnan float @llvm.vector.reduce.fmaximum.v32f32(<32 x float> %v)
+ ret float %red
+}
+
+declare float @llvm.vector.reduce.fmaximum.v64f32(<64 x float>)
+
+define float @vreduce_fmaximum_v64f32(ptr %x) {
+; CHECK-LABEL: vreduce_fmaximum_v64f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: sub sp, sp, a1
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; CHECK-NEXT: addi a1, a0, 128
+; CHECK-NEXT: li a2, 32
+; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
+; CHECK-NEXT: vle32.v v16, (a0)
+; CHECK-NEXT: vle32.v v24, (a1)
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v1, v24, v24
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
+; CHECK-NEXT: vmv1r.v v0, v1
+; CHECK-NEXT: vmerge.vvm v8, v24, v16, v0
+; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
+; CHECK-NEXT: vfmax.vv v16, v8, v16
+; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
+; CHECK-NEXT: vslidedown.vi v24, v16, 16
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
+; CHECK-NEXT: vmfeq.vv v8, v16, v16
+; CHECK-NEXT: vmerge.vvm v12, v24, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: vfmax.vv v12, v12, v8
+; CHECK-NEXT: vsetivli zero, 8, e32, m4, ta, ma
+; CHECK-NEXT: vslidedown.vi v16, v12, 8
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v12, v12
+; CHECK-NEXT: vmerge.vvm v10, v16, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v12, v16, v0
+; CHECK-NEXT: vfmax.vv v10, v10, v8
+; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 4
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmax.vv v9, v9, v8
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v9, 2
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v9, v11, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add sp, sp, a0
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: ret
+ %v = load <64 x float>, ptr %x
+ %red = call float @llvm.vector.reduce.fmaximum.v64f32(<64 x float> %v)
+ ret float %red
+}
+
+define float @vreduce_fmaximum_v64f32_nonans(ptr %x) {
+; CHECK-LABEL: vreduce_fmaximum_v64f32_nonans:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a1, 32
+; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: addi a0, a0, 128
+; CHECK-NEXT: vle32.v v16, (a0)
+; CHECK-NEXT: vfmax.vv v16, v8, v16
+; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
+; CHECK-NEXT: vslidedown.vi v24, v16, 16
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
+; CHECK-NEXT: vmfeq.vv v8, v16, v16
+; CHECK-NEXT: vmerge.vvm v12, v24, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: vfmax.vv v12, v12, v8
+; CHECK-NEXT: vsetivli zero, 8, e32, m4, ta, ma
+; CHECK-NEXT: vslidedown.vi v16, v12, 8
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v12, v12
+; CHECK-NEXT: vmerge.vvm v10, v16, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v12, v16, v0
+; CHECK-NEXT: vfmax.vv v10, v10, v8
+; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 4
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmax.vv v9, v9, v8
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v9, 2
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v9, v11, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <64 x float>, ptr %x
+ %red = call nnan float @llvm.vector.reduce.fmaximum.v64f32(<64 x float> %v)
+ ret float %red
+}
+
+declare float @llvm.vector.reduce.fmaximum.v128f32(<128 x float>)
+
+define float @vreduce_fmaximum_v128f32(ptr %x) {
+; CHECK-LABEL: vreduce_fmaximum_v128f32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: li a2, 0
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a1, a1, a2
+; CHECK-NEXT: sub sp, sp, a1
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
+; CHECK-NEXT: li a1, 32
+; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
+; CHECK-NEXT: addi a1, a0, 128
+; CHECK-NEXT: vle32.v v16, (a1)
+; CHECK-NEXT: addi a1, a0, 384
+; CHECK-NEXT: vle32.v v8, (a1)
+; CHECK-NEXT: addi a1, a0, 256
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vle32.v v24, (a0)
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
+; CHECK-NEXT: vmerge.vvm v24, v16, v8, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
+; CHECK-NEXT: vmfeq.vv v0, v8, v8
+; CHECK-NEXT: vle32.v v24, (a1)
+; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
+; CHECK-NEXT: vfmax.vv v8, v8, v16
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
+; CHECK-NEXT: vmfeq.vv v0, v8, v8
+; CHECK-NEXT: vmfeq.vv v1, v24, v24
+; CHECK-NEXT: vmerge.vvm v16, v8, v24, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
+; CHECK-NEXT: vmv1r.v v0, v1
+; CHECK-NEXT: vmerge.vvm v24, v24, v8, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
+; CHECK-NEXT: vfmax.vv v24, v24, v8
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
+; CHECK-NEXT: vmfeq.vv v1, v16, v16
+; CHECK-NEXT: vmerge.vvm v8, v24, v16, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
+; CHECK-NEXT: vmv1r.v v0, v1
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
+; CHECK-NEXT: vfmax.vv v16, v8, v16
+; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
+; CHECK-NEXT: vslidedown.vi v24, v16, 16
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
+; CHECK-NEXT: vmfeq.vv v8, v16, v16
+; CHECK-NEXT: vmerge.vvm v12, v24, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: vfmax.vv v12, v12, v8
+; CHECK-NEXT: vsetivli zero, 8, e32, m4, ta, ma
+; CHECK-NEXT: vslidedown.vi v16, v12, 8
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v12, v12
+; CHECK-NEXT: vmerge.vvm v10, v16, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v12, v16, v0
+; CHECK-NEXT: vfmax.vv v10, v10, v8
+; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 4
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmax.vv v9, v9, v8
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v9, 2
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v9, v11, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a1, 0
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a1, a1, a0
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: add sp, sp, a0
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: ret
+ %v = load <128 x float>, ptr %x
+ %red = call float @llvm.vector.reduce.fmaximum.v128f32(<128 x float> %v)
+ ret float %red
+}
+
+define float @vreduce_fmaximum_v128f32_nonans(ptr %x) {
+; CHECK-LABEL: vreduce_fmaximum_v128f32_nonans:
+; CHECK: # %bb.0:
+; CHECK-NEXT: li a1, 32
+; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
+; CHECK-NEXT: vle32.v v8, (a0)
+; CHECK-NEXT: addi a1, a0, 384
+; CHECK-NEXT: vle32.v v16, (a1)
+; CHECK-NEXT: addi a1, a0, 256
+; CHECK-NEXT: addi a0, a0, 128
+; CHECK-NEXT: vle32.v v24, (a0)
+; CHECK-NEXT: vle32.v v0, (a1)
+; CHECK-NEXT: vfmax.vv v16, v24, v16
+; CHECK-NEXT: vfmax.vv v8, v8, v0
+; CHECK-NEXT: vfmax.vv v16, v8, v16
+; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
+; CHECK-NEXT: vslidedown.vi v24, v16, 16
+; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
+; CHECK-NEXT: vmfeq.vv v8, v16, v16
+; CHECK-NEXT: vmerge.vvm v12, v24, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: vfmax.vv v12, v12, v8
+; CHECK-NEXT: vsetivli zero, 8, e32, m4, ta, ma
+; CHECK-NEXT: vslidedown.vi v16, v12, 8
+; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v12, v12
+; CHECK-NEXT: vmerge.vvm v10, v16, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v12, v16, v0
+; CHECK-NEXT: vfmax.vv v10, v10, v8
+; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 4
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmax.vv v9, v9, v8
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
+; CHECK-NEXT: vslidedown.vi v10, v9, 2
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v9, v11, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <128 x float>, ptr %x
+ %red = call nnan float @llvm.vector.reduce.fmaximum.v128f32(<128 x float> %v)
+ ret float %red
+}
+
+declare double @llvm.vector.reduce.fmaximum.v2f64(<2 x double>)
+
+define double @vreduce_fmaximum_v2f64(ptr %x) {
+; CHECK-LABEL: vreduce_fmaximum_v2f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vle64.v v9, (a0)
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <2 x double>, ptr %x
+ %red = call double @llvm.vector.reduce.fmaximum.v2f64(<2 x double> %v)
+ ret double %red
+}
+
+define double @vreduce_fmaximum_v2f64_nonans(ptr %x) {
+; CHECK-LABEL: vreduce_fmaximum_v2f64_nonans:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vle64.v v9, (a0)
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <2 x double>, ptr %x
+ %red = call nnan double @llvm.vector.reduce.fmaximum.v2f64(<2 x double> %v)
+ ret double %red
+}
+
+declare double @llvm.vector.reduce.fmaximum.v4f64(<4 x double>)
+
+define double @vreduce_fmaximum_v4f64(ptr %x) {
+; CHECK-LABEL: vreduce_fmaximum_v4f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vle64.v v10, (a0)
+; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 2
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmax.vv v9, v9, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <4 x double>, ptr %x
+ %red = call double @llvm.vector.reduce.fmaximum.v4f64(<4 x double> %v)
+ ret double %red
+}
+
+define double @vreduce_fmaximum_v4f64_nonans(ptr %x) {
+; CHECK-LABEL: vreduce_fmaximum_v4f64_nonans:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vle64.v v10, (a0)
+; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 2
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmax.vv v9, v9, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <4 x double>, ptr %x
+ %red = call nnan double @llvm.vector.reduce.fmaximum.v4f64(<4 x double> %v)
+ ret double %red
+}
+
+declare double @llvm.vector.reduce.fmaximum.v8f64(<8 x double>)
+
+define double @vreduce_fmaximum_v8f64(ptr %x) {
+; CHECK-LABEL: vreduce_fmaximum_v8f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; CHECK-NEXT: vle64.v v12, (a0)
+; CHECK-NEXT: vsetivli zero, 4, e64, m4, ta, ma
+; CHECK-NEXT: vslidedown.vi v16, v12, 4
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v12, v12
+; CHECK-NEXT: vmerge.vvm v10, v16, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v12, v16, v0
+; CHECK-NEXT: vfmax.vv v10, v10, v8
+; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 2
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmax.vv v9, v9, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <8 x double>, ptr %x
+ %red = call double @llvm.vector.reduce.fmaximum.v8f64(<8 x double> %v)
+ ret double %red
+}
+
+define double @vreduce_fmaximum_v8f64_nonans(ptr %x) {
+; CHECK-LABEL: vreduce_fmaximum_v8f64_nonans:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; CHECK-NEXT: vle64.v v12, (a0)
+; CHECK-NEXT: vsetivli zero, 4, e64, m4, ta, ma
+; CHECK-NEXT: vslidedown.vi v16, v12, 4
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v12, v12
+; CHECK-NEXT: vmerge.vvm v10, v16, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v12, v16, v0
+; CHECK-NEXT: vfmax.vv v10, v10, v8
+; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 2
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmax.vv v9, v9, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <8 x double>, ptr %x
+ %red = call nnan double @llvm.vector.reduce.fmaximum.v8f64(<8 x double> %v)
+ ret double %red
+}
+
+declare double @llvm.vector.reduce.fmaximum.v16f64(<16 x double>)
+
+define double @vreduce_fmaximum_v16f64(ptr %x) {
+; CHECK-LABEL: vreduce_fmaximum_v16f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; CHECK-NEXT: vle64.v v16, (a0)
+; CHECK-NEXT: vsetivli zero, 8, e64, m8, ta, ma
+; CHECK-NEXT: vslidedown.vi v24, v16, 8
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
+; CHECK-NEXT: vmfeq.vv v8, v16, v16
+; CHECK-NEXT: vmerge.vvm v12, v24, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: vfmax.vv v12, v12, v8
+; CHECK-NEXT: vsetivli zero, 4, e64, m4, ta, ma
+; CHECK-NEXT: vslidedown.vi v16, v12, 4
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v12, v12
+; CHECK-NEXT: vmerge.vvm v10, v16, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v12, v16, v0
+; CHECK-NEXT: vfmax.vv v10, v10, v8
+; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 2
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmax.vv v9, v9, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <16 x double>, ptr %x
+ %red = call double @llvm.vector.reduce.fmaximum.v16f64(<16 x double> %v)
+ ret double %red
+}
+
+define double @vreduce_fmaximum_v16f64_nonans(ptr %x) {
+; CHECK-LABEL: vreduce_fmaximum_v16f64_nonans:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; CHECK-NEXT: vle64.v v16, (a0)
+; CHECK-NEXT: vsetivli zero, 8, e64, m8, ta, ma
+; CHECK-NEXT: vslidedown.vi v24, v16, 8
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
+; CHECK-NEXT: vmfeq.vv v8, v16, v16
+; CHECK-NEXT: vmerge.vvm v12, v24, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: vfmax.vv v12, v12, v8
+; CHECK-NEXT: vsetivli zero, 4, e64, m4, ta, ma
+; CHECK-NEXT: vslidedown.vi v16, v12, 4
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v12, v12
+; CHECK-NEXT: vmerge.vvm v10, v16, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v12, v16, v0
+; CHECK-NEXT: vfmax.vv v10, v10, v8
+; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 2
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmax.vv v9, v9, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <16 x double>, ptr %x
+ %red = call nnan double @llvm.vector.reduce.fmaximum.v16f64(<16 x double> %v)
+ ret double %red
+}
+
+declare double @llvm.vector.reduce.fmaximum.v32f64(<32 x double>)
+
+define double @vreduce_fmaximum_v32f64(ptr %x) {
+; CHECK-LABEL: vreduce_fmaximum_v32f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: sub sp, sp, a1
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
+; CHECK-NEXT: addi a1, a0, 128
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; CHECK-NEXT: vle64.v v16, (a0)
+; CHECK-NEXT: vle64.v v24, (a1)
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v1, v24, v24
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
+; CHECK-NEXT: vmv1r.v v0, v1
+; CHECK-NEXT: vmerge.vvm v8, v24, v16, v0
+; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
+; CHECK-NEXT: vfmax.vv v16, v8, v16
+; CHECK-NEXT: vsetivli zero, 8, e64, m8, ta, ma
+; CHECK-NEXT: vslidedown.vi v24, v16, 8
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
+; CHECK-NEXT: vmfeq.vv v8, v16, v16
+; CHECK-NEXT: vmerge.vvm v12, v24, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: vfmax.vv v12, v12, v8
+; CHECK-NEXT: vsetivli zero, 4, e64, m4, ta, ma
+; CHECK-NEXT: vslidedown.vi v16, v12, 4
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v12, v12
+; CHECK-NEXT: vmerge.vvm v10, v16, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v12, v16, v0
+; CHECK-NEXT: vfmax.vv v10, v10, v8
+; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 2
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmax.vv v9, v9, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add sp, sp, a0
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: ret
+ %v = load <32 x double>, ptr %x
+ %red = call double @llvm.vector.reduce.fmaximum.v32f64(<32 x double> %v)
+ ret double %red
+}
+
+define double @vreduce_fmaximum_v32f64_nonans(ptr %x) {
+; CHECK-LABEL: vreduce_fmaximum_v32f64_nonans:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: addi a0, a0, 128
+; CHECK-NEXT: vle64.v v16, (a0)
+; CHECK-NEXT: vfmax.vv v16, v8, v16
+; CHECK-NEXT: vsetivli zero, 8, e64, m8, ta, ma
+; CHECK-NEXT: vslidedown.vi v24, v16, 8
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
+; CHECK-NEXT: vmfeq.vv v8, v16, v16
+; CHECK-NEXT: vmerge.vvm v12, v24, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: vfmax.vv v12, v12, v8
+; CHECK-NEXT: vsetivli zero, 4, e64, m4, ta, ma
+; CHECK-NEXT: vslidedown.vi v16, v12, 4
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v12, v12
+; CHECK-NEXT: vmerge.vvm v10, v16, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v12, v16, v0
+; CHECK-NEXT: vfmax.vv v10, v10, v8
+; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 2
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmax.vv v9, v9, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <32 x double>, ptr %x
+ %red = call nnan double @llvm.vector.reduce.fmaximum.v32f64(<32 x double> %v)
+ ret double %red
+}
+
+declare double @llvm.vector.reduce.fmaximum.v64f64(<64 x double>)
+
+define double @vreduce_fmaximum_v64f64(ptr %x) {
+; CHECK-LABEL: vreduce_fmaximum_v64f64:
+; CHECK: # %bb.0:
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: .cfi_def_cfa_offset 16
+; CHECK-NEXT: csrr a1, vlenb
+; CHECK-NEXT: li a2, 0
+; CHECK-NEXT: slli a1, a1, 3
+; CHECK-NEXT: add a2, a2, a1
+; CHECK-NEXT: slli a1, a1, 1
+; CHECK-NEXT: add a1, a1, a2
+; CHECK-NEXT: sub sp, sp, a1
+; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; CHECK-NEXT: addi a1, a0, 128
+; CHECK-NEXT: vle64.v v16, (a1)
+; CHECK-NEXT: addi a1, a0, 384
+; CHECK-NEXT: vle64.v v8, (a1)
+; CHECK-NEXT: addi a1, a0, 256
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vle64.v v24, (a0)
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
+; CHECK-NEXT: vmerge.vvm v24, v16, v8, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
+; CHECK-NEXT: vmfeq.vv v0, v8, v8
+; CHECK-NEXT: vle64.v v24, (a1)
+; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
+; CHECK-NEXT: vfmax.vv v8, v8, v16
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
+; CHECK-NEXT: vmfeq.vv v0, v8, v8
+; CHECK-NEXT: vmfeq.vv v1, v24, v24
+; CHECK-NEXT: vmerge.vvm v16, v8, v24, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
+; CHECK-NEXT: vmv1r.v v0, v1
+; CHECK-NEXT: vmerge.vvm v24, v24, v8, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
+; CHECK-NEXT: vfmax.vv v24, v24, v8
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
+; CHECK-NEXT: addi a0, sp, 16
+; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
+; CHECK-NEXT: vmfeq.vv v1, v16, v16
+; CHECK-NEXT: vmerge.vvm v8, v24, v16, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
+; CHECK-NEXT: vmv1r.v v0, v1
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: slli a0, a0, 4
+; CHECK-NEXT: add a0, sp, a0
+; CHECK-NEXT: addi a0, a0, 16
+; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
+; CHECK-NEXT: vfmax.vv v16, v8, v16
+; CHECK-NEXT: vsetivli zero, 8, e64, m8, ta, ma
+; CHECK-NEXT: vslidedown.vi v24, v16, 8
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
+; CHECK-NEXT: vmfeq.vv v8, v16, v16
+; CHECK-NEXT: vmerge.vvm v12, v24, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: vfmax.vv v12, v12, v8
+; CHECK-NEXT: vsetivli zero, 4, e64, m4, ta, ma
+; CHECK-NEXT: vslidedown.vi v16, v12, 4
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v12, v12
+; CHECK-NEXT: vmerge.vvm v10, v16, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v12, v16, v0
+; CHECK-NEXT: vfmax.vv v10, v10, v8
+; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 2
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmax.vv v9, v9, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: csrr a0, vlenb
+; CHECK-NEXT: li a1, 0
+; CHECK-NEXT: slli a0, a0, 3
+; CHECK-NEXT: add a1, a1, a0
+; CHECK-NEXT: slli a0, a0, 1
+; CHECK-NEXT: add a0, a0, a1
+; CHECK-NEXT: add sp, sp, a0
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: ret
+ %v = load <64 x double>, ptr %x
+ %red = call double @llvm.vector.reduce.fmaximum.v64f64(<64 x double> %v)
+ ret double %red
+}
+
+define double @vreduce_fmaximum_v64f64_nonans(ptr %x) {
+; CHECK-LABEL: vreduce_fmaximum_v64f64_nonans:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
+; CHECK-NEXT: vle64.v v8, (a0)
+; CHECK-NEXT: addi a1, a0, 384
+; CHECK-NEXT: vle64.v v16, (a1)
+; CHECK-NEXT: addi a1, a0, 256
+; CHECK-NEXT: addi a0, a0, 128
+; CHECK-NEXT: vle64.v v24, (a0)
+; CHECK-NEXT: vle64.v v0, (a1)
+; CHECK-NEXT: vfmax.vv v16, v24, v16
+; CHECK-NEXT: vfmax.vv v8, v8, v0
+; CHECK-NEXT: vfmax.vv v16, v8, v16
+; CHECK-NEXT: vsetivli zero, 8, e64, m8, ta, ma
+; CHECK-NEXT: vslidedown.vi v24, v16, 8
+; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v24, v24
+; CHECK-NEXT: vmfeq.vv v8, v16, v16
+; CHECK-NEXT: vmerge.vvm v12, v24, v16, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v16, v24, v0
+; CHECK-NEXT: vfmax.vv v12, v12, v8
+; CHECK-NEXT: vsetivli zero, 4, e64, m4, ta, ma
+; CHECK-NEXT: vslidedown.vi v16, v12, 4
+; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v16, v16
+; CHECK-NEXT: vmfeq.vv v8, v12, v12
+; CHECK-NEXT: vmerge.vvm v10, v16, v12, v0
+; CHECK-NEXT: vmv1r.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v12, v16, v0
+; CHECK-NEXT: vfmax.vv v10, v10, v8
+; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
+; CHECK-NEXT: vslidedown.vi v12, v10, 2
+; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v12, v12
+; CHECK-NEXT: vmfeq.vv v8, v10, v10
+; CHECK-NEXT: vmerge.vvm v9, v12, v10, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v10, v12, v0
+; CHECK-NEXT: vfmax.vv v9, v9, v8
+; CHECK-NEXT: vslidedown.vi v10, v9, 1
+; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT: vmfeq.vv v0, v10, v10
+; CHECK-NEXT: vmfeq.vv v8, v9, v9
+; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0
+; CHECK-NEXT: vmv.v.v v0, v8
+; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0
+; CHECK-NEXT: vfmax.vv v8, v11, v8
+; CHECK-NEXT: vfmv.f.s fa0, v8
+; CHECK-NEXT: ret
+ %v = load <64 x double>, ptr %x
+ %red = call nnan double @llvm.vector.reduce.fmaximum.v64f64(<64 x double> %v)
+ ret double %red
+}
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