[llvm] b8d92e1 - [RISCV] Fix crash in lowerVPSpliceExperimental with RV64LegalI32.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-02-02T22:06:11-08:00
New Revision: b8d92e1c4726ba6da9f7a6f388c08b3acd5cb62c

URL: https://github.com/llvm/llvm-project/commit/b8d92e1c4726ba6da9f7a6f388c08b3acd5cb62c
DIFF: https://github.com/llvm/llvm-project/commit/b8d92e1c4726ba6da9f7a6f388c08b3acd5cb62c.diff

LOG: [RISCV] Fix crash in lowerVPSpliceExperimental with RV64LegalI32.

EVL1 will be i32 and not get type legalized to i64 so we need to
manually promote it to XLenVT.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index bb8204d711d13..37d8ada1f926c 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -10824,6 +10824,9 @@ RISCVTargetLowering::lowerVPSpliceExperimental(SDValue Op,
     Mask = convertToScalableVector(MaskVT, Mask, DAG, Subtarget);
   }
 
+  // EVL1 may need to be extended to XLenVT with RV64LegalI32.
+  EVL1 = DAG.getNode(ISD::ZERO_EXTEND, DL, XLenVT, EVL1);
+
   bool IsMaskVector = VT.getVectorElementType() == MVT::i1;
   if (IsMaskVector) {
     ContainerVT = ContainerVT.changeVectorElementType(MVT::i8);