[llvm] [DAGCombiner] Optimize more vector element extractions. (PR #80520)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 2 16:34:15 PST 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-selectiondag
Author: Harald van Dijk (hvdijk)
<details>
<summary>Changes</summary>
Extracting an element from a non-legal type, floating point constants, and non-zero constants are all worth optimizing; we see better codegen on multiple platforms in existing tests.
cc @<!-- -->efriedma-quic who raised this in #<!-- -->80440
cc @<!-- -->kparzysz who authored `hfnosplat_cp.ll` which I have removed in the initial version of this PR.
`hfnosplat_cp.ll` has "no splat" in the name, but has a comment "Check that the vsplat instruction is generated", and never checks one way or the other whether the vsplat instruction is generated. With this PR, we appear to generate better code than before for this test, but I have no idea what this test is trying to check so I do not know how to adjust it. I would like to update it to check something more sensible, but I will need a bit of help with figuring out what it is meant to do.
---
Patch is 113.48 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/80520.diff
7 Files Affected:
- (modified) llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (+3-4)
- (modified) llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll (+1-170)
- (modified) llvm/test/CodeGen/ARM/arm-half-promote.ll (+60-95)
- (removed) llvm/test/CodeGen/Hexagon/autohvx/hfnosplat_cp.ll (-17)
- (modified) llvm/test/CodeGen/Mips/cconv/vector.ll (+392-283)
- (modified) llvm/test/CodeGen/X86/nontemporal-4.ll (+188-988)
- (modified) llvm/test/CodeGen/X86/vector-shuffle-combining.ll (+7-37)
``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index b17724cd07209..dfa0f520fe91e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -22240,9 +22240,8 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
}
// extract_vector_elt (build_vector x, y), 1 -> y
- if (((IndexC && VecOp.getOpcode() == ISD::BUILD_VECTOR) ||
- VecOp.getOpcode() == ISD::SPLAT_VECTOR) &&
- TLI.isTypeLegal(VecVT)) {
+ if ((IndexC && VecOp.getOpcode() == ISD::BUILD_VECTOR) ||
+ VecOp.getOpcode() == ISD::SPLAT_VECTOR) {
assert((VecOp.getOpcode() != ISD::BUILD_VECTOR ||
VecVT.isFixedLengthVector()) &&
"BUILD_VECTOR used for scalable vectors");
@@ -22252,7 +22251,7 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
EVT InEltVT = Elt.getValueType();
if (VecOp.hasOneUse() || TLI.aggressivelyPreferBuildVectorSources(VecVT) ||
- isNullConstant(Elt)) {
+ isIntOrFPConstant(Elt)) {
// Sometimes build_vector's scalar input types do not match result type.
if (ScalarVT == InEltVT)
return Elt;
diff --git a/llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll b/llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
index 274621307f540..74d377bb2bb2b 100644
--- a/llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
@@ -190,10 +190,6 @@ define <2 x half> @v_test_canonicalize_build_vector_v2f16(half %lo, half %hi) #1
; CI-LABEL: v_test_canonicalize_build_vector_v2f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
; CI-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_test_canonicalize_build_vector_v2f16:
@@ -2301,12 +2297,6 @@ define <3 x half> @v_test_canonicalize_var_v3f16(<3 x half> %val) #1 {
; CI-LABEL: v_test_canonicalize_var_v3f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
; CI-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_test_canonicalize_var_v3f16:
@@ -2341,14 +2331,6 @@ define <4 x half> @v_test_canonicalize_var_v4f16(<4 x half> %val) #1 {
; CI-LABEL: v_test_canonicalize_var_v4f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; CI-NEXT: v_cvt_f16_f32_e32 v3, v3
-; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-NEXT: v_cvt_f32_f16_e32 v3, v3
; CI-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_test_canonicalize_var_v4f16:
@@ -2611,9 +2593,7 @@ define <2 x half> @v_test_canonicalize_reg_k_v2f16(half %val) #1 {
; CI-LABEL: v_test_canonicalize_reg_k_v2f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
; CI-NEXT: v_mov_b32_e32 v1, 2.0
-; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
; CI-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_test_canonicalize_reg_k_v2f16:
@@ -2647,8 +2627,7 @@ define <2 x half> @v_test_canonicalize_k_reg_v2f16(half %val) #1 {
; CI-LABEL: v_test_canonicalize_k_reg_v2f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; CI-NEXT: v_cvt_f32_f16_e32 v1, v0
+; CI-NEXT: v_mov_b32_e32 v1, v0
; CI-NEXT: v_mov_b32_e32 v0, 2.0
; CI-NEXT: s_setpc_b64 s[30:31]
;
@@ -2878,18 +2857,6 @@ define <6 x half> @v_test_canonicalize_var_v6f16(<6 x half> %val) #1 {
; CI-LABEL: v_test_canonicalize_var_v6f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; CI-NEXT: v_cvt_f16_f32_e32 v3, v3
-; CI-NEXT: v_cvt_f16_f32_e32 v4, v4
-; CI-NEXT: v_cvt_f16_f32_e32 v5, v5
-; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-NEXT: v_cvt_f32_f16_e32 v3, v3
-; CI-NEXT: v_cvt_f32_f16_e32 v4, v4
-; CI-NEXT: v_cvt_f32_f16_e32 v5, v5
; CI-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_test_canonicalize_var_v6f16:
@@ -2933,22 +2900,6 @@ define <8 x half> @v_test_canonicalize_var_v8f16(<8 x half> %val) #1 {
; CI-LABEL: v_test_canonicalize_var_v8f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; CI-NEXT: v_cvt_f16_f32_e32 v3, v3
-; CI-NEXT: v_cvt_f16_f32_e32 v4, v4
-; CI-NEXT: v_cvt_f16_f32_e32 v5, v5
-; CI-NEXT: v_cvt_f16_f32_e32 v6, v6
-; CI-NEXT: v_cvt_f16_f32_e32 v7, v7
-; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-NEXT: v_cvt_f32_f16_e32 v3, v3
-; CI-NEXT: v_cvt_f32_f16_e32 v4, v4
-; CI-NEXT: v_cvt_f32_f16_e32 v5, v5
-; CI-NEXT: v_cvt_f32_f16_e32 v6, v6
-; CI-NEXT: v_cvt_f32_f16_e32 v7, v7
; CI-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_test_canonicalize_var_v8f16:
@@ -3001,30 +2952,6 @@ define <12 x half> @v_test_canonicalize_var_v12f16(<12 x half> %val) #1 {
; CI-LABEL: v_test_canonicalize_var_v12f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; CI-NEXT: v_cvt_f16_f32_e32 v3, v3
-; CI-NEXT: v_cvt_f16_f32_e32 v4, v4
-; CI-NEXT: v_cvt_f16_f32_e32 v5, v5
-; CI-NEXT: v_cvt_f16_f32_e32 v6, v6
-; CI-NEXT: v_cvt_f16_f32_e32 v7, v7
-; CI-NEXT: v_cvt_f16_f32_e32 v8, v8
-; CI-NEXT: v_cvt_f16_f32_e32 v9, v9
-; CI-NEXT: v_cvt_f16_f32_e32 v10, v10
-; CI-NEXT: v_cvt_f16_f32_e32 v11, v11
-; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-NEXT: v_cvt_f32_f16_e32 v3, v3
-; CI-NEXT: v_cvt_f32_f16_e32 v4, v4
-; CI-NEXT: v_cvt_f32_f16_e32 v5, v5
-; CI-NEXT: v_cvt_f32_f16_e32 v6, v6
-; CI-NEXT: v_cvt_f32_f16_e32 v7, v7
-; CI-NEXT: v_cvt_f32_f16_e32 v8, v8
-; CI-NEXT: v_cvt_f32_f16_e32 v9, v9
-; CI-NEXT: v_cvt_f32_f16_e32 v10, v10
-; CI-NEXT: v_cvt_f32_f16_e32 v11, v11
; CI-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_test_canonicalize_var_v12f16:
@@ -3087,38 +3014,6 @@ define <16 x half> @v_test_canonicalize_var_v16f16(<16 x half> %val) #1 {
; CI-LABEL: v_test_canonicalize_var_v16f16:
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; CI-NEXT: v_cvt_f16_f32_e32 v3, v3
-; CI-NEXT: v_cvt_f16_f32_e32 v4, v4
-; CI-NEXT: v_cvt_f16_f32_e32 v5, v5
-; CI-NEXT: v_cvt_f16_f32_e32 v6, v6
-; CI-NEXT: v_cvt_f16_f32_e32 v7, v7
-; CI-NEXT: v_cvt_f16_f32_e32 v8, v8
-; CI-NEXT: v_cvt_f16_f32_e32 v9, v9
-; CI-NEXT: v_cvt_f16_f32_e32 v10, v10
-; CI-NEXT: v_cvt_f16_f32_e32 v11, v11
-; CI-NEXT: v_cvt_f16_f32_e32 v12, v12
-; CI-NEXT: v_cvt_f16_f32_e32 v13, v13
-; CI-NEXT: v_cvt_f16_f32_e32 v14, v14
-; CI-NEXT: v_cvt_f16_f32_e32 v15, v15
-; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-NEXT: v_cvt_f32_f16_e32 v3, v3
-; CI-NEXT: v_cvt_f32_f16_e32 v4, v4
-; CI-NEXT: v_cvt_f32_f16_e32 v5, v5
-; CI-NEXT: v_cvt_f32_f16_e32 v6, v6
-; CI-NEXT: v_cvt_f32_f16_e32 v7, v7
-; CI-NEXT: v_cvt_f32_f16_e32 v8, v8
-; CI-NEXT: v_cvt_f32_f16_e32 v9, v9
-; CI-NEXT: v_cvt_f32_f16_e32 v10, v10
-; CI-NEXT: v_cvt_f32_f16_e32 v11, v11
-; CI-NEXT: v_cvt_f32_f16_e32 v12, v12
-; CI-NEXT: v_cvt_f32_f16_e32 v13, v13
-; CI-NEXT: v_cvt_f32_f16_e32 v14, v14
-; CI-NEXT: v_cvt_f32_f16_e32 v15, v15
; CI-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_test_canonicalize_var_v16f16:
@@ -3216,71 +3111,7 @@ define <32 x half> @v_test_canonicalize_var_v32f16(<32 x half> %val) #1 {
; CI: ; %bb.0:
; CI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CI-NEXT: buffer_load_dword v31, off, s[0:3], s32
-; CI-NEXT: v_cvt_f16_f32_e32 v0, v0
-; CI-NEXT: v_cvt_f16_f32_e32 v1, v1
-; CI-NEXT: v_cvt_f16_f32_e32 v2, v2
-; CI-NEXT: v_cvt_f16_f32_e32 v3, v3
-; CI-NEXT: v_cvt_f16_f32_e32 v4, v4
-; CI-NEXT: v_cvt_f16_f32_e32 v5, v5
-; CI-NEXT: v_cvt_f16_f32_e32 v6, v6
-; CI-NEXT: v_cvt_f16_f32_e32 v7, v7
-; CI-NEXT: v_cvt_f16_f32_e32 v8, v8
-; CI-NEXT: v_cvt_f16_f32_e32 v9, v9
-; CI-NEXT: v_cvt_f16_f32_e32 v10, v10
-; CI-NEXT: v_cvt_f16_f32_e32 v11, v11
-; CI-NEXT: v_cvt_f16_f32_e32 v12, v12
-; CI-NEXT: v_cvt_f16_f32_e32 v13, v13
-; CI-NEXT: v_cvt_f16_f32_e32 v14, v14
-; CI-NEXT: v_cvt_f16_f32_e32 v15, v15
-; CI-NEXT: v_cvt_f16_f32_e32 v16, v16
-; CI-NEXT: v_cvt_f16_f32_e32 v17, v17
-; CI-NEXT: v_cvt_f16_f32_e32 v18, v18
-; CI-NEXT: v_cvt_f16_f32_e32 v19, v19
-; CI-NEXT: v_cvt_f16_f32_e32 v20, v20
-; CI-NEXT: v_cvt_f16_f32_e32 v21, v21
-; CI-NEXT: v_cvt_f16_f32_e32 v22, v22
-; CI-NEXT: v_cvt_f16_f32_e32 v23, v23
-; CI-NEXT: v_cvt_f16_f32_e32 v24, v24
-; CI-NEXT: v_cvt_f16_f32_e32 v25, v25
-; CI-NEXT: v_cvt_f16_f32_e32 v26, v26
-; CI-NEXT: v_cvt_f16_f32_e32 v27, v27
-; CI-NEXT: v_cvt_f16_f32_e32 v28, v28
-; CI-NEXT: v_cvt_f16_f32_e32 v29, v29
-; CI-NEXT: v_cvt_f16_f32_e32 v30, v30
-; CI-NEXT: v_cvt_f32_f16_e32 v0, v0
-; CI-NEXT: v_cvt_f32_f16_e32 v1, v1
-; CI-NEXT: v_cvt_f32_f16_e32 v2, v2
-; CI-NEXT: v_cvt_f32_f16_e32 v3, v3
-; CI-NEXT: v_cvt_f32_f16_e32 v4, v4
-; CI-NEXT: v_cvt_f32_f16_e32 v5, v5
-; CI-NEXT: v_cvt_f32_f16_e32 v6, v6
-; CI-NEXT: v_cvt_f32_f16_e32 v7, v7
-; CI-NEXT: v_cvt_f32_f16_e32 v8, v8
-; CI-NEXT: v_cvt_f32_f16_e32 v9, v9
-; CI-NEXT: v_cvt_f32_f16_e32 v10, v10
-; CI-NEXT: v_cvt_f32_f16_e32 v11, v11
-; CI-NEXT: v_cvt_f32_f16_e32 v12, v12
-; CI-NEXT: v_cvt_f32_f16_e32 v13, v13
-; CI-NEXT: v_cvt_f32_f16_e32 v14, v14
-; CI-NEXT: v_cvt_f32_f16_e32 v15, v15
-; CI-NEXT: v_cvt_f32_f16_e32 v16, v16
-; CI-NEXT: v_cvt_f32_f16_e32 v17, v17
-; CI-NEXT: v_cvt_f32_f16_e32 v18, v18
-; CI-NEXT: v_cvt_f32_f16_e32 v19, v19
-; CI-NEXT: v_cvt_f32_f16_e32 v20, v20
-; CI-NEXT: v_cvt_f32_f16_e32 v21, v21
-; CI-NEXT: v_cvt_f32_f16_e32 v22, v22
-; CI-NEXT: v_cvt_f32_f16_e32 v23, v23
-; CI-NEXT: v_cvt_f32_f16_e32 v24, v24
-; CI-NEXT: v_cvt_f32_f16_e32 v25, v25
-; CI-NEXT: v_cvt_f32_f16_e32 v26, v26
-; CI-NEXT: v_cvt_f32_f16_e32 v27, v27
-; CI-NEXT: v_cvt_f32_f16_e32 v28, v28
-; CI-NEXT: v_cvt_f32_f16_e32 v29, v29
-; CI-NEXT: v_cvt_f32_f16_e32 v30, v30
; CI-NEXT: s_waitcnt vmcnt(0)
-; CI-NEXT: v_cvt_f16_f32_e32 v31, v31
-; CI-NEXT: v_cvt_f32_f16_e32 v31, v31
; CI-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_test_canonicalize_var_v32f16:
diff --git a/llvm/test/CodeGen/ARM/arm-half-promote.ll b/llvm/test/CodeGen/ARM/arm-half-promote.ll
index e1ab75b2ac7f1..d6a8a9b9538f1 100644
--- a/llvm/test/CodeGen/ARM/arm-half-promote.ll
+++ b/llvm/test/CodeGen/ARM/arm-half-promote.ll
@@ -2,113 +2,78 @@
define arm_aapcs_vfpcc { <8 x half>, <8 x half> } @f1() {
; CHECK-LABEL: _f1
-; CHECK: vpush {d8, d9, d10, d11}
-; CHECK-NEXT: vmov.i32 q8, #0x0
-; CHECK-NEXT: vmov.u16 r0, d16[0]
-; CHECK-NEXT: vmov d4, r0, r0
-; CHECK-NEXT: vmov.u16 r0, d16[1]
-; CHECK-NEXT: vmov d8, r0, r0
-; CHECK-NEXT: vmov.u16 r0, d16[2]
-; CHECK-NEXT: vmov d5, r0, r0
-; CHECK-NEXT: vmov.u16 r0, d16[3]
-; CHECK-NEXT: vmov d9, r0, r0
-; CHECK-NEXT: vmov.u16 r0, d17[0]
-; CHECK-NEXT: vmov d6, r0, r0
-; CHECK-NEXT: vmov.u16 r0, d17[1]
-; CHECK-NEXT: vmov d10, r0, r0
-; CHECK-NEXT: vmov.u16 r0, d17[2]
-; CHECK-NEXT: vmov d7, r0, r0
-; CHECK-NEXT: vmov.u16 r0, d17[3]
-; CHECK-NEXT: vmov d11, r0, r0
-; CHECK: vmov.f32 s0, s8
-; CHECK: vmov.f32 s1, s16
-; CHECK: vmov.f32 s2, s10
-; CHECK: vmov.f32 s3, s18
-; CHECK: vmov.f32 s4, s12
-; CHECK: vmov.f32 s5, s20
-; CHECK: vmov.f32 s6, s14
-; CHECK: vmov.f32 s7, s22
-; CHECK: vmov.f32 s9, s16
-; CHECK: vmov.f32 s11, s18
-; CHECK: vmov.f32 s13, s20
-; CHECK: vmov.f32 s15, s22
-; CHECK: vpop {d8, d9, d10, d11}
+; CHECK: vpush {d8}
+; CHECK-NEXT: vmov.f64 d8, #5.000000e-01
+; CHECK-NEXT: vmov.i32 d8, #0x0
+; CHECK-NEXT: vmov.i32 d0, #0x0
+; CHECK-NEXT: vmov.i32 d1, #0x0
+; CHECK-NEXT: vmov.i32 d2, #0x0
+; CHECK-NEXT: vmov.i32 d3, #0x0
+; CHECK-NEXT: vmov.i32 d4, #0x0
+; CHECK-NEXT: vmov.i32 d5, #0x0
+; CHECK-NEXT: vmov.i32 d6, #0x0
+; CHECK-NEXT: vmov.i32 d7, #0x0
+; CHECK-NEXT: vmov.f32 s1, s16
+; CHECK-NEXT: vmov.f32 s3, s16
+; CHECK-NEXT: vmov.f32 s5, s16
+; CHECK-NEXT: vmov.f32 s7, s16
+; CHECK-NEXT: vmov.f32 s9, s16
+; CHECK-NEXT: vmov.f32 s11, s16
+; CHECK-NEXT: vmov.f32 s13, s16
+; CHECK-NEXT: vmov.f32 s15, s16
+; CHECK-NEXT: vpop {d8}
; CHECK-NEXT: bx lr
-
ret { <8 x half>, <8 x half> } zeroinitializer
}
define swiftcc { <8 x half>, <8 x half> } @f2() {
; CHECK-LABEL: _f2
-; CHECK: vpush {d8, d9, d10, d11}
-; CHECK-NEXT: vmov.i32 q8, #0x0
-; CHECK-NEXT: vmov.u16 r0, d16[0]
-; CHECK-NEXT: vmov d4, r0, r0
-; CHECK-NEXT: vmov.u16 r0, d16[1]
-; CHECK-NEXT: vmov d8, r0, r0
-; CHECK-NEXT: vmov.u16 r0, d16[2]
-; CHECK-NEXT: vmov d5, r0, r0
-; CHECK-NEXT: vmov.u16 r0, d16[3]
-; CHECK-NEXT: vmov d9, r0, r0
-; CHECK-NEXT: vmov.u16 r0, d17[0]
-; CHECK-NEXT: vmov d6, r0, r0
-; CHECK-NEXT: vmov.u16 r0, d17[1]
-; CHECK-NEXT: vmov d10, r0, r0
-; CHECK-NEXT: vmov.u16 r0, d17[2]
-; CHECK-NEXT: vmov d7, r0, r0
-; CHECK-NEXT: vmov.u16 r0, d17[3]
-; CHECK-NEXT: vmov d11, r0, r0
-; CHECK: vmov.f32 s0, s8
-; CHECK: vmov.f32 s1, s16
-; CHECK: vmov.f32 s2, s10
-; CHECK: vmov.f32 s3, s18
-; CHECK: vmov.f32 s4, s12
-; CHECK: vmov.f32 s5, s20
-; CHECK: vmov.f32 s6, s14
-; CHECK: vmov.f32 s7, s22
-; CHECK: vmov.f32 s9, s16
-; CHECK: vmov.f32 s11, s18
-; CHECK: vmov.f32 s13, s20
-; CHECK: vmov.f32 s15, s22
-; CHECK-NEXT: vpop {d8, d9, d10, d11}
+; CHECK: vpush {d8}
+; CHECK-NEXT: vmov.f64 d8, #5.000000e-01
+; CHECK-NEXT: vmov.i32 d8, #0x0
+; CHECK-NEXT: vmov.i32 d0, #0x0
+; CHECK-NEXT: vmov.i32 d1, #0x0
+; CHECK-NEXT: vmov.i32 d2, #0x0
+; CHECK-NEXT: vmov.i32 d3, #0x0
+; CHECK-NEXT: vmov.i32 d4, #0x0
+; CHECK-NEXT: vmov.i32 d5, #0x0
+; CHECK-NEXT: vmov.i32 d6, #0x0
+; CHECK-NEXT: vmov.i32 d7, #0x0
+; CHECK-NEXT: vmov.f32 s1, s16
+; CHECK-NEXT: vmov.f32 s3, s16
+; CHECK-NEXT: vmov.f32 s5, s16
+; CHECK-NEXT: vmov.f32 s7, s16
+; CHECK-NEXT: vmov.f32 s9, s16
+; CHECK-NEXT: vmov.f32 s11, s16
+; CHECK-NEXT: vmov.f32 s13, s16
+; CHECK-NEXT: vmov.f32 s15, s16
+; CHECK-NEXT: vpop {d8}
; CHECK-NEXT: bx lr
-
ret { <8 x half>, <8 x half> } zeroinitializer
}
define fastcc { <8 x half>, <8 x half> } @f3() {
; CHECK-LABEL: _f3
-; CHECK: vpush {d8, d9, d10, d11}
-; CHECK-NEXT: vmov.i32 q8, #0x0
-; CHECK-NEXT: vmov.u16 r0, d16[0]
-; CHECK-NEXT: vmov d4, r0, r0
-; CHECK-NEXT: vmov.u16 r0, d16[1]
-; CHECK-NEXT: vmov d8, r0, r0
-; CHECK-NEXT: vmov.u16 r0, d16[2]
-; CHECK-NEXT: vmov d5, r0, r0
-; CHECK-NEXT: vmov.u16 r0, d16[3]
-; CHECK-NEXT: vmov d9, r0, r0
-; CHECK-NEXT: vmov.u16 r0, d17[0]
-; CHECK-NEXT: vmov d6, r0, r0
-; CHECK-NEXT: vmov.u16 r0, d17[1]
-; CHECK-NEXT: vmov d10, r0, r0
-; CHECK-NEXT: vmov.u16 r0, d17[2]
-; CHECK-NEXT: vmov d7, r0, r0
-; CHECK-NEXT: vmov.u16 r0, d17[3]
-; CHECK-NEXT: vmov d11, r0, r0
-; CHECK: vmov.f32 s0, s8
-; CHECK: vmov.f32 s1, s16
-; CHECK: vmov.f32 s2, s10
-; CHECK: vmov.f32 s3, s18
-; CHECK: vmov.f32 s4, s12
-; CHECK: vmov.f32 s5, s20
-; CHECK: vmov.f32 s6, s14
-; CHECK: vmov.f32 s7, s22
-; CHECK: vmov.f32 s9, s16
-; CHECK: vmov.f32 s11, s18
-; CHECK: vmov.f32 s13, s20
-; CHECK: vmov.f32 s15, s22
-; CHECK-NEXT: vpop {d8, d9, d10, d11}
+; CHECK: vpush {d8}
+; CHECK-NEXT: vmov.f64 d8, #5.000000e-01
+; CHECK-NEXT: vmov.i32 d8, #0x0
+; CHECK-NEXT: vmov.i32 d0, #0x0
+; CHECK-NEXT: vmov.i32 d1, #0x0
+; CHECK-NEXT: vmov.i32 d2, #0x0
+; CHECK-NEXT: vmov.i32 d3, #0x0
+; CHECK-NEXT: vmov.i32 d4, #0x0
+; CHECK-NEXT: vmov.i32 d5, #0x0
+; CHECK-NEXT: vmov.i32 d6, #0x0
+; CHECK-NEXT: vmov.i32 d7, #0x0
+; CHECK-NEXT: vmov.f32 s1, s16
+; CHECK-NEXT: vmov.f32 s3, s16
+; CHECK-NEXT: vmov.f32 s5, s16
+; CHECK-NEXT: vmov.f32 s7, s16
+; CHECK-NEXT: vmov.f32 s9, s16
+; CHECK-NEXT: vmov.f32 s11, s16
+; CHECK-NEXT: vmov.f32 s13, s16
+; CHECK-NEXT: vmov.f32 s15, s16
+; CHECK-NEXT: vpop {d8}
; CHECK-NEXT: bx lr
ret { <8 x half>, <8 x half> } zeroinitializer
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/hfnosplat_cp.ll b/llvm/test/CodeGen/Hexagon/autohvx/hfnosplat_cp.ll
deleted file mode 100644
index 4c5c96e61b78c..0000000000000
--- a/llvm/test/CodeGen/Hexagon/autohvx/hfnosplat_cp.ll
+++ /dev/null
@@ -1,17 +0,0 @@
-; RUN: llc -mtriple=hexagon < %s | FileCheck %s
-
-; Check that the vsplat instruction is generated
-; CHECK: .word 1097875824
-; CHECK: .word 1048133241
-; CHECK: .word 0
-
-target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
-target triple = "hexagon"
-; Function Attrs: nofree norecurse nounwind writeonly
-define dso_local i32 @foo(ptr nocapture %a) local_unnamed_addr #0 {
-vector.body:
- store <40 x half> <half 0xH4170, half 0xH4170, half 0xH4170, half 0xH4170, half 0xH4170, half 0xH4170, half 0xH4170, half 0xH4170, half 0xH4170, half 0xH4170, half 0xH4170, half 0xH4170, half 0xH4170, half 0xH4170, half 0xH4170, half 0xH4170, half 0xH4170, half 0xH4170, half 0xH4170, half 0xH4170, half 0xH4170, half 0xH4170, half 0xH4170, half 0xH4170, half 0xH4170, half 0xH4170, half 0xH4170, half 0xH4170, half 0xH4170, half 0xH4170, half 0xH4170, half 0xH3E79, half 0xH3E79, half 0xH3E79, half 0xH3E79, half 0xH3E79, half 0xH3E79, half 0xH3E79, half 0xH3E79, half 0xH3E79>, ptr %a, align 2
- ret i32 0
-}
-
-attributes #0 = { nofree norecurse nounwind writeonly "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv69" "target-features"="+hvx-length128b,+hvxv69,+v69,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }
diff --git a/llvm/test/CodeGen/Mips/cconv/vector.ll b/llvm/test/CodeGen/Mips/cconv/vector.ll
index 28a7dc046139b..a56005ead73ef 100644
--- a/llvm/test/CodeGen/Mips/cconv/vector.ll
+++ b/llvm/test/CodeGen/Mips/cconv/vector.ll
@@ -3855,77 +3855,81 @@ define void @calli8_16() {
; MIPS64EB-NEXT: jr $ra
; MIPS64EB-NEXT: nop
;
-; MIPS32R5-LABEL: calli8_16:
-; MIP...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/80520
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