[llvm] [SelectionDAG] Add computeKnownBits support for ISD::STEP_VECTOR (PR #80452)

[Craig Topper via llvm-commits]

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@@ -3110,6 +3110,19 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
     }
     break;
   }
+  case ISD::STEP_VECTOR: {
+    const APInt &Step = Op.getConstantOperandAPInt(0);
+
+    if (Step.isPowerOf2())
+      Known.Zero.setLowBits(Step.logBase2());
+
+    const Function &F = getMachineFunction().getFunction();
+    const APInt MaxNumElts = getVScaleRange(&F, BitWidth).getUnsignedMax() *
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topperc wrote:

An SEW=8 LMUL=8 step vector overflows on a VLEN=512 core like sifive-x280. That's 512 elements. so the step vector produces [0, ..., 255, 0, ..., 255].

https://github.com/llvm/llvm-project/pull/80452