[llvm] faeb3d1 - [AMDGPU] Regenerate ctpop64.ll test checks
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 2 10:13:56 PST 2024
Author: Simon Pilgrim
Date: 2024-02-02T18:08:15Z
New Revision: faeb3d1f106d607f51babe3770e899bc9bda7f3a
URL: https://github.com/llvm/llvm-project/commit/faeb3d1f106d607f51babe3770e899bc9bda7f3a
DIFF: https://github.com/llvm/llvm-project/commit/faeb3d1f106d607f51babe3770e899bc9bda7f3a.diff
LOG: [AMDGPU] Regenerate ctpop64.ll test checks
Added:
Modified:
llvm/test/CodeGen/AMDGPU/ctpop64.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/ctpop64.ll b/llvm/test/CodeGen/AMDGPU/ctpop64.ll
index 1fc508810e34b..1346678e51e3d 100644
--- a/llvm/test/CodeGen/AMDGPU/ctpop64.ll
+++ b/llvm/test/CodeGen/AMDGPU/ctpop64.ll
@@ -1,5 +1,6 @@
-; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
-; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI %s
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
@@ -12,28 +13,73 @@ declare <16 x i64> @llvm.ctpop.v16i64(<16 x i64>) nounwind readnone
declare i65 @llvm.ctpop.i65(i65) nounwind readnone
declare i128 @llvm.ctpop.i128(i128) nounwind readnone
-; FUNC-LABEL: {{^}}s_ctpop_i64:
-; SI: s_load_dwordx2 [[SVAL:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0x13
-; VI: s_load_dwordx2 [[SVAL:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0x4c
-; GCN: s_bcnt1_i32_b64 [[SRESULT:s[0-9]+]], [[SVAL]]
-; GCN: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
-; GCN: buffer_store_dword [[VRESULT]],
-; GCN: s_endpgm
define amdgpu_kernel void @s_ctpop_i64(ptr addrspace(1) noalias %out, [8 x i32], i64 %val) nounwind {
+; SI-LABEL: s_ctpop_i64:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x13
+; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
+; SI-NEXT: v_mov_b32_e32 v0, s4
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: s_ctpop_i64:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x4c
+; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
+; VI-NEXT: v_mov_b32_e32 v0, s4
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_endpgm
%ctpop = call i64 @llvm.ctpop.i64(i64 %val) nounwind readnone
%truncctpop = trunc i64 %ctpop to i32
store i32 %truncctpop, ptr addrspace(1) %out, align 4
ret void
}
-; FUNC-LABEL: {{^}}v_ctpop_i64:
-; GCN: {{buffer|flat}}_load_dwordx2 v[[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]],
-; GCN: v_bcnt_u32_b32{{(_e64)*}} [[MIDRESULT:v[0-9]+]], v[[LOVAL]], 0
-; SI-NEXT: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]]
-; VI-NEXT: v_bcnt_u32_b32 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]]
-; GCN: buffer_store_dword [[RESULT]],
-; GCN: s_endpgm
define amdgpu_kernel void @v_ctpop_i64(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {
+; SI-LABEL: v_ctpop_i64:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s10, 0
+; SI-NEXT: s_mov_b32 s11, s7
+; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_mov_b64 s[8:9], s[2:3]
+; SI-NEXT: v_mov_b32_e32 v1, 0
+; SI-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[8:11], 0 addr64
+; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: s_mov_b32 s4, s0
+; SI-NEXT: s_mov_b32 s5, s1
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_bcnt_u32_b32_e64 v0, v0, 0
+; SI-NEXT: v_bcnt_u32_b32_e32 v0, v1, v0
+; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: v_ctpop_i64:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_bcnt_u32_b32 v0, v0, 0
+; VI-NEXT: v_bcnt_u32_b32 v0, v1, v0
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%in.gep = getelementptr i64, ptr addrspace(1) %in, i32 %tid
%val = load i64, ptr addrspace(1) %in.gep, align 8
@@ -43,16 +89,49 @@ define amdgpu_kernel void @v_ctpop_i64(ptr addrspace(1) noalias %out, ptr addrsp
ret void
}
-; FUNC-LABEL: {{^}}v_ctpop_i64_user:
-; GCN: {{buffer|flat}}_load_dwordx2 v[[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]],
-; GCN: v_bcnt_u32_b32{{(_e64)*}} [[MIDRESULT:v[0-9]+]], v[[LOVAL]], 0
-; SI-NEXT: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]]
-; VI-NEXT: v_bcnt_u32_b32 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]]
-; GCN-DAG: v_or_b32_e32 v[[RESULT_LO:[0-9]+]], s{{[0-9]+}}, [[RESULT]]
-; GCN-DAG: v_mov_b32_e32 v[[RESULT_HI:[0-9]+]], s{{[0-9]+}}
-; GCN: buffer_store_dwordx2 v[[[RESULT_LO]]:[[RESULT_HI]]]
-; GCN: s_endpgm
define amdgpu_kernel void @v_ctpop_i64_user(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in, i64 %s.val) nounwind {
+; SI-LABEL: v_ctpop_i64_user:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; SI-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0xd
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s10, 0
+; SI-NEXT: s_mov_b32 s11, s3
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_mov_b64 s[8:9], s[6:7]
+; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
+; SI-NEXT: v_mov_b32_e32 v1, 0
+; SI-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[8:11], 0 addr64
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_mov_b32 s0, s4
+; SI-NEXT: s_mov_b32 s1, s5
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_bcnt_u32_b32_e64 v0, v0, 0
+; SI-NEXT: v_bcnt_u32_b32_e32 v0, v1, v0
+; SI-NEXT: v_mov_b32_e32 v1, s13
+; SI-NEXT: v_or_b32_e32 v0, s12, v0
+; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: v_ctpop_i64_user:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
+; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s7
+; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v0
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
+; VI-NEXT: s_mov_b32 s7, 0xf000
+; VI-NEXT: s_mov_b32 s6, -1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_bcnt_u32_b32 v0, v0, 0
+; VI-NEXT: v_bcnt_u32_b32 v0, v1, v0
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: v_or_b32_e32 v0, s0, v0
+; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%in.gep = getelementptr i64, ptr addrspace(1) %in, i32 %tid
%val = load i64, ptr addrspace(1) %in.gep, align 8
@@ -62,37 +141,123 @@ define amdgpu_kernel void @v_ctpop_i64_user(ptr addrspace(1) noalias %out, ptr a
ret void
}
-; FUNC-LABEL: {{^}}s_ctpop_v2i64:
-; GCN: s_bcnt1_i32_b64
-; GCN: s_bcnt1_i32_b64
-; GCN: s_endpgm
define amdgpu_kernel void @s_ctpop_v2i64(ptr addrspace(1) noalias %out, <2 x i64> %val) nounwind {
+; SI-LABEL: s_ctpop_v2i64:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd
+; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
+; SI-NEXT: s_bcnt1_i32_b64 s5, s[6:7]
+; SI-NEXT: v_mov_b32_e32 v0, s4
+; SI-NEXT: v_mov_b32_e32 v1, s5
+; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: s_ctpop_v2i64:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
+; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
+; VI-NEXT: s_bcnt1_i32_b64 s5, s[6:7]
+; VI-NEXT: v_mov_b32_e32 v0, s4
+; VI-NEXT: v_mov_b32_e32 v1, s5
+; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; VI-NEXT: s_endpgm
%ctpop = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %val) nounwind readnone
%truncctpop = trunc <2 x i64> %ctpop to <2 x i32>
store <2 x i32> %truncctpop, ptr addrspace(1) %out, align 8
ret void
}
-; FUNC-LABEL: {{^}}s_ctpop_v4i64:
-; GCN: s_bcnt1_i32_b64
-; GCN: s_bcnt1_i32_b64
-; GCN: s_bcnt1_i32_b64
-; GCN: s_bcnt1_i32_b64
-; GCN: s_endpgm
define amdgpu_kernel void @s_ctpop_v4i64(ptr addrspace(1) noalias %out, <4 x i64> %val) nounwind {
+; SI-LABEL: s_ctpop_v4i64:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x11
+; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
+; SI-NEXT: s_bcnt1_i32_b64 s5, s[6:7]
+; SI-NEXT: s_bcnt1_i32_b64 s6, s[8:9]
+; SI-NEXT: s_bcnt1_i32_b64 s7, s[10:11]
+; SI-NEXT: v_mov_b32_e32 v0, s4
+; SI-NEXT: v_mov_b32_e32 v1, s5
+; SI-NEXT: v_mov_b32_e32 v2, s6
+; SI-NEXT: v_mov_b32_e32 v3, s7
+; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: s_ctpop_v4i64:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x44
+; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
+; VI-NEXT: s_bcnt1_i32_b64 s5, s[6:7]
+; VI-NEXT: s_bcnt1_i32_b64 s6, s[8:9]
+; VI-NEXT: s_bcnt1_i32_b64 s7, s[10:11]
+; VI-NEXT: v_mov_b32_e32 v0, s4
+; VI-NEXT: v_mov_b32_e32 v1, s5
+; VI-NEXT: v_mov_b32_e32 v2, s6
+; VI-NEXT: v_mov_b32_e32 v3, s7
+; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; VI-NEXT: s_endpgm
%ctpop = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %val) nounwind readnone
%truncctpop = trunc <4 x i64> %ctpop to <4 x i32>
store <4 x i32> %truncctpop, ptr addrspace(1) %out, align 16
ret void
}
-; FUNC-LABEL: {{^}}v_ctpop_v2i64:
-; GCN: v_bcnt_u32_b32
-; GCN: v_bcnt_u32_b32
-; GCN: v_bcnt_u32_b32
-; GCN: v_bcnt_u32_b32
-; GCN: s_endpgm
define amdgpu_kernel void @v_ctpop_v2i64(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {
+; SI-LABEL: v_ctpop_v2i64:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s10, 0
+; SI-NEXT: s_mov_b32 s11, s7
+; SI-NEXT: v_lshlrev_b32_e32 v0, 4, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_mov_b64 s[8:9], s[2:3]
+; SI-NEXT: v_mov_b32_e32 v1, 0
+; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64
+; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: s_mov_b32 s4, s0
+; SI-NEXT: s_mov_b32 s5, s1
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_bcnt_u32_b32_e64 v0, v0, 0
+; SI-NEXT: v_bcnt_u32_b32_e64 v2, v2, 0
+; SI-NEXT: v_bcnt_u32_b32_e32 v0, v1, v0
+; SI-NEXT: v_bcnt_u32_b32_e32 v1, v3, v2
+; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: v_ctpop_v2i64:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v0, 4, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_bcnt_u32_b32 v0, v0, 0
+; VI-NEXT: v_bcnt_u32_b32 v2, v2, 0
+; VI-NEXT: v_bcnt_u32_b32 v0, v1, v0
+; VI-NEXT: v_bcnt_u32_b32 v1, v3, v2
+; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%in.gep = getelementptr <2 x i64>, ptr addrspace(1) %in, i32 %tid
%val = load <2 x i64>, ptr addrspace(1) %in.gep, align 16
@@ -102,17 +267,61 @@ define amdgpu_kernel void @v_ctpop_v2i64(ptr addrspace(1) noalias %out, ptr addr
ret void
}
-; FUNC-LABEL: {{^}}v_ctpop_v4i64:
-; GCN: v_bcnt_u32_b32
-; GCN: v_bcnt_u32_b32
-; GCN: v_bcnt_u32_b32
-; GCN: v_bcnt_u32_b32
-; GCN: v_bcnt_u32_b32
-; GCN: v_bcnt_u32_b32
-; GCN: v_bcnt_u32_b32
-; GCN: v_bcnt_u32_b32
-; GCN: s_endpgm
define amdgpu_kernel void @v_ctpop_v4i64(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {
+; SI-LABEL: v_ctpop_v4i64:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s10, 0
+; SI-NEXT: s_mov_b32 s11, s7
+; SI-NEXT: v_lshlrev_b32_e32 v4, 5, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_mov_b64 s[8:9], s[2:3]
+; SI-NEXT: v_mov_b32_e32 v5, 0
+; SI-NEXT: buffer_load_dwordx4 v[0:3], v[4:5], s[8:11], 0 addr64
+; SI-NEXT: buffer_load_dwordx4 v[4:7], v[4:5], s[8:11], 0 addr64 offset:16
+; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: s_mov_b32 s4, s0
+; SI-NEXT: s_mov_b32 s5, s1
+; SI-NEXT: s_waitcnt vmcnt(1)
+; SI-NEXT: v_bcnt_u32_b32_e64 v0, v0, 0
+; SI-NEXT: v_bcnt_u32_b32_e64 v2, v2, 0
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_bcnt_u32_b32_e64 v4, v4, 0
+; SI-NEXT: v_bcnt_u32_b32_e64 v6, v6, 0
+; SI-NEXT: v_bcnt_u32_b32_e32 v0, v1, v0
+; SI-NEXT: v_bcnt_u32_b32_e32 v1, v3, v2
+; SI-NEXT: v_bcnt_u32_b32_e32 v2, v5, v4
+; SI-NEXT: v_bcnt_u32_b32_e32 v3, v7, v6
+; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: v_ctpop_v4i64:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v0, 5, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v4, vcc, s2, v0
+; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
+; VI-NEXT: flat_load_dwordx4 v[0:3], v[4:5]
+; VI-NEXT: v_add_u32_e32 v4, vcc, 16, v4
+; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; VI-NEXT: flat_load_dwordx4 v[4:7], v[4:5]
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: s_waitcnt vmcnt(1)
+; VI-NEXT: v_bcnt_u32_b32 v0, v0, 0
+; VI-NEXT: v_bcnt_u32_b32 v8, v2, 0
+; VI-NEXT: v_bcnt_u32_b32 v2, v1, v0
+; VI-NEXT: v_bcnt_u32_b32 v3, v3, v8
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_bcnt_u32_b32 v4, v4, 0
+; VI-NEXT: v_bcnt_u32_b32 v6, v6, 0
+; VI-NEXT: v_bcnt_u32_b32 v4, v5, v4
+; VI-NEXT: v_bcnt_u32_b32 v5, v7, v6
+; VI-NEXT: buffer_store_dwordx4 v[2:5], off, s[0:3], 0
+; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%in.gep = getelementptr <4 x i64>, ptr addrspace(1) %in, i32 %tid
%val = load <4 x i64>, ptr addrspace(1) %in.gep, align 32
@@ -122,16 +331,65 @@ define amdgpu_kernel void @v_ctpop_v4i64(ptr addrspace(1) noalias %out, ptr addr
ret void
}
-; FUNC-LABEL: {{^}}ctpop_i64_in_br:
-; SI-DAG: s_load_dwordx2 s[[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]], s[{{[0-9]+:[0-9]+}}], 0xd
-; VI-DAG: s_load_dwordx2 s[[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]], s[{{[0-9]+:[0-9]+}}], 0x34
-; GCN-DAG: s_bcnt1_i32_b64 [[RESULT:s[0-9]+]], {{s\[}}[[LOVAL]]:[[HIVAL]]]
-; GCN-DAG: s_mov_b32 [[ZERO:s[0-9]+]], 0
-; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], [[RESULT]]
-; GCN-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], [[ZERO]]
-; GCN: buffer_store_dwordx2 {{v\[}}[[VLO]]:[[VHI]]]
-; GCN: s_endpgm
define amdgpu_kernel void @ctpop_i64_in_br(ptr addrspace(1) %out, ptr addrspace(1) %in, i64 %ctpop_arg, i32 %cond) {
+; SI-LABEL: ctpop_i64_in_br:
+; SI: ; %bb.0: ; %entry
+; SI-NEXT: s_load_dword s8, s[0:1], 0xf
+; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; SI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_cmp_lg_u32 s8, 0
+; SI-NEXT: s_cbranch_scc0 .LBB7_4
+; SI-NEXT: ; %bb.1: ; %else
+; SI-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x2
+; SI-NEXT: s_mov_b64 s[6:7], 0
+; SI-NEXT: s_andn2_b64 vcc, exec, s[6:7]
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_mov_b64 vcc, vcc
+; SI-NEXT: s_cbranch_vccnz .LBB7_3
+; SI-NEXT: .LBB7_2: ; %if
+; SI-NEXT: s_bcnt1_i32_b64 s0, s[2:3]
+; SI-NEXT: s_mov_b32 s1, 0
+; SI-NEXT: .LBB7_3: ; %endif
+; SI-NEXT: v_mov_b32_e32 v0, s0
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: v_mov_b32_e32 v1, s1
+; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; SI-NEXT: s_endpgm
+; SI-NEXT: .LBB7_4:
+; SI-NEXT: s_mov_b64 s[6:7], -1
+; SI-NEXT: ; implicit-def: $sgpr0_sgpr1
+; SI-NEXT: s_branch .LBB7_2
+;
+; VI-LABEL: ctpop_i64_in_br:
+; VI: ; %bb.0: ; %entry
+; VI-NEXT: s_load_dword s8, s[0:1], 0x3c
+; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; VI-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_cmp_lg_u32 s8, 0
+; VI-NEXT: s_cbranch_scc0 .LBB7_4
+; VI-NEXT: ; %bb.1: ; %else
+; VI-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x8
+; VI-NEXT: s_mov_b64 s[6:7], 0
+; VI-NEXT: s_cbranch_execnz .LBB7_3
+; VI-NEXT: .LBB7_2: ; %if
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_bcnt1_i32_b64 s0, s[2:3]
+; VI-NEXT: s_mov_b32 s1, 0
+; VI-NEXT: .LBB7_3: ; %endif
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s0
+; VI-NEXT: s_mov_b32 s7, 0xf000
+; VI-NEXT: s_mov_b32 s6, -1
+; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; VI-NEXT: s_endpgm
+; VI-NEXT: .LBB7_4:
+; VI-NEXT: s_mov_b64 s[6:7], -1
+; VI-NEXT: ; implicit-def: $sgpr0_sgpr1
+; VI-NEXT: s_branch .LBB7_2
entry:
%tmp0 = icmp eq i32 %cond, 0
br i1 %tmp0, label %if, label %else
@@ -151,25 +409,76 @@ endif:
ret void
}
-; FUNC-LABEL: {{^}}s_ctpop_i128:
-; GCN: s_bcnt1_i32_b64 [[SRESULT0:s[0-9]+]],
-; GCN: s_bcnt1_i32_b64 [[SRESULT1:s[0-9]+]],
-; GCN: s_add_i32 s{{[0-9]+}}, [[SRESULT1]], [[SRESULT0]]
-; GCN: s_endpgm
define amdgpu_kernel void @s_ctpop_i128(ptr addrspace(1) noalias %out, i128 %val) nounwind {
+; SI-LABEL: s_ctpop_i128:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb
+; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
+; SI-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
+; SI-NEXT: s_add_i32 s4, s4, s6
+; SI-NEXT: v_mov_b32_e32 v0, s4
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: s_ctpop_i128:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
+; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
+; VI-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
+; VI-NEXT: s_add_i32 s4, s4, s6
+; VI-NEXT: v_mov_b32_e32 v0, s4
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_endpgm
%ctpop = call i128 @llvm.ctpop.i128(i128 %val) nounwind readnone
%truncctpop = trunc i128 %ctpop to i32
store i32 %truncctpop, ptr addrspace(1) %out, align 4
ret void
}
-; FUNC-LABEL: {{^}}s_ctpop_i65:
-; GCN: s_and_b32
-; GCN: s_bcnt1_i32_b64 [[REG0:s[0-9]+]],
-; GCN: s_bcnt1_i32_b64 [[REG1:s[0-9]+]],
-; GCN: s_add_i32 {{s[0-9]+}}, [[REG0]], [[REG1]]
-; GCN: s_endpgm
define amdgpu_kernel void @s_ctpop_i65(ptr addrspace(1) noalias %out, i65 %val) nounwind {
+; SI-LABEL: s_ctpop_i65:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; SI-NEXT: s_load_dword s8, s[0:1], 0xd
+; SI-NEXT: s_mov_b32 s3, 0xf000
+; SI-NEXT: s_mov_b32 s2, -1
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_mov_b32 s0, s4
+; SI-NEXT: s_mov_b32 s1, s5
+; SI-NEXT: s_and_b32 s4, s8, 1
+; SI-NEXT: s_mov_b32 s5, 0
+; SI-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
+; SI-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
+; SI-NEXT: s_add_i32 s4, s6, s4
+; SI-NEXT: v_mov_b32_e32 v0, s4
+; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: s_ctpop_i65:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; VI-NEXT: s_load_dword s8, s[0:1], 0x34
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: s_mov_b32 s0, s4
+; VI-NEXT: s_mov_b32 s1, s5
+; VI-NEXT: s_and_b32 s4, s8, 1
+; VI-NEXT: s_mov_b32 s5, 0
+; VI-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
+; VI-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
+; VI-NEXT: s_add_i32 s4, s6, s4
+; VI-NEXT: v_mov_b32_e32 v0, s4
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_endpgm
%ctpop = call i65 @llvm.ctpop.i65(i65 %val) nounwind readnone
%truncctpop = trunc i65 %ctpop to i32
store i32 %truncctpop, ptr addrspace(1) %out, align 4
@@ -177,22 +486,49 @@ define amdgpu_kernel void @s_ctpop_i65(ptr addrspace(1) noalias %out, i65 %val)
}
; FIXME: Should not have extra add
-
-; FUNC-LABEL: {{^}}v_ctpop_i128:
-; SI: buffer_load_dwordx4 v[[[VAL0:[0-9]+]]:[[VAL3:[0-9]+]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64
-; VI: flat_load_dwordx4 v[[[VAL0:[0-9]+]]:[[VAL3:[0-9]+]]], v{{\[[0-9]+:[0-9]+\]}}
-
-; GCN-DAG: v_bcnt_u32_b32{{(_e64)*}} [[MIDRESULT0:v[0-9]+]], v{{[0-9]+}}, 0
-; GCN-DAG: v_bcnt_u32_b32{{(_e32)*(_e64)*}} [[MIDRESULT1:v[0-9]+]], v[[VAL3]], [[MIDRESULT0]]
-
-; GCN-DAG: v_bcnt_u32_b32{{(_e64)*}} [[MIDRESULT2:v[0-9]+]], v[[VAL0]], 0
-; GCN-DAG: v_bcnt_u32_b32{{(_e32)*(_e64)*}} [[MIDRESULT3:v[0-9]+]], v{{[0-9]+}}, [[MIDRESULT2]]
-
-; GCN: v_add_{{[iu]}}32_e32 [[RESULT:v[0-9]+]], vcc, [[MIDRESULT2]], [[MIDRESULT1]]
-
-; GCN: buffer_store_dword [[RESULT]],
-; GCN: s_endpgm
define amdgpu_kernel void @v_ctpop_i128(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) nounwind {
+; SI-LABEL: v_ctpop_i128:
+; SI: ; %bb.0:
+; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; SI-NEXT: s_mov_b32 s7, 0xf000
+; SI-NEXT: s_mov_b32 s10, 0
+; SI-NEXT: s_mov_b32 s11, s7
+; SI-NEXT: v_lshlrev_b32_e32 v0, 4, v0
+; SI-NEXT: s_waitcnt lgkmcnt(0)
+; SI-NEXT: s_mov_b64 s[8:9], s[2:3]
+; SI-NEXT: v_mov_b32_e32 v1, 0
+; SI-NEXT: buffer_load_dwordx4 v[0:3], v[0:1], s[8:11], 0 addr64
+; SI-NEXT: s_mov_b32 s6, -1
+; SI-NEXT: s_mov_b32 s4, s0
+; SI-NEXT: s_mov_b32 s5, s1
+; SI-NEXT: s_waitcnt vmcnt(0)
+; SI-NEXT: v_bcnt_u32_b32_e64 v2, v2, 0
+; SI-NEXT: v_bcnt_u32_b32_e64 v0, v0, 0
+; SI-NEXT: v_bcnt_u32_b32_e32 v2, v3, v2
+; SI-NEXT: v_bcnt_u32_b32_e32 v0, v1, v0
+; SI-NEXT: v_add_i32_e32 v0, vcc, v0, v2
+; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; SI-NEXT: s_endpgm
+;
+; VI-LABEL: v_ctpop_i128:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; VI-NEXT: v_lshlrev_b32_e32 v0, 4, v0
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v1, s3
+; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1]
+; VI-NEXT: s_mov_b32 s3, 0xf000
+; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_bcnt_u32_b32 v2, v2, 0
+; VI-NEXT: v_bcnt_u32_b32 v0, v0, 0
+; VI-NEXT: v_bcnt_u32_b32 v2, v3, v2
+; VI-NEXT: v_bcnt_u32_b32 v0, v1, v0
+; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2
+; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%in.gep = getelementptr i128, ptr addrspace(1) %in, i32 %tid
%val = load i128, ptr addrspace(1) %in.gep, align 8
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