[llvm] [SelectionDAG] Add computeKnownBits support for ISD::STEP_VECTOR (PR #80452)

[Philip Reames via llvm-commits]

================
@@ -3110,6 +3110,19 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
     }
     break;
   }
+  case ISD::STEP_VECTOR: {
+    const APInt &Step = Op.getConstantOperandAPInt(0);
+
+    if (Step.isPowerOf2())
+      Known.Zero.setLowBits(Step.logBase2());
+
+    const Function &F = getMachineFunction().getFunction();
+    const APInt MaxNumElts = getVScaleRange(&F, BitWidth).getUnsignedMax() *
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preames wrote:

I think in practice, the overflow will never happen for current targets.  The maximum value of vscale for AArch64 and RISCV is quite small and the maximum size of the vector isn't likely to be much larger than a m8 in practice.  Should definitely guard the case properly for future proofing though.  

https://github.com/llvm/llvm-project/pull/80452