[llvm] 2d1f5af - [AMDGPU] Reduce duplication in SOP instruction definitions. NFCI. (#80413)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 2 02:59:30 PST 2024
Author: Jay Foad
Date: 2024-02-02T10:59:26Z
New Revision: 2d1f5af8b0b07a4ac19eae699aa660debb1a5613
URL: https://github.com/llvm/llvm-project/commit/2d1f5af8b0b07a4ac19eae699aa660debb1a5613
DIFF: https://github.com/llvm/llvm-project/commit/2d1f5af8b0b07a4ac19eae699aa660debb1a5613.diff
LOG: [AMDGPU] Reduce duplication in SOP instruction definitions. NFCI. (#80413)
Use !tolower instead of repeating the name when defining a renamed Real
instruction.
Added:
Modified:
llvm/lib/Target/AMDGPU/SOPInstructions.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index ae5ef0541929b..37f9a4a3d234f 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -1970,13 +1970,15 @@ multiclass SOP1_Real_gfx11<bits<8> op> {
Select_gfx11<!cast<SOP1_Pseudo>(NAME).Mnemonic>;
}
-multiclass SOP1_Real_Renamed_gfx12<bits<8> op, SOP1_Pseudo backing_pseudo, string real_name> {
+multiclass SOP1_Real_Renamed_gfx12<bits<8> op, SOP1_Pseudo backing_pseudo> {
+ defvar real_name = !tolower(NAME);
def _gfx12 : SOP1_Real<op, backing_pseudo, real_name>,
Select_gfx12<backing_pseudo.Mnemonic>,
MnemonicAlias<backing_pseudo.Mnemonic, real_name>, Requires<[isGFX12Plus]>;
}
-multiclass SOP1_Real_Renamed_gfx11<bits<8> op, SOP1_Pseudo backing_pseudo, string real_name> {
+multiclass SOP1_Real_Renamed_gfx11<bits<8> op, SOP1_Pseudo backing_pseudo> {
+ defvar real_name = !tolower(NAME);
def _gfx11 : SOP1_Real<op, backing_pseudo, real_name>,
Select_gfx11<backing_pseudo.Mnemonic>,
MnemonicAlias<backing_pseudo.Mnemonic, real_name>, Requires<[isGFX11Only]>;
@@ -1985,9 +1987,9 @@ multiclass SOP1_Real_Renamed_gfx11<bits<8> op, SOP1_Pseudo backing_pseudo, strin
multiclass SOP1_Real_gfx11_gfx12<bits<8> op> :
SOP1_Real_gfx11<op>, SOP1_Real_gfx12<op>;
-multiclass SOP1_Real_Renamed_gfx11_gfx12<bits<8> op, SOP1_Pseudo backing_pseudo, string real_name> :
- SOP1_Real_Renamed_gfx11<op, backing_pseudo, real_name>,
- SOP1_Real_Renamed_gfx12<op, backing_pseudo, real_name>;
+multiclass SOP1_Real_Renamed_gfx11_gfx12<bits<8> op, SOP1_Pseudo backing_pseudo> :
+ SOP1_Real_Renamed_gfx11<op, backing_pseudo>,
+ SOP1_Real_Renamed_gfx12<op, backing_pseudo>;
defm S_MOV_B32 : SOP1_Real_gfx11_gfx12<0x000>;
defm S_MOV_B64 : SOP1_Real_gfx11_gfx12<0x001>;
@@ -1995,12 +1997,12 @@ defm S_CMOV_B32 : SOP1_Real_gfx11_gfx12<0x002>;
defm S_CMOV_B64 : SOP1_Real_gfx11_gfx12<0x003>;
defm S_BREV_B32 : SOP1_Real_gfx11_gfx12<0x004>;
defm S_BREV_B64 : SOP1_Real_gfx11_gfx12<0x005>;
-defm S_CTZ_I32_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x008, S_FF1_I32_B32, "s_ctz_i32_b32">;
-defm S_CTZ_I32_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x009, S_FF1_I32_B64, "s_ctz_i32_b64">;
-defm S_CLZ_I32_U32 : SOP1_Real_Renamed_gfx11_gfx12<0x00a, S_FLBIT_I32_B32, "s_clz_i32_u32">;
-defm S_CLZ_I32_U64 : SOP1_Real_Renamed_gfx11_gfx12<0x00b, S_FLBIT_I32_B64, "s_clz_i32_u64">;
-defm S_CLS_I32 : SOP1_Real_Renamed_gfx11_gfx12<0x00c, S_FLBIT_I32, "s_cls_i32">;
-defm S_CLS_I32_I64 : SOP1_Real_Renamed_gfx11_gfx12<0x00d, S_FLBIT_I32_I64, "s_cls_i32_i64">;
+defm S_CTZ_I32_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x008, S_FF1_I32_B32>;
+defm S_CTZ_I32_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x009, S_FF1_I32_B64>;
+defm S_CLZ_I32_U32 : SOP1_Real_Renamed_gfx11_gfx12<0x00a, S_FLBIT_I32_B32>;
+defm S_CLZ_I32_U64 : SOP1_Real_Renamed_gfx11_gfx12<0x00b, S_FLBIT_I32_B64>;
+defm S_CLS_I32 : SOP1_Real_Renamed_gfx11_gfx12<0x00c, S_FLBIT_I32>;
+defm S_CLS_I32_I64 : SOP1_Real_Renamed_gfx11_gfx12<0x00d, S_FLBIT_I32_I64>;
defm S_SEXT_I32_I8 : SOP1_Real_gfx11_gfx12<0x00e>;
defm S_SEXT_I32_I16 : SOP1_Real_gfx11_gfx12<0x00f>;
defm S_BITSET0_B32 : SOP1_Real_gfx11_gfx12<0x010>;
@@ -2031,18 +2033,18 @@ defm S_NOR_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x028>;
defm S_NOR_SAVEEXEC_B64 : SOP1_Real_gfx11_gfx12<0x029>;
defm S_XNOR_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x02a>;
/*defm S_XNOR_SAVEEXEC_B64 : SOP1_Real_gfx11_gfx12<0x02b>; //same as older arch, handled there*/
-defm S_AND_NOT0_SAVEEXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x02c, S_ANDN1_SAVEEXEC_B32, "s_and_not0_saveexec_b32">;
-defm S_AND_NOT0_SAVEEXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x02d, S_ANDN1_SAVEEXEC_B64, "s_and_not0_saveexec_b64">;
-defm S_OR_NOT0_SAVEEXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x02e, S_ORN1_SAVEEXEC_B32, "s_or_not0_saveexec_b32">;
-defm S_OR_NOT0_SAVEEXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x02f, S_ORN1_SAVEEXEC_B64, "s_or_not0_saveexec_b64">;
-defm S_AND_NOT1_SAVEEXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x030, S_ANDN2_SAVEEXEC_B32, "s_and_not1_saveexec_b32">;
-defm S_AND_NOT1_SAVEEXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x031, S_ANDN2_SAVEEXEC_B64, "s_and_not1_saveexec_b64">;
-defm S_OR_NOT1_SAVEEXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x032, S_ORN2_SAVEEXEC_B32, "s_or_not1_saveexec_b32">;
-defm S_OR_NOT1_SAVEEXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x033, S_ORN2_SAVEEXEC_B64, "s_or_not1_saveexec_b64">;
-defm S_AND_NOT0_WREXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x034, S_ANDN1_WREXEC_B32, "s_and_not0_wrexec_b32">;
-defm S_AND_NOT0_WREXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x035, S_ANDN1_WREXEC_B64, "s_and_not0_wrexec_b64">;
-defm S_AND_NOT1_WREXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x036, S_ANDN2_WREXEC_B32, "s_and_not1_wrexec_b32">;
-defm S_AND_NOT1_WREXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x037, S_ANDN2_WREXEC_B64, "s_and_not1_wrexec_b64">;
+defm S_AND_NOT0_SAVEEXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x02c, S_ANDN1_SAVEEXEC_B32>;
+defm S_AND_NOT0_SAVEEXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x02d, S_ANDN1_SAVEEXEC_B64>;
+defm S_OR_NOT0_SAVEEXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x02e, S_ORN1_SAVEEXEC_B32>;
+defm S_OR_NOT0_SAVEEXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x02f, S_ORN1_SAVEEXEC_B64>;
+defm S_AND_NOT1_SAVEEXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x030, S_ANDN2_SAVEEXEC_B32>;
+defm S_AND_NOT1_SAVEEXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x031, S_ANDN2_SAVEEXEC_B64>;
+defm S_OR_NOT1_SAVEEXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x032, S_ORN2_SAVEEXEC_B32>;
+defm S_OR_NOT1_SAVEEXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x033, S_ORN2_SAVEEXEC_B64>;
+defm S_AND_NOT0_WREXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x034, S_ANDN1_WREXEC_B32>;
+defm S_AND_NOT0_WREXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x035, S_ANDN1_WREXEC_B64>;
+defm S_AND_NOT1_WREXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x036, S_ANDN2_WREXEC_B32>;
+defm S_AND_NOT1_WREXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x037, S_ANDN2_WREXEC_B64>;
defm S_MOVRELS_B32 : SOP1_Real_gfx11_gfx12<0x040>;
defm S_MOVRELS_B64 : SOP1_Real_gfx11_gfx12<0x041>;
defm S_MOVRELD_B32 : SOP1_Real_gfx11_gfx12<0x042>;
@@ -2196,27 +2198,28 @@ multiclass SOP2_Real_gfx12<bits<7> op> {
Select_gfx12<!cast<SOP2_Pseudo>(NAME).Mnemonic>;
}
-multiclass SOP2_Real_Renamed_gfx12<bits<7> op, SOP2_Pseudo backing_pseudo, string real_name> {
+multiclass SOP2_Real_Renamed_gfx12<bits<7> op, SOP2_Pseudo backing_pseudo> {
+ defvar real_name = !tolower(NAME);
def _gfx12 : SOP2_Real32<op, backing_pseudo, real_name>,
Select_gfx12<backing_pseudo.Mnemonic>,
MnemonicAlias<backing_pseudo.Mnemonic, real_name>, Requires<[isGFX12Plus]>;
}
-defm S_MIN_NUM_F32 : SOP2_Real_Renamed_gfx12<0x042, S_MIN_F32, "s_min_num_f32">;
-defm S_MAX_NUM_F32 : SOP2_Real_Renamed_gfx12<0x043, S_MAX_F32, "s_max_num_f32">;
-defm S_MIN_NUM_F16 : SOP2_Real_Renamed_gfx12<0x04b, S_MIN_F16, "s_min_num_f16">;
-defm S_MAX_NUM_F16 : SOP2_Real_Renamed_gfx12<0x04c, S_MAX_F16, "s_max_num_f16">;
+defm S_MIN_NUM_F32 : SOP2_Real_Renamed_gfx12<0x042, S_MIN_F32>;
+defm S_MAX_NUM_F32 : SOP2_Real_Renamed_gfx12<0x043, S_MAX_F32>;
+defm S_MIN_NUM_F16 : SOP2_Real_Renamed_gfx12<0x04b, S_MIN_F16>;
+defm S_MAX_NUM_F16 : SOP2_Real_Renamed_gfx12<0x04c, S_MAX_F16>;
defm S_MINIMUM_F32 : SOP2_Real_gfx12<0x04f>;
defm S_MAXIMUM_F32 : SOP2_Real_gfx12<0x050>;
defm S_MINIMUM_F16 : SOP2_Real_gfx12<0x051>;
defm S_MAXIMUM_F16 : SOP2_Real_gfx12<0x052>;
-defm S_ADD_CO_U32 : SOP2_Real_Renamed_gfx12<0x000, S_ADD_U32, "s_add_co_u32">;
-defm S_SUB_CO_U32 : SOP2_Real_Renamed_gfx12<0x001, S_SUB_U32, "s_sub_co_u32">;
-defm S_ADD_CO_I32 : SOP2_Real_Renamed_gfx12<0x002, S_ADD_I32, "s_add_co_i32">;
-defm S_SUB_CO_I32 : SOP2_Real_Renamed_gfx12<0x003, S_SUB_I32, "s_sub_co_i32">;
-defm S_ADD_CO_CI_U32 : SOP2_Real_Renamed_gfx12<0x004, S_ADDC_U32, "s_add_co_ci_u32">;
-defm S_SUB_CO_CI_U32 : SOP2_Real_Renamed_gfx12<0x005, S_SUBB_U32, "s_sub_co_ci_u32">;
+defm S_ADD_CO_U32 : SOP2_Real_Renamed_gfx12<0x000, S_ADD_U32>;
+defm S_SUB_CO_U32 : SOP2_Real_Renamed_gfx12<0x001, S_SUB_U32>;
+defm S_ADD_CO_I32 : SOP2_Real_Renamed_gfx12<0x002, S_ADD_I32>;
+defm S_SUB_CO_I32 : SOP2_Real_Renamed_gfx12<0x003, S_SUB_I32>;
+defm S_ADD_CO_CI_U32 : SOP2_Real_Renamed_gfx12<0x004, S_ADDC_U32>;
+defm S_SUB_CO_CI_U32 : SOP2_Real_Renamed_gfx12<0x005, S_SUBB_U32>;
//===----------------------------------------------------------------------===//
// SOP2 - GFX11, GFX12.
@@ -2227,7 +2230,8 @@ multiclass SOP2_Real_gfx11<bits<7> op> {
Select_gfx11<!cast<SOP2_Pseudo>(NAME).Mnemonic>;
}
-multiclass SOP2_Real_Renamed_gfx11<bits<7> op, SOP2_Pseudo backing_pseudo, string real_name> {
+multiclass SOP2_Real_Renamed_gfx11<bits<7> op, SOP2_Pseudo backing_pseudo> {
+ defvar real_name = !tolower(NAME);
def _gfx11 : SOP2_Real32<op, backing_pseudo, real_name>,
Select_gfx11<backing_pseudo.Mnemonic>,
MnemonicAlias<backing_pseudo.Mnemonic, real_name>, Requires<[isGFX11Only]>;
@@ -2236,9 +2240,9 @@ multiclass SOP2_Real_Renamed_gfx11<bits<7> op, SOP2_Pseudo backing_pseudo, strin
multiclass SOP2_Real_gfx11_gfx12<bits<7> op> :
SOP2_Real_gfx11<op>, SOP2_Real_gfx12<op>;
-multiclass SOP2_Real_Renamed_gfx11_gfx12<bits<8> op, SOP2_Pseudo backing_pseudo, string real_name> :
- SOP2_Real_Renamed_gfx11<op, backing_pseudo, real_name>,
- SOP2_Real_Renamed_gfx12<op, backing_pseudo, real_name>;
+multiclass SOP2_Real_Renamed_gfx11_gfx12<bits<8> op, SOP2_Pseudo backing_pseudo> :
+ SOP2_Real_Renamed_gfx11<op, backing_pseudo>,
+ SOP2_Real_Renamed_gfx12<op, backing_pseudo>;
defm S_ABSDIFF_I32 : SOP2_Real_gfx11_gfx12<0x006>;
defm S_LSHL_B32 : SOP2_Real_gfx11_gfx12<0x008>;
@@ -2267,10 +2271,10 @@ defm S_NOR_B32 : SOP2_Real_gfx11_gfx12<0x01e>;
defm S_NOR_B64 : SOP2_Real_gfx11_gfx12<0x01f>;
defm S_XNOR_B32 : SOP2_Real_gfx11_gfx12<0x020>;
defm S_XNOR_B64 : SOP2_Real_gfx11_gfx12<0x021>;
-defm S_AND_NOT1_B32 : SOP2_Real_Renamed_gfx11_gfx12<0x022, S_ANDN2_B32, "s_and_not1_b32">;
-defm S_AND_NOT1_B64 : SOP2_Real_Renamed_gfx11_gfx12<0x023, S_ANDN2_B64, "s_and_not1_b64">;
-defm S_OR_NOT1_B32 : SOP2_Real_Renamed_gfx11_gfx12<0x024, S_ORN2_B32, "s_or_not1_b32">;
-defm S_OR_NOT1_B64 : SOP2_Real_Renamed_gfx11_gfx12<0x025, S_ORN2_B64, "s_or_not1_b64">;
+defm S_AND_NOT1_B32 : SOP2_Real_Renamed_gfx11_gfx12<0x022, S_ANDN2_B32>;
+defm S_AND_NOT1_B64 : SOP2_Real_Renamed_gfx11_gfx12<0x023, S_ANDN2_B64>;
+defm S_OR_NOT1_B32 : SOP2_Real_Renamed_gfx11_gfx12<0x024, S_ORN2_B32>;
+defm S_OR_NOT1_B64 : SOP2_Real_Renamed_gfx11_gfx12<0x025, S_ORN2_B64>;
defm S_BFE_U32 : SOP2_Real_gfx11_gfx12<0x026>;
defm S_BFE_I32 : SOP2_Real_gfx11_gfx12<0x027>;
defm S_BFE_U64 : SOP2_Real_gfx11_gfx12<0x028>;
@@ -2283,8 +2287,8 @@ defm S_MUL_HI_I32 : SOP2_Real_gfx11_gfx12<0x02e>;
defm S_CSELECT_B32 : SOP2_Real_gfx11_gfx12<0x030>;
defm S_CSELECT_B64 : SOP2_Real_gfx11_gfx12<0x031>;
defm S_PACK_HL_B32_B16 : SOP2_Real_gfx11_gfx12<0x035>;
-defm S_ADD_NC_U64 : SOP2_Real_Renamed_gfx12<0x053, S_ADD_U64, "s_add_nc_u64">;
-defm S_SUB_NC_U64 : SOP2_Real_Renamed_gfx12<0x054, S_SUB_U64, "s_sub_nc_u64">;
+defm S_ADD_NC_U64 : SOP2_Real_Renamed_gfx12<0x053, S_ADD_U64>;
+defm S_SUB_NC_U64 : SOP2_Real_Renamed_gfx12<0x054, S_SUB_U64>;
defm S_MUL_U64 : SOP2_Real_gfx12<0x055>;
//===----------------------------------------------------------------------===//
@@ -2421,7 +2425,8 @@ multiclass SOPK_Real32_gfx12<bits<5> op> {
Select_gfx12<!cast<SOPK_Pseudo>(NAME).Mnemonic>;
}
-multiclass SOPK_Real32_Renamed_gfx12<bits<5> op, SOPK_Pseudo backing_pseudo, string real_name> {
+multiclass SOPK_Real32_Renamed_gfx12<bits<5> op, SOPK_Pseudo backing_pseudo> {
+ defvar real_name = !tolower(NAME);
def _gfx12 : SOPK_Real32<op, backing_pseudo, real_name>,
Select_gfx12<backing_pseudo.Mnemonic>,
MnemonicAlias<backing_pseudo.Mnemonic, real_name>, Requires<[isGFX12Plus]>;
@@ -2448,7 +2453,7 @@ multiclass SOPK_Real32_gfx11_gfx12<bits<5> op> :
multiclass SOPK_Real64_gfx11_gfx12<bits<5> op> :
SOPK_Real64_gfx11<op>, SOPK_Real64_gfx12<op>;
-defm S_ADDK_CO_I32 : SOPK_Real32_Renamed_gfx12<0x00f, S_ADDK_I32, "s_addk_co_i32">;
+defm S_ADDK_CO_I32 : SOPK_Real32_Renamed_gfx12<0x00f, S_ADDK_I32>;
defm S_GETREG_B32 : SOPK_Real32_gfx11_gfx12<0x011>;
defm S_SETREG_B32 : SOPK_Real32_gfx11_gfx12<0x012>;
defm S_SETREG_IMM32_B32 : SOPK_Real64_gfx11_gfx12<0x013>;
@@ -2551,13 +2556,14 @@ multiclass SOPP_Real_32_gfx12<bits<7> op> {
SOPPRelaxTable<0, !cast<SOPP_Pseudo>(NAME).KeyName, "_gfx12">;
}
-multiclass SOPP_Real_32_Renamed_gfx12<bits<7> op, SOPP_Pseudo backing_pseudo, string real_name> {
+multiclass SOPP_Real_32_Renamed_gfx12<bits<7> op, SOPP_Pseudo backing_pseudo> {
+ defvar real_name = !tolower(NAME);
def _gfx12 : SOPP_Real_32<op, backing_pseudo, real_name>,
Select_gfx12<backing_pseudo.Mnemonic>,
MnemonicAlias<backing_pseudo.Mnemonic, real_name>, Requires<[isGFX12Plus]>;
}
-defm S_WAIT_ALU : SOPP_Real_32_Renamed_gfx12<0x008, S_WAITCNT_DEPCTR, "s_wait_alu">;
+defm S_WAIT_ALU : SOPP_Real_32_Renamed_gfx12<0x008, S_WAITCNT_DEPCTR>;
defm S_BARRIER_WAIT : SOPP_Real_32_gfx12<0x014>;
defm S_BARRIER_LEAVE : SOPP_Real_32_gfx12<0x015>;
defm S_WAIT_LOADCNT : SOPP_Real_32_gfx12<0x040>;
@@ -2593,7 +2599,8 @@ multiclass SOPP_Real_64_gfx11<bits<7> op> {
SOPPRelaxTable<1, !cast<SOPP_Pseudo>(NAME).KeyName, "_gfx11">;
}
-multiclass SOPP_Real_32_Renamed_gfx11<bits<7> op, SOPP_Pseudo backing_pseudo, string real_name> {
+multiclass SOPP_Real_32_Renamed_gfx11<bits<7> op, SOPP_Pseudo backing_pseudo> {
+ defvar real_name = !tolower(NAME);
def _gfx11 : SOPP_Real_32<op, backing_pseudo, real_name>,
Select_gfx11<backing_pseudo.Mnemonic>,
MnemonicAlias<backing_pseudo.Mnemonic, real_name>, Requires<[isGFX11Only]>;
@@ -2605,9 +2612,9 @@ multiclass SOPP_Real_32_gfx11_gfx12<bits<7> op> :
multiclass SOPP_Real_64_gfx11_gfx12<bits<7> op> :
SOPP_Real_64_gfx11<op>, SOPP_Real_64_gfx12<op>;
-multiclass SOPP_Real_32_Renamed_gfx11_gfx12<bits<7> op, SOPP_Pseudo backing_pseudo, string real_name> :
- SOPP_Real_32_Renamed_gfx11<op, backing_pseudo, real_name>,
- SOPP_Real_32_Renamed_gfx12<op, backing_pseudo, real_name>;
+multiclass SOPP_Real_32_Renamed_gfx11_gfx12<bits<7> op, SOPP_Pseudo backing_pseudo> :
+ SOPP_Real_32_Renamed_gfx11<op, backing_pseudo>,
+ SOPP_Real_32_Renamed_gfx12<op, backing_pseudo>;
multiclass SOPP_Real_With_Relaxation_gfx12<bits<7> op> {
defm "" : SOPP_Real_32_gfx12<op>;
@@ -2625,7 +2632,7 @@ multiclass SOPP_Real_With_Relaxation_gfx11_gfx12<bits<7>op> :
defm S_SETKILL : SOPP_Real_32_gfx11_gfx12<0x001>;
defm S_SETHALT : SOPP_Real_32_gfx11_gfx12<0x002>;
defm S_SLEEP : SOPP_Real_32_gfx11_gfx12<0x003>;
-defm S_SET_INST_PREFETCH_DISTANCE : SOPP_Real_32_Renamed_gfx11<0x004, S_INST_PREFETCH, "s_set_inst_prefetch_distance">;
+defm S_SET_INST_PREFETCH_DISTANCE : SOPP_Real_32_Renamed_gfx11<0x004, S_INST_PREFETCH>;
defm S_CLAUSE : SOPP_Real_32_gfx11_gfx12<0x005>;
defm S_DELAY_ALU : SOPP_Real_32_gfx11_gfx12<0x007>;
defm S_WAITCNT_DEPCTR : SOPP_Real_32_gfx11<0x008>;
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