[llvm] [JITLink][AArch32] Add TableGen Backend for Instr Encodings (PR #76996)

[Stefan Gränitz via llvm-commits]

weliveindetail wrote:

We discussed this in our last call. The approach is interesting and it would be great to integrate TableGen, but we are not sure about the details yet. In particular, it seems useful to have the specific byte-sequences at hand and easily discoverable. The TableGen approach will hide them from the code. For the moment we leave this here as a proposal for further consideration. Some situations to consider:

* in tests we write assembly to produce the expected opcodes: TableGen names are similar to assembly instructions, but not always obvious -- we still need to compare instruction bytes
* we often work with disassembly when debugging and compare instruction bytes
* instruction bytes are very relevant for reviews as well
* we must be able to match byte sequences for a range of instructions, for example B/B.W/BL/BLX (we'd need to combine TableGen results with bitwise operations)
* encode/decode functions are hand-written (and we probably want to keep that)

https://github.com/llvm/llvm-project/pull/76996