[llvm] [CodeGen] Return ArrayRef from TargetRegisterClass::getRegisters. NFCI. (PR #80411)

[Jay Foad via llvm-commits]

https://github.com/jayfoad created https://github.com/llvm/llvm-project/pull/80411

This will allow future patches to use indexing and methods like
drop_front on the result.


>From 4ff51049da695629447f8cc99f0476fdd9c44b01 Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Fri, 2 Feb 2024 09:54:21 +0000
Subject: [PATCH] [CodeGen] Return ArrayRef from
 TargetRegisterClass::getRegisters. NFCI.

This will allow future patches to use indexing and methods like
drop_front on the result.
---
 llvm/include/llvm/CodeGen/TargetRegisterInfo.h | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
index 75c482d7bcaa9..5098fc68df3b2 100644
--- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -81,9 +81,8 @@ class TargetRegisterClass {
   /// Return the number of registers in this class.
   unsigned getNumRegs() const { return MC->getNumRegs(); }
 
-  iterator_range<SmallVectorImpl<MCPhysReg>::const_iterator>
-  getRegisters() const {
-    return make_range(MC->begin(), MC->end());
+  ArrayRef<MCPhysReg> getRegisters() const {
+    return ArrayRef(begin(), getNumRegs());
   }
 
   /// Return the specified register in the class.
@@ -203,7 +202,7 @@ class TargetRegisterClass {
   ///
   /// By default, this method returns all registers in the class.
   ArrayRef<MCPhysReg> getRawAllocationOrder(const MachineFunction &MF) const {
-    return OrderFunc ? OrderFunc(MF) : ArrayRef(begin(), getNumRegs());
+    return OrderFunc ? OrderFunc(MF) : getRegisters();
   }
 
   /// Returns the combination of all lane masks of register in this class.