[llvm] [RFC] implement convergence control in MIR using SelectionDAG (PR #71785)

[Sameer Sahasrabuddhe via llvm-commits]

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@@ -1193,7 +1193,9 @@ EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
 
   // Run post-isel target hook to adjust this instruction if needed.
   if (II.hasPostISelHook())
-    TLI->AdjustInstrPostInstrSelection(*MIB, Node);
+    TLI->AdjustInstrPostInstrSelection(
+        *MIB, Node,
+        [this, &VRBaseMap](SDValue Op) { return getVR(Op, VRBaseMap); });
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ssahasra wrote:

Actually, the reason I went down this path is that `CONVERGENCECTRL_GLUE` is an AMDGPU opcode. I had started by thinking that glueing the token operand to an `SDNode` is a target-specific hack. But at this point, I am fairly confident that this scheme is suitable for all targets. That will simplify other places too, such as the callback passed to `AMDGPUTargetLowering::CollectTargetIntrinsicOperands()`.

As far as I can see, the token still has to be glued, and it eventually becomes an implicit use in the MIR. Otherwise a lot of convergent operations will need to be updated in the TD files.

https://github.com/llvm/llvm-project/pull/71785