[llvm] [RISCV] Add srmcfg CSR from Ssqosid extension. (PR #79914)

[Craig Topper via llvm-commits]

================
@@ -132,6 +132,11 @@ def : SysReg<"sip", 0x144>;
 let DeprecatedName = "sptbr" in
 def : SysReg<"satp", 0x180>;
 
+//===----------------------------------------------------------------------===//
+// Quality-of-Service(QoS) Identifiers (Ssqosid)
+//===----------------------------------------------------------------------===//
+def : SysReg<"srmcfg", 0x181>;
----------------
topperc wrote:

1. End of the paragraph at the beginning of Chapter 2.  

> The srmcfg register is an SXLEN-bit read/write register used to configure a Resource Control ID (RCID) and a Monitoring Counter ID (MCID). Both RCID and MCID are WARL fields. The register is
formatted as shown in Figure 1 when SXLEN=64 and Figure 2 when SXLEN=32. **The CSR number is
0x181**.

2. I don't think so. The only thing I know about is registers that have a high register for RV32.

https://github.com/llvm/llvm-project/pull/79914