[llvm] [AArch64][SVE2] Generate urshr rounding shift rights (PR #78374)

[Usman Nadeem via llvm-commits]

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@@ -20192,6 +20248,9 @@ static SDValue performIntrinsicCombine(SDNode *N,
   case Intrinsic::aarch64_sve_uqsub_x:
     return DAG.getNode(ISD::USUBSAT, SDLoc(N), N->getValueType(0),
                        N->getOperand(1), N->getOperand(2));
+  case Intrinsic::aarch64_sve_urshr:
+    return DAG.getNode(AArch64ISD::URSHR_I_PRED, SDLoc(N), N->getValueType(0),
+                       N->getOperand(1), N->getOperand(2), N->getOperand(3));
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UsmanNadeem wrote:

For naming I looked at a few other instructions that have similar behavior as `urshr`, i.e. inactive elements in the destination vector remain unmodified, and they were also named as `_PRED`.

I am quite new to the isel backend. Can you please explain what difference having a PatFrag would make compared to the code above?

https://github.com/llvm/llvm-project/pull/78374