[llvm] [clang] [RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (PR #79399)

[Craig Topper via llvm-commits]

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@@ -764,6 +771,62 @@ def FeatureStdExtSmepmp
     : SubtargetFeature<"smepmp", "HasStdExtSmepmp", "true",
                        "'Smepmp' (Enhanced Physical Memory Protection)", []>;
 
+def FeatureStdExtSsccptr
+    : SubtargetFeature<"ssccptr", "HasStdExtSsccptr", "true",
+                       "'Ssccptr' (Main memory supports page table reads)", []>;
+
+def FeatureStdExtShcounterenvw
+    : SubtargetFeature<"shcounterenw", "HasStdExtShcounterenw", "true",
+                       "'Shcounterenw' (Support writeable enables for any supproted counter)", []>;
+def FeatureStdExtSscounterenvw
+    : SubtargetFeature<"sscounterenw", "HasStdExtSscounterenw", "true",
+                       "'Sscounterenw' (Support writeable enables for any supproted counter)", []>;
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topperc wrote:

Thanks. I had taken the shorter text from the very end of https://github.com/riscv/riscv-profiles/blob/main/rva23-profile.adoc

https://github.com/llvm/llvm-project/pull/79399