[llvm] [CodeGen] [ARM] Make RISC-V Init Undef Pass Target Independent and add support for the ARM Architecture. (PR #77770)

[via llvm-commits]

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@@ -152,7 +118,7 @@ bool RISCVInitUndef::handleReg(MachineInstr *MI) {
       continue;
     if (!UseMO.getReg().isVirtual())
       continue;
-    if (!isVectorRegClass(UseMO.getReg()))
+    if (!TII->isVectorRegClass(MRI->getRegClass(UseMO.getReg())))
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ostannard wrote:

Yes, I think it would be better to delete this check, as the register class shouldn't change whether that transformation is necessary or not. My main concern here is that there's actually some other condition, and the original RISC-V implementation was using this as a proxy for it which happened to be correct for RISC-V, but not in general. Removing the condition and running the tests seems like a good way to check that.

https://github.com/llvm/llvm-project/pull/77770